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131. 发明授权

US06492269B1 Methods for edge alignment mark protection during damascene electrochemical plating of copper 有权
标题翻译：铜镶嵌电镀过程中边缘对准标记保护方法
公开(公告)号：US06492269B1
公开(公告)日：2002-12-10
申请号：US09755570
申请日：2001-01-08
申请人： Chung-Shi Liu , Shau-Lin Shue , Chen-Hua Yu , Ching-Hua Hsieh
发明人： Chung-Shi Liu , Shau-Lin Shue , Chen-Hua Yu , Ching-Hua Hsieh
IPC分类号： H01L2144
CPC分类号： H01L21/2885 , H01L21/76877 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/54493 , H01L2924/0002 , H01L2924/00
摘要： This invention relates to a method of fabrication for metal wiring used in semiconductor integrated circuit devices, and more specifically, to a copper plating method, whereby the wafer edge alignment marks for subsequent processing steps are protected from being covered by copper deposition by two methods: the first method being that of forming alignment mark shields at the wafer's edge, thus preventing both barrier and copper seed layers from being deposited in those regions; the second method being that of forming small pad-like extrusions at the contact ring of the copper plating fixture, thus preventing copper plating at the contact points. In the first method, an alignment mark shield Is utilized to cover the alignment mark areas, near the edge of the wafer, with a mechanical shield. This shield protects the alignment mark regions from film deposition during the sputter deposition steps of barrier and copper seed layers. The alignment marks are left without a copper seed layer, hence preventing copper deposition in these regions during copper electroplating. In the second method, the alignment mark areas, near the edge of the wafer, are protected from copper electroplating deposition by use of small pad-like extrusions positioned at copper plating contact ring. The pad-like extrusion is part of the contact ring and prevents copper buildup and deposition on the alignment mark.
摘要翻译：本发明涉及一种用于半导体集成电路器件的金属布线的制造方法，更具体地说，涉及一种镀铜方法，由此通过两种方法保护用于后续处理步骤的晶片边缘对准标记不被铜沉积覆盖：第一种方法是在晶片边缘处形成对准标记屏蔽，从而防止屏障和铜种子层沉积在那些区域中; 第二种方法是在镀铜夹具的接触环处形成小的垫状挤压件，从而防止接触点处的镀铜。在第一种方法中，使用对准标记屏蔽来利用机械屏蔽覆盖晶片边缘附近的对准标记区域。在屏障和铜种子层的溅射沉积步骤期间，该屏蔽件保护对准标记区域免受膜沉积。留下对准标记没有铜种子层，因此在铜电镀期间防止这些区域中的铜沉积。在第二种方法中，通过使用位于铜电镀接触环的小的垫状突出部，在晶片的边缘附近的对准标记区域被保护以避免铜电镀沉积。垫状挤出物是接触环的一部分，可防止铜对准标记上的积累和沉积。

132. 发明授权

US06395642B1 Method to improve copper process integration 有权
标题翻译：改善铜工艺整合的方法
公开(公告)号：US06395642B1
公开(公告)日：2002-05-28
申请号：US09473032
申请日：1999-12-28
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L21302
CPC分类号： C25D5/34 , C25D7/123
摘要： A method is disclosed to improve copper process integration in the forming copper interconnects in integrated circuits. This is accomplished by integrating the process of forming a copper seed layer in an interconnect structure such as a trench or a groove, with the process of plasma cleaning of the structure prior to the electroplating of copper into the trench. NH3 plasma can be used for this purpose. Or, H2/N2 thermal reduction can also be employed. The integrated process promotes well-controlled electro-chemical deposition (ECD) of copper for solid filling of the trench.
摘要翻译：公开了一种改进集成电路中形成铜互连的铜工艺集成的方法。这通过将铜晶种层形成在诸如沟槽或沟槽的互连结构中的过程与在电镀铜到沟槽之前对结构进行等离子体清洁的过程来实现。 NH3等离子体可用于此目的。或者也可以使用H 2 / N 2热还原。整合过程促进铜的良好控制的电化学沉积（ECD），用于固体填充沟槽。

133. 发明授权

US06387800B1 Method of forming barrier and seed layers for electrochemical deposition of copper 有权
标题翻译：形成铜的电化学沉积的阻挡层和种子层的方法
公开(公告)号：US06387800B1
公开(公告)日：2002-05-14
申请号：US09467117
申请日：1999-12-20
申请人： Chung-Shi Liu , Shau-Lin Shue
发明人： Chung-Shi Liu , Shau-Lin Shue
IPC分类号： H01L2144
CPC分类号： H01L21/76874 , H01L21/2855 , H01L21/2885 , H01L21/76843 , H01L21/76877
摘要： A process in the fabrication of integrated circuits has been developed for copper diffusion barrier layer and copper seed layer. The invention teaches a method of combining ion metal plasma (IMP) deposition techniques, i.e., with and without AC/Rf bias, in a series of steps or cycles (of at least four or more cycles depending on device geometry), of AC/Rf bias “ON”, AC/Rf bias “OFF”, to form both the copper metal diffusion barrier (reactive IMP) and then subsequently, the copper seed layer. The current invention applies to lining both a single and dual damascene structure to form a copper metal barrier layer, TaN, and copper seed layer for interconnects and vias prior to electrochemical deposition (ECD) of copper.
摘要翻译：已经开发了用于铜扩散阻挡层和铜种子层的集成电路制造工艺。本发明教导了一种将离子金属等离子体（IMP）沉积技术（即，具有和不具有AC / Rf偏压）组合在一系列步骤或循环（至少四个或更多个周期，取决于器件几何形状））的方法，AC / Rf偏压“ON”，AC / Rf偏压“OFF”，以形成铜金属扩散阻挡层（反应性IMP），然后形成铜种子层。本发明适用于单层和双镶嵌结构，以在铜的电化学沉积（ECD）之前形成用于互连和通孔的铜金属阻挡层，TaN和铜籽晶层。

134. 发明授权

US06372645B1 Methods to reduce metal bridges and line shorts in integrated circuits 有权
标题翻译：降低集成电路中金属桥和线路短路的方法
公开(公告)号：US06372645B1
公开(公告)日：2002-04-16
申请号：US09439367
申请日：1999-11-15
申请人： Chung-Shi Liu , Shau-Lin Shue , Chen-Hua Yu , Shih-Chi Lin , Ming-Jer Lee , Ying-Lang Wang , Yu-Ku Lin
发明人： Chung-Shi Liu , Shau-Lin Shue , Chen-Hua Yu , Shih-Chi Lin , Ming-Jer Lee , Ying-Lang Wang , Yu-Ku Lin
IPC分类号： H01L2144
CPC分类号： H01L21/76838 , H01L21/32051
摘要： In the first option of the present invention, a semiconductor structure is provided and an overlying titanium nitride barrier layer is deposited thereon at about 100° C. At least Al and Cu is sputtered over the titanium nitride barrier layer from about 270 to 300° C. to form an Al—Cu alloy containing metal layer. The sputtered Al—Cu alloy containing metal layer is promptly cooled at a cooling rate greater than about 100° C./minute to a temperature below 200° C. to form a Al—Cu alloy containing metal layer having minimal CuAl2 grain growth. The semiconductor structure is removed from the cooling chamber and the semiconductor structure is processed further below 200° C. to form semiconductor device precursors. In the second option of the present invention, a semiconductor structure having an overlying barrier layer is provided. At least Al and Cu is sputtered over the barrier layer at a first temperature to form an Al—Cu alloy containing metal layer having CuAl2 grains of a first average size. The semiconductor structure is processed and then heated to a second temperature to dissolve the CuAl2 grains of a first average size then rapidly cooling to a third temperature whereby the CuAl2 grains formed have a second average size within the Al—Cu alloy containing metal layer. The second average size CuAl2 grains being less than the first average size CuAl2 grains.
摘要翻译：在本发明的第一种选择中，提供了一种半导体结构，并在其上沉积了大约100℃的上覆氮化钛阻挡层。至少Al和Cu溅射在氮化钛阻挡层上约270-300℃ 以形成含有金属层的Al-Cu合金。将溅射的含有Al-Cu合金的金属层以大于约100℃/分钟的冷却速度迅速冷却到低于200℃的温度，以形成含有最小CuAl 2晶粒生长的金属层的Al-Cu合金。将半导体结构从冷却室中移除，半导体结构进一步在200℃以下进行处理以形成半导体器件前体。在本发明的第二个选择中，提供了具有上覆阻挡层的半导体结构。在第一温度下至少将Al和Cu溅射在阻挡层上，以形成含有具有第一平均尺寸的CuAl 2晶粒的金属层的Al-Cu合金。将半导体结构加工，然后加热至第二温度以溶解第一平均尺寸的CuAl 2晶粒，然后快速冷却至第三温度，由此形成的CuAl 2晶粒在含有Al-Cu合金的金属层内具有第二平均尺寸。第二平均尺寸CuAl2晶粒小于第一平均尺寸CuAl2晶粒。

135. 发明授权

US06350688B1 Via RC improvement for copper damascene and beyond technology 有权
标题翻译：通过RC改进铜大马士革和超越技术
公开(公告)号：US06350688B1
公开(公告)日：2002-02-26
申请号：US09629646
申请日：2000-08-01
申请人： Chung-Shi Liu , Shau-Lin Shue , Chen-Hua Yu
发明人： Chung-Shi Liu , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L2144
CPC分类号： H01L21/76886 , C25D5/48 , C25D5/50 , C25D7/123 , H01L21/76877
摘要： A new anneal procedure is provided that is applied to copper damascene via interconnects after copper ECP deposition and prior to copper planarization.
摘要翻译：提供了一种新的退火方法，通过铜ECP沉积之后和铜平坦化之前通过互连应用于铜镶嵌层。

136. 发明授权

US06287966B1 Low sheet resistance of titanium salicide process 失效
标题翻译：钛硅化物工艺的低表面电阻
公开(公告)号：US06287966B1
公开(公告)日：2001-09-11
申请号：US09303835
申请日：1999-05-03
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L214763
CPC分类号： H01L21/28052 , H01L21/28273 , H01L21/28518 , H01L29/665
摘要： A method for establishing low sheet resistance for the Titanium Salicide process that teaches a C-54 TiSix process by means of an additional vacuum bake. The present invention teaches an additional vacuum bake step prior to pre-metal HF dip during the Si-ion mixing process, an additional vacuum bake step prior to PAI during the PAI process, an additional vacuum bake step prior to pre-metal HF dip during the PAI process.
摘要翻译：一种通过额外的真空烘烤教导C-54 TiSix工艺的用于制备用于Titanium Salicide工艺的低薄层电阻的方法。本发明教导了在Si离子混合过程中在金属前HF浸渍之前的另外的真空烘烤步骤，PAI过程之前的PAI之前的另外的真空烘烤步骤，在金属前HF浸渍之前的另外的真空烘烤步骤 PAI过程。

137. 发明授权

US06271136B1 Multi-step plasma process for forming TiSiN barrier 有权
标题翻译：用于形成TiSiN屏障的多步等离子体工艺
公开(公告)号：US06271136B1
公开(公告)日：2001-08-07
申请号：US09542809
申请日：2000-04-04
申请人： Shau-Lin Shue , Chung-Shi Liu
发明人： Shau-Lin Shue , Chung-Shi Liu
IPC分类号： H01L2144
CPC分类号： H01L21/76873 , C23C16/34 , C23C16/56 , H01L21/28556 , H01L21/76843 , H01L21/76856 , H01L21/76862
摘要： This invention relates to a robust method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of an improved copper metal diffusion barrier layer, TiSiN, by a combination of metal-organic chemical vapor deposition (MOCVD) and multi-step plasma treatment that improves the diffusion resistant properties of the barrier layer (at both interfaces or surfaces) for both copper and silicon diffusion, in a single and dual damascene process, to fabricate reliable metal interconnects and contact vias. After a metal-organic chemical vapor deposition (MOCVD) to form TiNxCyOz, TiCxNyHz complexes, a multi-step plasma treatment follows. The first plasma treatment bombards the surface with nitrogen and hydrogen ions to reduce the complexes to TiN. The TiN barrier layer is then treated with an enhanced plasma deposition by using silane and bombarding the surface with silicon ions. The net result is the formation of a TiSiN film with improved diffusion resistance.
摘要翻译：本发明涉及用于半导体集成电路器件的坚固的制造方法，更具体地涉及通过金属有机化学气相沉积（MOCVD）和多步骤的组合形成改进的铜金属扩散阻挡层TiSiN 在单个和双镶嵌工艺中改善铜和硅扩散的阻挡层（在两个界面或表面处）的扩散阻力特性的等离子体处理，以制造可靠的金属互连和接触通孔。经金属有机化学气相沉积（MOCVD）形成TiNxCyOz，TiCxNyHZ配合物后，进行多步等离子体处理。第一次等离子体处理用氮和氢离子轰击表面，以减少与TiN的配合物。然后通过使用硅烷和用硅离子轰击表面，通过增强的等离子体沉积处理TiN阻挡层。最终的结果是形成具有改善的扩散阻力的TiSiN膜。

138. 发明授权

US06225223B1 Method to eliminate dishing of copper interconnects 有权
标题翻译：消除铜互连凹陷的方法
公开(公告)号：US06225223B1
公开(公告)日：2001-05-01
申请号：US09374297
申请日：1999-08-16
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L2144
CPC分类号： H01L21/7684
摘要： A method of forming an interconnect, comprising the following steps. A dielectric layer, having an upper surface, is formed over a semiconductor structure. A trench, having side walls and a bottom, is formed within the dielectric layer. A barrier layer is then formed over the dielectric layer and lining the trench's side walls and bottom. A first copper layer is deposited on the barrier layer, filling the lined trench and blanket filling the barrier layer covered dielectric layer. The first copper layer is planarized, exposing the upper surface of the dielectric layer and forming a dished copper filled trench. A second copper layer is selectively deposited on the dished copper filled trench by either electroless plating or chemical vapor deposition (CVD). The second copper layer extending above the upper surface of the dielectric layer. The second copper layer is then planarized to form an essentially planar copper filled trench, or interconnect, level with the upper surface of said dielectric layer.
摘要翻译：一种形成互连的方法，包括以下步骤。具有上表面的介电层形成在半导体结构之上。具有侧壁和底部的沟槽形成在电介质层内。然后在电介质层上形成阻挡层，并衬在沟槽的侧壁和底部。第一铜层沉积在阻挡层上，填充衬里的沟槽并覆盖填充阻挡层覆盖的电介质层。第一铜层被平坦化，暴露电介质层的上表面并形成填充有铜的沟槽。通过无电镀或化学气相沉积（CVD），第二铜层选择性地沉积在带有填充铜的填充沟槽上。第二铜层延伸到电介质层的上表面之上。然后将第二铜层平坦化以形成与所述电介质层的上表面基本上平面的铜填充沟槽或互连级。

139. 发明授权

US06181013B2 Method for selective growth of Cu3Ge or Cu5Si for passivation of damascene copper structures and device manufactured thereby 有权
标题翻译：选择性生长Cu3Ge或Cu5Si用于钝化镶嵌铜结构的方法及其制造的器件
公开(公告)号：US06181013B2
公开(公告)日：2001-01-30
申请号：US09524521
申请日：2000-03-13
申请人： Chung-Shi Liu , Chen-Hua Yu , Tien-I Bao , Syun-Ming Jang
发明人： Chung-Shi Liu , Chen-Hua Yu , Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L2348
CPC分类号： H01L21/76867 , H01L21/7684 , H01L21/76849
摘要： Form a dielectric layer on a surface of a conductive substrate with a trench through the top surface down to the substrate. Form a barrier layer over the dielectric layer including the exposed surface of the conductive substrate and the exposed sidewalls of the dielectric layer. Form a copper conductor over the barrier layer and overfilling the narrow hole in the trench. Etch away material from the surface of the copper conductor by a CMP process lowering the copper leaving a thin layer of copper over the barrier layer above the dielectric layer aside from the hole. Form a copper passivation by combining an element selected from silicon and germanium with copper on the exposed surfaces of the copper surfaces forming an interface in the narrower hole between the copper and the copper compound located below the dielectric top level. Etch away material from the surface of the copper compound and the barrier layer to planarize the copper compound by etching down to the dielectric top level leaving a thin layer of the copper passivation compound covering the copper conductor in the narrower hole.
摘要翻译：在具有沟槽的导电基底的表面上形成电介质层，通过顶表面向下延伸到衬底。在包括导电基板的暴露表面和电介质层的暴露的侧壁的电介质层上形成阻挡层。在阻挡层上形成一个铜导体，并且填充沟槽中的窄孔。通过CMP工艺从铜表面蚀刻掉材料，在除了孔之外的电介质层之上的阻挡层上方，降低铜，从而留下薄的铜层。通过将选自硅和锗的元素与铜的暴露表面上的铜组合形成铜钝化，在铜和化合物之间的较窄的孔中形成界面，位于电介质顶层之下。从铜化合物的表面和阻挡层的表面蚀刻掉材料以通过蚀刻到电介质顶部水平来平坦化铜化合物，留下覆盖较窄孔中的铜导体的铜钝化化合物的薄层。

140. 发明授权

US6143657A Method of increasing the stability of a copper to copper interconnection process and structure manufactured thereby 有权
标题翻译：提高铜与铜互连工艺的稳定性的方法和由此制造的结构
公开(公告)号：US6143657A
公开(公告)日：2000-11-07
申请号：US225063
申请日：1999-01-04
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44 , H01L29/43
CPC分类号： H01L21/76867 , H01L21/76805 , H01L21/76843 , H01L21/76879 , H01L23/5226 , H01L23/532 , H01L23/53238 , H01L2924/0002 , Y10S257/915
摘要： A via is formed between a copper conductor and a second copper conductor in a thin film electronic device with a copper plug interconnecting the copper conductor and the second copper conductor. Form a stop layer over the first copper conductor and a dielectric layer over the stop layer. Pattern the dielectric and etch stop layers by etching a hole therethrough down into a copper conductor leaving an exposed surface of the copper conductor and exposed sidewalls of the dielectric layer and the etch stop layer. Grow a copper germanide (Cu.sub.3 Ge) compound, thin film at the base of the hole on the exposed surface of the copper conductor from exposure to germane GeH.sub.4 gas. Form a barrier layer over the copper germanide (Cu.sub.3 Ge) compound, thin film, the dielectric layer and the first copper conductor. The barrier layer forms a via hole in the hole. Form a second copper conductor including the copper plug over the barrier layer, the copper plug filling the narrow via hole.
摘要翻译：在具有将铜导体和第二铜导体互连的铜插头的薄膜电子器件中的铜导体和第二铜导体之间形成通孔。在第一铜导体上形成停止层，在停止层上形成介电层。通过将孔向下蚀刻到铜导体中来形成电介质和蚀刻停止层，留下铜导体的暴露表面和介电层和蚀刻停止层的暴露的侧壁。在铜导体的暴露表面上的孔的底部生长出锗化锗（Cu3Ge）复合物，暴露于锗锗GeH4气体中的薄膜。在铜锗化合物（Cu3Ge）化合物，薄膜，电介质层和第一铜导体上形成阻挡层。阻挡层在孔中形成通孔。在阻挡层上形成包括铜塞的第二铜导体，铜塞填充窄通孔。

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