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121. 发明申请

US20160233871A1 JITTER-BASED CLOCK SELECTION 有权
标题翻译：基于JITTER的时钟选择
公开(公告)号：US20160233871A1
公开(公告)日：2016-08-11
申请号：US15130802
申请日：2016-04-15
申请人： Rambus Inc.
发明人： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
IPC分类号： H03L7/16 , H03K3/03 , H03L7/24 , H03K5/00 , H03K5/14
CPC分类号： H03L7/16 , H03J2200/10 , H03K3/0315 , H03K5/00006 , H03K5/13 , H03K5/14 , H03L7/06 , H03L7/0995 , H03L7/24
摘要： In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
摘要翻译：在第一时钟频率倍增器中，具有光谱交错锁定范围的多个注入锁定振荡器（ILO）并行操作，以实现基本上比孤立的国际劳工组织的输入频率范围更宽的集体输入频率范围。在每个输入频率变化之后，可以根据一个或多个限定条件评估国际劳工组织输出时钟，以选择其中一个ILO作为最终的时钟源。在第二个时钟倍频器中，灵活注入速率的注入锁定振荡器锁定到超谐波，次谐波或全频率注入脉冲，在不同的注入脉冲速率之间无缝转换，以实现宽的输入频率范围。响应于输入时钟由第一和/或第二时钟频率乘法器影响的倍频因子在飞行中确定，然后与编程的（期望的）乘法因子进行比较，以在频率乘法器的不同分频实例之间进行选择时钟。

122. 发明授权

US09281823B2 Single insertion trimming of highly accurate reference oscillators 有权
公开(公告)号：US09281823B2
公开(公告)日：2016-03-08
申请号：US14183799
申请日：2014-02-19
申请人： Si-Ware Systems
发明人： Ahmed Elkholy , Ayman Ahmed
IPC分类号： H03L1/04 , H03L7/085 , H03L1/02 , H03L7/099 , H03L7/16
CPC分类号： H03L1/026 , H03L1/027 , H03L1/04 , H03L7/085 , H03L7/091 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/06 , H03L2207/50
摘要： A highly integrated monolithic self-compensated oscillator (SCO) with high frequency stability versus temperature variations is described, together with a cost effective single insertion point trimming (SPT) algorithm. The SPT is utilized to adjust the phase and frequency of the SCO to meet frequency stability versus temperature and frequency accuracy requirements for a reference clock. The techniques used in the SPT algorithm provide a robust, fast and low testing cost for the SCO. Moreover, the concepts and techniques utilized in the SCO SPT can be used effectively for any temperature compensated oscillator (TCO) including TCXO, MEMS, FBAR and RC oscillators. Additionally, the described SPT algorithm is capable of measuring the temperature sensitivity of any oscillator, estimating suitable temperature compensation parameters and adjusting the oscillator frequency to the required value simultaneously.

123. 发明授权

US09231753B2 Low power oversampling with reduced-architecture delay locked loop 有权
标题翻译：低功耗过采样与减少架构延迟锁定环路
公开(公告)号：US09231753B2
公开(公告)日：2016-01-05
申请号：US14326657
申请日：2014-07-09
申请人： Intel Corporation
发明人： Wei-Lien Yang
IPC分类号： H03L7/06 , H04L7/00 , H04L25/49 , H03L7/081 , H03L7/16
CPC分类号： H04L7/0037 , H03L7/0818 , H03L7/16 , H04L25/4902
摘要： In one embodiment, an apparatus including a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.
摘要翻译：在一个实施例中，一种装置，包括相位检测器单元，用于确定反相参考时钟信号和反馈时钟信号之间的相位差。该装置还包括一个控制器单元，用于根据相位差产生延迟信号。该装置还包括一组电压控制延迟线，以基于延迟信号产生相位输出，其中相位输出由该装置提供给时钟发生器单元，以产生用于由接收器进行数据恢复的过采样时钟信号。

124. 发明授权

US09214947B2 Phase-lock in all-digital phase-locked loops 有权
标题翻译：全锁相环锁相环
公开(公告)号：US09214947B2
公开(公告)日：2015-12-15
申请号：US13770083
申请日：2013-02-19
申请人： Intel Mobile Communications GmbH
发明人： Stefan Mendel
IPC分类号： H03L7/085 , H03L7/099 , H03L7/18 , H03L7/095 , H03L7/10 , H03L7/16
CPC分类号： H03L7/16 , H03L7/095 , H03L7/099 , H03L7/104 , H03L7/18 , H03L2207/50
摘要： This disclosure relates to an all digital phase-lock loop (ADPLL). The ADPLL determines an error generated by a digitally controlled oscillator (DCO) which is operated using a tuning word, stores information related to the error, and compensates for the error based on the stored information.
摘要翻译：本公开涉及全数字锁相环（ADPLL）。 ADPLL确定由使用调谐字操作的数控振荡器（DCO）产生的错误，存储与错误有关的信息，并且基于存储的信息来补偿错误。

125. 发明授权

US09194946B1 Combined FMCW and FM pulse-compression radar systems and methods 有权
标题翻译：联合FMCW和FM脉冲压缩雷达系统和方法
公开(公告)号：US09194946B1
公开(公告)日：2015-11-24
申请号：US13625767
申请日：2012-09-24
申请人： Honeywell International Inc.
发明人： David C. Vacanti
IPC分类号： G01S13/32 , G01S13/53 , G01S13/58 , H03L7/16 , H03L7/06
CPC分类号： G01S13/28 , G01S13/286 , G01S13/32 , G01S13/9307 , H03L2207/06
摘要： Systems and methods for providing an efficient radar system that can operate at both near and far ranges. An exemplary radar system includes a controller that generates a clock signal and a mode signal, a transmitter with a synthesizer, and a dual-mode transmitter. The synthesizer and the transmitter generate a signal in a first or a second mode (frequency ranges) based on the clock or mode signals. An antenna transmits the generated signal and receives a return signal based on the transmitted signal. A receiver processes the received return signal according to the first or second mode, based on the generated at least one clock signal or mode signal. A processor determines existence of a target included in the processed return signal. An output device (such as a display device) outputs a presentation based on the determination. The system operates in FMCW or pulse modes.
摘要翻译：用于提供可在近距离和远距离范围内操作的有效雷达系统的系统和方法。示例性雷达系统包括产生时钟信号和模式信号的控制器，具有合成器的发射机和双模发射机。合成器和发射机基于时钟或模式信号在第一或第二模式（频率范围）中产生信号。天线发送所生成的信号并基于发送的信号接收返回信号。接收机根据所生成的至少一个时钟信号或模式信号，根据第一或第二模式处理所接收的返回信号。处理器确定包括在处理的返回信号中的目标的存在。输出装置（诸如显示装置）基于该确定输出演示。系统以FMCW或脉冲模式工作。

126. 发明授权

US09160396B2 LO generation and distribution in a multi-band transceiver 有权
标题翻译： LO生成和分配在多频带收发器中
公开(公告)号：US09160396B2
公开(公告)日：2015-10-13
申请号：US14042129
申请日：2013-09-30
申请人： QUALCOMM Incorporated
发明人： Babak Soltanian , Jafar Savoj
IPC分类号： H04B1/40 , H03L7/099 , H03L7/10 , H03L7/16 , H03L7/193 , H03L7/197 , H04B1/00
CPC分类号： H04B1/40 , H03L7/099 , H03L7/104 , H03L7/16 , H03L7/193 , H03L7/1976 , H04B1/0082
摘要： A VCO of a PLL outputs a first differential signal of frequency FVCO. A first divide-by-two circuit local to the VCO divides the first differential signal and outputs a first quadrature signal of frequency FVCO/2. Two of the component signals of the first quadrature signal are routed to a second divide-by-two circuit local to a first mixer of a first device. The second divide-by-two circuit outputs a second quadrature signal of frequency FVCO/4 to the first mixer. All four signals of the first quadrature signal of frequency FVCO/2 are routed through phase mismatch correction circuitry to a second mixer of a second device. In one example, FVCO is a tunable frequency of about ten gigahertz, the first device is an IEEE802.11b/g transmitter or receiver that transmits or receives in a first band, and the second device is an IEEE 802.11a transmitter or receiver that transmits or receives in a second band.
摘要翻译： PLL的VCO输出频率为FVCO的第一差分信号。第一差分信号分频到VCO的局部区域，并输出频率为FVCO / 2的第一正交信号。第一正交信号的分量信号中的两个被路由到第一设备的第一混频器本地的第二分频电路。第二分频电路向第一混频器输出频率为FVCO / 4的第二正交信号。频率为FVCO / 2的第一正交信号的所有四个信号通过相位失配校正电路被路由到第二装置的第二混频器。在一个示例中，FVCO是大约十千兆赫兹的可调谐频率，第一设备是在第一频带中发送或接收的IEEE802.11b / g发射机或接收机，第二设备是发射或接收的IEEE 802.11a发射机或接收机或接收在第二频带。

127. 发明授权

US09130737B1 Signal-generating circuit and wireless communication device 有权
标题翻译：信号发生电路和无线通信装置
公开(公告)号：US09130737B1
公开(公告)日：2015-09-08
申请号：US14610271
申请日：2015-01-30
申请人： Panasonic Corporation
发明人： Koji Takinami , Takayuki Tsukizawa , Kenji Miyanaga , Shunsuke Hirano
IPC分类号： H03D3/24 , H04L7/033 , H04B1/405 , H04B1/00 , H03L7/18 , H03L7/193 , H03L7/16
CPC分类号： H03L7/16 , H03L7/18 , H03L7/193 , H04B1/403 , H04B1/408
摘要： A signal-generating circuit includes a voltage-controlled oscillator that generates an oscillated signal; a first frequency divider that generates a first divided signal by dividing the oscillated signal; a second frequency divider that generates a second divided signal by dividing the divided signal; a phase comparator that receives as input the second divided signal and a reference signal and outputs two signals corresponding to a phase difference therebetween; a loop filter that extracts a low frequency signal between the two signals to be output to the voltage-controlled oscillator; a third frequency divider that generates a third divided signal by dividing the first divided signal; a first frequency converter that generates a first frequency converted signal by multiplying the oscillated signal by the third divided signal; and a first multiplier that generates a multiplied signal by multiplying the first frequency converted signal by a first multiplication number.
摘要翻译：信号发生电路包括产生振荡信号的压控振荡器; 第一分频器，通过分频振荡信号产生第一分频信号; 第二分频器，通过划分分频信号产生第二分频信号; 相位比较器，接收第二分频信号和参考信号作为输入，并输出对应于它们之间的相位差的两个信号; 环路滤波器，提取要输出到压控振荡器的两个信号之间的低频信号; 第三分频器，通过划分第一分频信号产生第三分频信号; 第一频率转换器，其通过将所述振荡信号乘以所述第三分频信号来产生第一频率转换信号; 以及第一乘法器，通过将第一频率转换信号乘以第一乘法数来产生相乘的信号。

128. 发明授权

US09094184B2 First and second phase detectors and phase offset adder PLL 有权
标题翻译：第一和第二相位检测器和相位偏移加法器PLL
公开(公告)号：US09094184B2
公开(公告)日：2015-07-28
申请号：US14525965
申请日：2014-10-28
申请人： Texas Instruments Incorporated
发明人： Robert Bogdan Staszewski , Dirk Leipold
IPC分类号： H03L7/087 , H04L7/033 , H03C3/09 , H03K19/00 , H03L7/085 , H03L7/091 , H03L7/093 , H03L7/099 , H03L7/16 , H03L7/08 , H04L7/00
CPC分类号： H03L7/0992 , H03C3/0966 , H03K19/0016 , H03L7/08 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/099 , H03L7/0991 , H03L7/16 , H03L2207/50 , H04L7/0029 , H04L7/0331
摘要： A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.
摘要翻译：锁相环电路（30,100,110）包括可控振荡器（42），用于响应于控制信号产生所需频率的输出信号;第一相位检测电路（32,102,112），用于产生输出指示响应于输出信号的相位差和参考信号的第一边缘和第二相位检测电路（34,104,114），用于产生响应于输出信号的指示相位差的输出和参考信号的第二边缘。到可控振荡器（42）的控制信号由第一和第二相位检测电路的输出驱动。

129. 发明授权

US09071254B2 Oscillator and self-calibration method thereof 有权
标题翻译：振荡器及其自校准方法
公开(公告)号：US09071254B2
公开(公告)日：2015-06-30
申请号：US14032925
申请日：2013-09-20
申请人： Grace Semiconductor Manufacturing Corporation
发明人： Ada Chen , Emir Yu
IPC分类号： H03L7/093 , H03L7/16
CPC分类号： H03L7/16 , H03L1/00 , H03L7/00 , H03L7/093
摘要： An oscillator and a self-calibration method thereof are provided. The oscillator includes: an oscillation unit for generating an oscillation signal; a converting unit for converting frequency of the oscillation signal into a voltage signal; a comparison unit for comparing the voltage signal with a first voltage corresponding to a higher frequency and a second voltage corresponding to a lower frequency, and outputting a comparison result signal; an adjusting unit for storing a calibration value, adjusting the calibration value based on the comparison result signal and outputting a calibration signal corresponding to the adjusted calibration value; and a calibration unit for calibrating the frequency of the oscillation signal based on the calibration signal. Self-calibration for the frequency of the oscillation signal may be achieved, which may ensure the stability of the frequency of the oscillation signal.
摘要翻译：提供振荡器及其自校准方法。振荡器包括：用于产生振荡信号的振荡单元; 转换单元，用于将振荡信号的频率转换成电压信号; 比较单元，用于将电压信号与对应于较低频率的较高频率和第二电压对应的第一电压进行比较，并输出比较结果信号; 调整单元，用于存储校准值，基于比较结果信号调整校准值，并输出与校准校准值对应的校准信号; 以及校准单元，用于基于校准信号来校准振荡信号的频率。可以实现对振荡信号频率的自校准，这可以确保振荡信号的频率的稳定性。

130. 发明申请

US20140347137A1 ADJUSTING TUNING SEGMENTS IN A DIGITALLY-CONTROLLED OSCILLATOR 有权
标题翻译：调整数字控制振荡器中的调谐部分
公开(公告)号：US20140347137A1
公开(公告)日：2014-11-27
申请号：US13901481
申请日：2013-05-23
申请人： Intel IP Corporation
发明人： Claudio REY , David HARNISHFEGER , Darin NGUYEN
IPC分类号： H03L7/16
CPC分类号： H03L7/099 , H03B5/124 , H03L7/103 , H03L7/18 , H03L2207/06
摘要： A circuit may include a digitally-controlled oscillator including a coarse frequency-tuning array with a multiple selectable coarse frequency-tuning segments. Each of the coarse frequency-tuning segments may have a coarse segment frequency step size. The digitally-controlled oscillator may also include a fine frequency-tuning array with multiple selectable fine frequency-tuning segments. The fine frequency-tuning array may have a fine array frequency step size that is at least twice the coarse segment frequency step size. The digitally-controlled oscillator may be configured to generate an output signal with a frequency based on the coarse frequency-tuning array and the fine frequency-tuning array.
摘要翻译：电路可以包括数字控制振荡器，其包括具有多个可选粗略频率调谐段的粗调频调谐阵列。每个粗调频段可以具有粗段频率步长。数字控制振荡器还可以包括具有多个可选精细频率调谐段的精细频率调谐阵列。精细的频率调谐阵列可以具有至少是粗略段频率步长的两倍的精细阵列频率步长。数字控制振荡器可以被配置为基于粗调频调谐阵列和精细频率调谐阵列产生具有频率的输出信号。

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