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121. 发明授权

US5761210A Signal processing apparatus and method 失效
标题翻译：信号处理装置及方法
公开(公告)号：US5761210A
公开(公告)日：1998-06-02
申请号：US486750
申请日：1995-06-07
申请人： Anthony Peter J. Claydon , Richard J. Gammack
发明人： Anthony Peter J. Claydon , Richard J. Gammack
IPC分类号： H04N7/26 , H03H17/02 , H03H21/00 , H03K5/24 , H03M3/02 , H03M13/00 , H03M13/15 , H03M13/27 , H04B3/06 , H04L1/00 , H04L7/00 , H04L7/033 , H04L7/04 , H04L25/03 , H04L25/06 , H04L27/00 , H04L27/02 , H04L27/06 , H04L27/227 , H04L27/38 , H04N5/00 , H04N5/21 , H04N5/44 , H04N5/455 , H04N5/52 , H04N7/24 , H04N7/30 , H04N21/2383 , H04N21/438 , G06F11/00
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04L7/0334
摘要： An integrated CMOS circuit is disclosed for deinterleaving transmitted data packets. The circuit operates with a RAM buffer that is no larger than a block of interleaved data. An optimized addressing scheme is provided that minimizes on-chip hardware. The circuit provides an orderly initialization of the buffer, and a suitable emptying process during a channel change or other interruption of data flow.
摘要翻译：公开了用于对所发送的数据分组进行解交织的集成CMOS电路。该电路使用不大于交错数据块的RAM缓冲器。提供了优化的寻址方案，最小化片上硬件。该电路提供缓冲器的有序初始化，以及在通道改变或数据流的其他中断过程中的适当的排空过程。

122. 发明授权

US5566183A System and method for deinterleaving digital data 失效
标题翻译：用于解交织数字数据的系统和方法
公开(公告)号：US5566183A
公开(公告)日：1996-10-15
申请号：US348424
申请日：1994-12-02
申请人： Andrzej F. Partyka
发明人： Andrzej F. Partyka
IPC分类号： H04L1/00 , H03M13/23 , H03M13/27 , H03M13/41 , H04Q7/38 , G06F11/00
CPC分类号： H03M13/2764
摘要： A deinterleaver for reordering elements of an interleaved digital data sequence (data packet) to obtain an original digital data sequence. The deinterleaver is used in a mobile station operating in a mobile communication system. The interleaved digital data sequence is previously generated by interleaving elements of an original digital data sequence such that digital data elements located in successive positions of the original digital data sequence are located in positions separated by one or more intervening digital data elements in the interleaved digital data sequence. The deinterleaver comprises a data buffer for storing the interleaved digital data sequence; a decoder to generate a first address of a desired data element of the interleaved digital data sequence, the first address corresponding to a position of the desired data element in the original digital data sequence; and an address twister to translate the first address to a second address corresponding to a position of the desired data element in the interleaved digital data sequence; wherein the data buffer is accessed according to the second address to retrieve the desired data element of the original digital data sequence.
摘要翻译：一种去交织器，用于对交织的数字数据序列（数据分组）的元素重新排序以获得原始数字数据序列。解交织器用于在移动通信系统中操作的移动台中。先前通过交织原始数字数据序列的元素来产生交错的数字数据序列，使得位于原始数字数据序列的连续位置的数字数据元素位于由交织数字数据中的一个或多个中间数字数据元素隔开的位置序列。解交织器包括用于存储交织的数字数据序列的数据缓冲器; 解码器，用于生成所述交错数字数据序列的所需数据元素的第一地址，所述第一地址对应于所述原始数字数据序列中期望数据元素的位置; 以及地址扭转器，用于将所述第一地址转换为与所述交织的数字数据序列中的期望数据元素的位置相对应的第二地址; 其中根据第二地址访问数据缓冲器以检索原始数字数据序列的期望数据元素。

123. 发明授权

US5257271A Sample data transmission apparatus 失效
标题翻译：样品数据传输装置
公开(公告)号：US5257271A
公开(公告)日：1993-10-26
申请号：US939406
申请日：1992-09-01
申请人： Roger Lagadec , Keisuke Sekiguchi , Hiroyuki Yamauchi , Masaru Tezuka , Satoru Tobita , Yoichiro Sako , Hiroyuki Hara, deceased
发明人： Roger Lagadec , Keisuke Sekiguchi , Hiroyuki Yamauchi , Masaru Tezuka , Satoru Tobita , Yoichiro Sako , Hiroyuki Hara, deceased
IPC分类号： G11B20/18 , H03M13/27 , H04L1/14
CPC分类号： H03M13/2764 , G11B20/1809
摘要： In a sampled data transmitting apparatus in which the sampled data to be transmitted are divided into odd-numbered samples and even-numbered samples and arranged in different rows of a two-dimensional data array, and in which error correction codes are annexed to each row and to each column of the two-dimensional data array, the row arraying sequence in one of the odd-numbered or even-numbered rows is caused to differ from the row arraying sequence in the other of the odd-numbered or even-numbered rows so that odd-numbered data and even-numbered data continuous with the odd-numbered data are not arranged in one row. In this manner, even when error correction becomes impossible by the error correcting code for one row, interpolation remains feasible because there exist no odd-numbered data or even-numbered data contiguous to each other in the row.
摘要翻译：在采样数据发送装置中，将要发送的采样数据划分为奇数样本和偶数样本，并排列在二维数据阵列的不同行中，其中纠错码附于每行并且对于二维数据阵列的每列，使奇数或偶数行之一中的行排列顺序与奇数行或偶数行中的另一行中的行排列顺序不同使得与奇数数据连续的奇数数据和偶数数据不排列在一行中。以这种方式，即使通过一行的纠错码不可能进行纠错，因为在该行中不存在彼此邻接的奇数数据或偶数数据，因此内插仍然是可行的。

124. 发明授权

US10879936B2 Methods, systems, and computer readable media for de-interleaving data in a communication system 有权
公开(公告)号：US10879936B2
公开(公告)日：2020-12-29
申请号：US16110887
申请日：2018-08-23
申请人： Keysight Technologies, Inc.
发明人： Damon Lee Campbell
IPC分类号： H03M13/27 , H04W72/04 , H04L1/00
CPC分类号： H03M13/2764 , H04L1/0071 , H04W72/042
摘要： A system includes a data bus, Q registers each having a register width B, and a receiver circuit. The receiver circuit is configured for receiving, at each clock cycle of a number of clock cycles of the communication system, a bit lane of data on a data bus, each bit lane including Q valid bits of an interleaved packet of length E. The receiver circuit is configured for placing, at each clock cycle, each of the Q valid bits into a respective bin of Q bins each having a bin width equal to the register width B. The receiver circuit is configured for determining that the bins are full, and in response to determining that the bins are full, transferring the contents of the bins into the registers.

125. 发明申请

US20180373588A1 BAD BIT REGISTER FOR MEMORY 审中-公开
公开(公告)号：US20180373588A1
公开(公告)日：2018-12-27
申请号：US15630538
申请日：2017-06-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John K. DeBrosse , Daniel C. Worledge
IPC分类号： G06F11/10 , H03M13/27
CPC分类号： G06F11/1016 , G11C11/16 , G11C29/06 , G11C29/34 , G11C29/42 , G11C29/4401 , G11C29/52 , G11C29/789 , G11C2029/0403 , G11C2029/4402 , H01L27/222 , H01L43/08 , H03M13/2764 , H04L1/0071
摘要： A memory device, a memory system, and corresponding methods are provided. The memory device includes a non-volatile random access memory. The non-volatile memory includes a suspect bit register configured to store addresses of bits that are determined to have had errors. The non-volatile memory further includes a bad bit register configured to store addresses of bits that both (i) appeared in the suspect bit register due to a first error and (ii) are determined to have had a second error. Hence, the memory device overcomes the aforementioned intrinsic write-error-rate by identifying the bad bits so they can be fused out, thus avoiding errors during use of the non-volatile random access memory.

126. 发明授权

US09971684B2 Self-configurable device for interleaving/deinterleaving data frames 有权
公开(公告)号：US09971684B2
公开(公告)日：2018-05-15
申请号：US14380554
申请日：2013-02-22
申请人： UNIVERSITE DE BRETAGNE SUD , CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE—CNRS
发明人： Philippe Coussy , Cyrille Chavet
IPC分类号： G06F12/10 , G06F12/06 , H03M13/27 , H03M13/00 , G06F13/28 , H03M13/11
CPC分类号： G06F12/0607 , G06F13/28 , G06F2212/251 , H03M13/1102 , H03M13/2764 , H03M13/2775 , H03M13/2789 , H03M13/6513 , H03M13/6519 , H03M13/6569
摘要： A device for interleaving/deinterleaving digital data delivered by processing elements (P0 . . . Pn-1) suitable for being used both with turbo-codes and with LDPC codes. The device includes memory banks (B0 . . . Bm-1) for storing data coming from or going to the processing elements, an interconnection network (INT) for directing the data between the processing elements and the memory banks, and a control unit (CTRL) for controlling the interconnection network and the memory banks. The control unit (CTRL) includes a calculation circuit (CAL) capable of the online generation of command words for the interconnection network and addressing and control sequences of the memory banks, ensuring conflict-free memory access on the basis of the interleaving rule to be applied, the size of the digital data frames, the number of processing units and memory banks, and the interconnection network.

127. 发明授权

US08572332B2 De-interleaving mechanism involving a multi-banked LLR buffer 有权
标题翻译：涉及多段LLR缓冲器的解交织机制
公开(公告)号：US08572332B2
公开(公告)日：2013-10-29
申请号：US12404613
申请日：2009-03-16
申请人： Ali RostamPisheh , Raghu N. Challa , Iwen Yao , Davie J. Santos , Mrinal M. Nath
发明人： Ali RostamPisheh , Raghu N. Challa , Iwen Yao , Davie J. Santos , Mrinal M. Nath
IPC分类号： G06F12/00
CPC分类号： H03M13/2785 , H03M13/2764 , H03M13/2771 , H03M13/2775 , H03M13/6566
摘要： A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of a transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks such that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner.
摘要翻译：解交织器产生多个解交织重排物理（DRP）地址，以将对应的多个LLR值同时写入多存储存储器，使得不多于一个LLR值被写入多存储体的每个存储体一次记忆这种并行写入的序列导致存储在存储器中的子包的传输的LLR值。在生成DRP地址期间执行的地址转换导致LLR值被存储在存储体中，使得解码器可以以解交织的顺序读出存储器中的LLR值。存储体的每个存储器位置是用于存储多个相关LLR值的字位置，其中一个LLR值与其奇偶校验值一起存储。用于同时写入多个LLR值的能力用于以快速有效的方式清除位置。

128. 发明授权

US08397123B2 Recursive realization of polynomial permutation interleaving 有权
标题翻译：递归实现多项式置换交织
公开(公告)号：US08397123B2
公开(公告)日：2013-03-12
申请号：US12571319
申请日：2009-09-30
申请人： Hanfang Pan , Michael A. Howard , Yongbin Wei , Michael A. Kongelf
发明人： Hanfang Pan , Michael A. Howard , Yongbin Wei , Michael A. Kongelf
IPC分类号： H03M13/00
CPC分类号： H03M13/2775 , H03M13/2739 , H03M13/2764 , H03M13/6502 , H03M13/6505 , H03M13/6525
摘要： Systems and methodologies are described that facilitate automatically generating interleaved addresses during turbo decoding. An efficient recursive technique can be employed in which layers of nested loops enable the computation of a polynomial and a modular function given interleaved parameters “a” and “b” from a look up table. With the recursive technique, interleaved addresses can be generated, one interleaved address per clock cycle which can maintain turbo decoding performance.
摘要翻译：描述了在turbo解码期间便于自动生成交错地址的系统和方法。可以采用一种有效的递归技术，其中嵌套循环层能够从查询表中计算多项式和给定交织参数a和b的模块化函数。使用递归技术，可以产生交织地址，每个时钟周期的一个交织地址可以保持turbo解码性能。

129. 发明授权

US08175142B2 Odd-even interleaving while changing the operating mode in a digital video broadcasting (DVB) standard 有权
标题翻译：在数字视频广播（DVB）标准中改变操作模式时，奇偶交织
公开(公告)号：US08175142B2
公开(公告)日：2012-05-08
申请号：US12435657
申请日：2009-05-05
申请人： Samuel Asanbeng Atungsiri , Matthew Paul Athol Taylor
发明人： Samuel Asanbeng Atungsiri , Matthew Paul Athol Taylor
IPC分类号： H03H7/30
CPC分类号： H04L27/2602 , H03M13/2742 , H03M13/2764 , H04L1/0071 , H04L27/2647 , H04N21/6112
摘要： A data processing apparatus to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols include first sets of data symbols and second sets of input data symbols. The data processing apparatus includes a controller, an address generator, and an interleaver memory. The controller is configured, when operating in accordance with an even interleaving process, to read out a first set of the input data symbols from the interleaver memory on to the sub-carrier signals of an even OFDM symbol using read addresses generated by the address generator, and to write in a second set of the input data symbols into the interleaver memory using the addresses generated by the address generator.
摘要翻译：一种数据处理装置，用于将要传送的输入数据符号映射到正交频分复用OFDM符号的预定数量的副载波信号。根据多种操作模式中的一种确定预定数量的副载波信号，并且输入数据符号包括第一组数据符号和第二组输入数据符号。数据处理装置包括控制器，地址发生器和交织器存储器。当根据偶数交织处理操作时，控制器被配置为使用由地址生成器生成的读取地址从交织器存储器读出第一组输入数据符号到偶数OFDM符号的副载波信号并且使用由地址生成器生成的地址将第二组输入数据符号写入交织器存储器。

130. 发明授权

US08127105B2 Parallel pruned bit-reversal interleaver 有权
标题翻译：并行修剪的位反转交织器
公开(公告)号：US08127105B2
公开(公告)日：2012-02-28
申请号：US12264880
申请日：2008-11-04
申请人： Mohamad Mansour
发明人： Mohamad Mansour
IPC分类号： G06F12/00
CPC分类号： H03M13/2764 , H03M13/276
摘要： A parallel lookahead pruned bit-reversal interleaver algorithm and architecture have been proposed. The algorithm interleaves a packet of length N in at most log(N)−1 steps compared to N steps using existing sequential algorithms, and has a simple architecture amenable for high-speed applications. The proposed algorithm is valuable for emerging wireless standards especially those that employ PBRI channel (de-)interleavers on long packets in reducing interleaving latency on the transmitter side and deinterleaving latency on the receiver side.
摘要翻译：已经提出了并行的前瞻性修剪的位反转交织器算法和架构。该算法使用现有的顺序算法，与N个步骤相比，以最多log（N）-1个步长交织长度为N的数据包，并且具有适用于高速应用的简单架构。所提出的算法对于新兴的无线标准是有价值的，特别是那些在长分组上采用PBRI信道（去）交织器来减少发送机侧的交织等待时间并在接收机侧解交织等待时间的算法。

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