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121. 发明授权

US07732872B2 Integration scheme for multiple metal gate work function structures 失效
标题翻译：多金属门功能结构的集成方案
公开(公告)号：US07732872B2
公开(公告)日：2010-06-08
申请号：US11924053
申请日：2007-10-25
申请人： Kangguo Cheng , Michael P. Chudzik , Ramachandra Divakaruni , Geng Wang , Robert C. Wong , Haining S. Yang
发明人： Kangguo Cheng , Michael P. Chudzik , Ramachandra Divakaruni , Geng Wang , Robert C. Wong , Haining S. Yang
IPC分类号： H01L27/088
CPC分类号： H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1116 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.
摘要翻译：在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整氧化层。还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。

122. 发明申请

US20090268510A1 DYNAMIC RANDOM ACCESS MEMORY CIRCUIT, DESIGN STRUCTURE AND METHOD 有权
标题翻译：动态随机访问存储器电路，设计结构和方法
公开(公告)号：US20090268510A1
公开(公告)日：2009-10-29
申请号：US12108548
申请日：2008-04-24
申请人： John E. Barth, JR. , Kangguo Cheng , Hoki Kim , Geng Wang
发明人： John E. Barth, JR. , Kangguo Cheng , Hoki Kim , Geng Wang
IPC分类号： G11C11/24 , H01L21/8242
CPC分类号： H01L27/10829 , G11C7/02 , G11C11/4099 , H01L27/10861 , H01L27/10885 , H01L27/10891 , H01L27/10897
摘要： Disclosed is a DRAM circuit that incorporates an improved reference cell, has half the capacitance of the memory cell, does not require a particular reference voltage, and can be formed using the same fabrication processes as the memory cell. This DRAM circuit comprises a memory cell with a single trench capacitor and a reference cell having two trench capacitors. The two reference cell trench capacitors are connected in series through a merged buried capacitor plate such that they provide half the capacitance of the memory cell trench capacitor. Additionally, the reference cell trench capacitors have essentially the same structure as the memory cell trench capacitor so that they can be formed in conjunction with the memory cell trench capacitor. Also disclosed are a design structure for the above-described memory circuit and a method for forming the above-described memory circuit.
摘要翻译：公开了一种DRAM电路，其包含改进的参考单元，具有存储单元的一半电容，不需要特定参考电压，并且可以使用与存储单元相同的制造工艺来形成。该DRAM电路包括具有单沟槽电容器的存储单元和具有两个沟槽电容器的参考单元。两个参考单元沟槽电容器通过合并的埋入式电容器板串联连接，使得它们提供存储单元沟槽电容器的一半的电容。此外，参考单元沟槽电容器具有与存储单元沟槽电容器基本相同的结构，使得它们可以与存储单元沟槽电容器结合形成。还公开了用于上述存储电路的设计结构和用于形成上述存储电路的方法。

123. 发明授权

US07439149B1 Structure and method for forming SOI trench memory with single-sided strap 失效
标题翻译：用单面带形成SOI沟槽存储器的结构和方法
公开(公告)号：US07439149B1
公开(公告)日：2008-10-21
申请号：US11861704
申请日：2007-09-26
申请人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/20
CPC分类号： H01L27/10867 , H01L27/0207
摘要： A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask so as cover one side of the trench and removing one or more materials from an uncovered opposite side of the trench; and forming a conductive buried strap material within the trench; wherein the strap mask is patterned in a manner such that a single-sided buried strap is defined within the trench, the single-sided buried strap configured in a manner such that the deep trench capacitor is electrically accessible at only one side of the trench.
摘要翻译：形成沟槽存储单元的方法包括在衬底材料内形成沟槽电容器，所述沟槽电容器包括形成在沟槽内的节点电介质层和形成在所述沟槽内与所述节点电介质层接触的导电电容器电极材料; 形成带状掩模，以覆盖沟槽的一侧，并从沟槽的未覆盖的相对侧移除一种或多种材料; 以及在所述沟槽内形成导电掩埋带材料; 其中所述带掩模被图案化，使得在所述沟槽内限定单面掩埋带，所述单侧埋入带以使得所述深沟槽电容器仅在所述沟槽的一侧电可访问的方式构造。

124. 发明授权

US07388261B2 Structure and method for accurate deep trench resistance measurement 有权
标题翻译：精确深沟槽电阻测量的结构和方法
公开(公告)号：US07388261B2
公开(公告)日：2008-06-17
申请号：US11853040
申请日：2007-09-11
申请人： Kangguo Cheng , Geng Wang
发明人： Kangguo Cheng , Geng Wang
IPC分类号： H01L29/76
CPC分类号： H01L22/34 , H01L27/1087 , H01L29/8605 , H01L2924/0002 , H01L2924/00
摘要： A test structure for implementing resistance measurement of a deep trench formed in a semiconductor device includes a pair of deep trenches formed within a semiconductor substrate. The pair of deep trenches has a dielectric material formed on side and bottom surfaces thereof, and includes a conductive fill material therein. Bottom portions of the pair of deep trenches are merged with one another so as to provide an electrically conductive path therethrough.
摘要翻译：用于实现在半导体器件中形成的深沟槽的电阻测量的测试结构包括形成在半导体衬底内的一对深沟槽。一对深沟槽具有在其侧表面和底表面上形成的电介质材料，并且在其中包括导电填充材料。一对深沟槽的底部部分彼此合并，以提供穿过其中的导电路径。

125. 发明申请

US20050224852A1 Offset vertical device 失效
标题翻译：偏移垂直装置
公开(公告)号：US20050224852A1
公开(公告)日：2005-10-13
申请号：US10813352
申请日：2004-03-30
申请人： Kangguo Cheng , Ramachandra Divakaruni , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Geng Wang
IPC分类号： H01L21/334 , H01L21/8242 , H01L27/108 , H01L29/94
CPC分类号： H01L27/10867 , H01L27/1087 , H01L29/66181 , H01L29/945
摘要： The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical contact to each other through a first buried strap, where the first buried strap positioned on a first collar region; and at least one second-type memory cell, where each of the at least are second-type memory device comprises a second transistor and a second underlying capacitor that are in electrical contact through an offset buried strap, where the offset buried strap is positioned on a second collar region, wherein the second collar region has a length equal to the first collar region.
摘要翻译：本发明包括一种用于形成存储器阵列的方法和由其制成的存储器阵列。具体而言，存储器阵列包括至少一个第一型存储器件，至少一个第一型存储器件中的每一个包括通过第一掩埋带彼此电接触的第一晶体管和第一底层电容器，其中位于第一环区的第一掩埋带; 以及至少一个第二类型存储单元，其中至少第二类型存储器件中的每一个包括第二晶体管和第二底层电容器，所述第二晶体管和第二底层电容器通过偏移掩埋带电接触，其中所述偏移掩埋带位于第二衣领区域，其中第二衣领区域具有等于第一衣领区域的长度。

126. 发明申请

US20110201161A1 METHOD OF FORMING A BURIED PLATE BY ION IMPLANTATION 失效
标题翻译：通过离子植入形成板坯的方法
公开(公告)号：US20110201161A1
公开(公告)日：2011-08-18
申请号：US12705768
申请日：2010-02-15
申请人： Joseph Ervin , Geng Wang
发明人： Joseph Ervin , Geng Wang
IPC分类号： H01L21/02 , H01L21/336
CPC分类号： H01L21/84 , H01L21/2652 , H01L27/1087 , H01L27/1203 , H01L29/66181 , H01L29/78 , H01L29/945
摘要： A mask layer formed over a semiconductor substrate is lithographically patterned to form an opening therein. Ions are implanted at an angle that is normal to the surface of the semiconductor substrate through the opening and into an upper portion of the semiconductor substrate. Straggle of the implanted ions form a doped region that laterally extends beyond a horizontal cross-sectional area of the opening. A deep trench is formed by performing an anisotropic etch of a semiconductor material underneath the opening to a depth above a deep end of an implanted region. Ion implantation steps and anisotropic etch steps are alternately employed to extend the depth of the doped region and the depth of the deep trench, thereby forming a doped region around a deep trench that has narrow lateral dimensions. The doped region can be employed as a buried plate for a deep trench capacitor.
摘要翻译：在半导体衬底上形成的掩模层被光刻图案化以在其中形成开口。离子以与半导体衬底的表面垂直的角度通过开口注入并进入半导体衬底的上部。注入离子的束缚形成横向延伸超过开口的水平横截面积的掺杂区域。通过对开口下方的半导体材料进行向注入区域的深端上方的深度的各向异性蚀刻来形成深沟槽。交替使用离子注入步骤和各向异性蚀刻步骤来扩展掺杂区域的深度和深沟槽的深度，从而在具有窄横向尺寸的深沟槽周围形成掺杂区域。掺杂区域可以用作深沟槽电容器的掩埋板。

127. 发明授权

US08536649B2 Method to reduce threshold voltage variability with through gate well implant 失效
标题翻译：通过栅极井注入降低阈值电压变化的方法
公开(公告)号：US08536649B2
公开(公告)日：2013-09-17
申请号：US13608860
申请日：2012-09-10
申请人： Geng Wang , Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries
发明人： Geng Wang , Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries
IPC分类号： H01L29/66
CPC分类号： H01L29/66772 , H01L21/2652 , H01L29/78696
摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.
摘要翻译：本公开提供了一种半导体器件，其可以包括包括覆盖绝缘层的半导体层的衬底。存在于半导体层的沟道部分上的栅极结构。第一掺杂区存在于半导体层的沟道部分中，其中第一掺杂区的峰值浓度存在于栅极导体的下部和半导体层的上部之间。第二掺杂剂区域存在于半导体层的沟道部分中，其中第二掺杂剂区域的峰值浓度存在于半导体层的下部。

128. 发明申请

US20120326233A1 METHOD TO REDUCE THRESHOLD VOLTAGE VARIABILITY WITH THROUGH GATE WELL IMPLANT 失效
标题翻译：通过门式井口植入降低阈值电压变化的方法
公开(公告)号：US20120326233A1
公开(公告)日：2012-12-27
申请号：US13608860
申请日：2012-09-10
申请人： Geng Wang , Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries
发明人： Geng Wang , Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries
IPC分类号： H01L29/78
CPC分类号： H01L29/66772 , H01L21/2652 , H01L29/78696
摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.
摘要翻译：本公开提供了一种半导体器件，其可以包括包括覆盖绝缘层的半导体层的衬底。存在于半导体层的沟道部分上的栅极结构。第一掺杂区存在于半导体层的沟道部分中，其中第一掺杂区的峰值浓度存在于栅极导体的下部和半导体层的上部之间。第二掺杂剂区域存在于半导体层的沟道部分中，其中第二掺杂剂区域的峰值浓度存在于半导体层的下部内。

129. 发明授权

US08298884B2 Method to reduce threshold voltage variability with through gate well implant 有权
标题翻译：通过栅极井注入降低阈值电压变化的方法
公开(公告)号：US08298884B2
公开(公告)日：2012-10-30
申请号：US12862048
申请日：2010-08-24
申请人： Geng Wang , Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries
发明人： Geng Wang , Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries
IPC分类号： H01L21/338
CPC分类号： H01L29/66772 , H01L21/2652 , H01L29/78696
摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.
摘要翻译：本公开提供了一种半导体器件，其可以包括包括覆盖绝缘层的半导体层的衬底。存在于半导体层的沟道部分上的栅极结构。第一掺杂区存在于半导体层的沟道部分中，其中第一掺杂区的峰值浓度存在于栅极导体的下部和半导体层的上部之间。第二掺杂剂区域存在于半导体层的沟道部分中，其中第二掺杂剂区域的峰值浓度存在于半导体层的下部。

130. 发明授权

US08133781B2 Method of forming a buried plate by ion implantation 失效
标题翻译：通过离子注入形成掩埋板的方法
公开(公告)号：US08133781B2
公开(公告)日：2012-03-13
申请号：US12705768
申请日：2010-02-15
申请人： Joseph Ervin , Geng Wang
发明人： Joseph Ervin , Geng Wang
IPC分类号： H01L21/8242 , H01L21/20 , H01L21/425
CPC分类号： H01L21/84 , H01L21/2652 , H01L27/1087 , H01L27/1203 , H01L29/66181 , H01L29/78 , H01L29/945
摘要： A mask layer formed over a semiconductor substrate is lithographically patterned to form an opening therein. Ions are implanted at an angle that is normal to the surface of the semiconductor substrate through the opening and into an upper portion of the semiconductor substrate. Straggle of the implanted ions form a doped region that laterally extends beyond a horizontal cross-sectional area of the opening. A deep trench is formed by performing an anisotropic etch of a semiconductor material underneath the opening to a depth above a deep end of an implanted region. Ion implantation steps and anisotropic etch steps are alternately employed to extend the depth of the doped region and the depth of the deep trench, thereby forming a doped region around a deep trench that has narrow lateral dimensions. The doped region can be employed as a buried plate for a deep trench capacitor.
摘要翻译：在半导体衬底上形成的掩模层被光刻图案化以在其中形成开口。离子以与半导体衬底的表面垂直的角度通过开口注入并进入半导体衬底的上部。注入离子的束缚形成横向延伸超过开口的水平横截面积的掺杂区域。通过对开口下方的半导体材料进行向注入区域的深端上方的深度的各向异性蚀刻来形成深沟槽。交替使用离子注入步骤和各向异性蚀刻步骤来扩展掺杂区域的深度和深沟槽的深度，从而在具有窄横向尺寸的深沟槽周围形成掺杂区域。掺杂区域可以用作深沟槽电容器的掩埋板。

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