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121. 发明授权

US06473819B1 Scalable interruptible queue locks for shared-memory multiprocessor 有权
标题翻译：可扩展的可中断队列锁为共享内存多处理器
公开(公告)号：US06473819B1
公开(公告)日：2002-10-29
申请号：US09465297
申请日：1999-12-17
申请人： Benedict Joseph Jackson , Paul Edward McKenney , Ramakrishnan Rajamony , Ronald Lynn Rockhold
发明人： Benedict Joseph Jackson , Paul Edward McKenney , Ramakrishnan Rajamony , Ronald Lynn Rockhold
IPC分类号： G06F1200
CPC分类号： G06F9/52
摘要： A method for a computation agent to acquire a queue lock in a multiprocessor system that prevents deadlock between the computation agent and external interrupts. The method provides for the computation agent to join a queue to acquire a lock. Next, upon receiving ownership of the lock, the computation agent raises its priority level to a higher second priority level. In response to a receipt of an external interrupt having a higher priority level occurring before the computation agent has raised its priority level to the second higher priority level, the computation agent relinquishes ownership of the lock. Subsequent to raising its priority level to the second higher priority level, the computation agent determines if it still has ownership of the lock. If the computation agent determines that it has not acquired possession of the lock after raising its priority level, the computation agent rejoins the queue to reacquire the lock. In one embodiment of the present invention, the computation agent's priority level is restored to its original, i.e., first priority level, when it rejoins the queue to reacquire the lock.
摘要翻译：一种用于计算代理获取多处理器系统中的队列锁的方法，其防止计算代理和外部中断之间的死锁。该方法提供计算代理加入队列以获取锁。接下来，在获得锁的所有权时，计算代理将其优先级提高到更高的第二优先级。响应于在计算代理已经将其优先级提高到第二较高优先级之前发生具有较高优先级的外部中断的接收，计算代理放弃对锁的所有权。在将其优先级提高到第二高优先级之后，计算代理确定它是否仍具有锁的所有权。如果计算代理确定在提升其优先级后尚未获得该锁的拥有权，则计算代理重新加入队列以重新获取该锁。在本发明的一个实施例中，当它重新加入队列以重新获取锁时，计算代理的优先级被恢复到其原始的，即第一优先级。

122. 发明授权

US06421775B1 Interconnected processing nodes configurable as at least one non-uniform memory access (NUMA) data processing system 有权
标题翻译：互连处理节点可配置为至少一个非均匀存储器访问（NUMA）数据处理系统
公开(公告)号：US06421775B1
公开(公告)日：2002-07-16
申请号：US09335301
申请日：1999-06-17
申请人： Bishop Chapman Brock , David Brian Glasco , James Lyle Peterson , Ramakrishnan Rajamony , Ronald Lynn Rockhold
发明人： Bishop Chapman Brock , David Brian Glasco , James Lyle Peterson , Ramakrishnan Rajamony , Ronald Lynn Rockhold
IPC分类号： G06F15177
CPC分类号： G06F15/177
摘要： A data processing system includes a plurality of processing nodes that each contain at least one processor and data storage. The plurality of processing nodes are coupled together by a system interconnect. The data processing system further includes a configuration utility residing in data storage within at least one of the plurality of processing nodes. The configuration utility selectively configures the plurality of processing nodes into either a single non-uniform memory access (NUMA) system or into multiple independent data processing systems through communication via the system interconnect.
摘要翻译：数据处理系统包括多个处理节点，每个处理节点包含至少一个处理器和数据存储器。多个处理节点通过系统互连耦合在一起。数据处理系统还包括驻留在多个处理节点中的至少一个处理节点内的数据存储器中的配置实用程序。配置实用程序通过经由系统互连的通信将多个处理节点选择性地配置为单个非均匀存储器访问（NUMA）系统或多个独立的数据处理系统。

123. 发明授权

US08417913B2 Superpage coalescing which supports read/write access to a new virtual superpage mapping during copying of physical pages 失效
标题翻译： Superpage coalescing在复制物理页面期间支持对新的虚拟超级页面映射的读/写访问
公开(公告)号：US08417913B2
公开(公告)日：2013-04-09
申请号：US10713733
申请日：2003-11-13
申请人： Elmootazbellah Nabil Elnozahy , James Lyle Peterson , Ramakrishnan Rajamony , Hazim Shafi
发明人： Elmootazbellah Nabil Elnozahy , James Lyle Peterson , Ramakrishnan Rajamony , Hazim Shafi
IPC分类号： G06F12/00
CPC分类号： G06F12/1045
摘要： A method of assigning virtual memory to physical memory in a data processing system allocates a set of contiguous physical memory pages for a new page mapping, instructs the memory controller to move the virtual memory pages according to the new page mapping, and then allows access to the virtual memory pages using the new page mapping while the memory controller is still copying the virtual memory pages to the set of physical memory pages. The memory controller can use a mapping table which temporarily stores entries of the old and new page addresses, and releases the entries as copying for each entry is completed. The translation lookaside buffer (TLB) entries in the processor cores are updated for the new page addresses prior to completion of copying of the memory pages by the memory controller. The invention can be extended to non-uniform memory array (NUMA) systems. For systems with cache memory, any cache entry which is affected by the page move can be updated by modifying its address tag according to the new page mapping. This tag modification may be limited to cache entries in a dirty coherency state. The cache can further relocate a cache entry based on a changed congruence class for any modified address tag.
摘要翻译：将虚拟存储器分配给数据处理系统中的物理存储器的方法为新的页面映射分配一组连续的物理存储器页面，指示存储器控制器根据新的页面映射移动虚拟存储器页面，然后允许访问虚拟内存页面使用新页面映射，而内存控制器仍将虚拟内存页面复制到物理内存页面集合。存储器控制器可以使用临时存储旧页面地址和新页面地址的条目的映射表，并且对于每个条目的拷贝完成，释放条目。在由存储器控制器完成对存储器页面的复制之前，处理器核心中的翻译后备缓冲器（TLB）条目针对新的页地址进行更新。本发明可以扩展到非均匀存储器阵列（NUMA）系统。对于具有缓存内存的系统，可以通过根据新页面映射修改其地址标签来更新受页面移动影响的任何缓存条目。该标签修改可能被限制在脏相关性状态下的高速缓存条目。高速缓存可以根据修改后的地址标签的改变的一致性类别进一步重新定位缓存条目。

124. 发明申请

US20130041882A1 Technology for web site crawling, including action sequences for selecting non-hypertext-link parameters 审中-公开
标题翻译：用于网站抓取的技术，包括用于选择非超文本链接参数的动作序列
公开(公告)号：US20130041882A1
公开(公告)日：2013-02-14
申请号：US13600201
申请日：2012-08-30
申请人： Elizabeth Adleberg Brodsky , Elmootazbellah Nabil Elnozahy , Ramakrishnan Rajamony
发明人： Elizabeth Adleberg Brodsky , Elmootazbellah Nabil Elnozahy , Ramakrishnan Rajamony
IPC分类号： G06F17/30
CPC分类号： G06F16/951 , G06F16/9574
摘要： A web site page has a reference for providing an address for a next page. The web site is crawled by the crawler program, which parses the reference from one of the web pages and sends the reference to an applet running in the browser. The address for the next page is determined by the browser responsive to the reference and is sent to the crawler.
摘要翻译：网站页面提供了下一页地址的参考。该搜索器程序抓取该网站，该程序从其中一个网页解析引用，并将引用发送到在浏览器中运行的小程序。下一页的地址由浏览器根据引用确定，并发送到爬网程序。

125. 发明授权

US08255591B2 Method and system for managing cache injection in a multiprocessor system 有权
标题翻译：在多处理器系统中管理缓存注入的方法和系统
公开(公告)号：US08255591B2
公开(公告)日：2012-08-28
申请号：US10948407
申请日：2004-09-23
申请人： Patrick Joseph Bohrer , Ahmed Gheith , Peter Heiner Hochschild , Ramakrishnan Rajamony , Hazim Shafi , Balaram Sinharoy
发明人： Patrick Joseph Bohrer , Ahmed Gheith , Peter Heiner Hochschild , Ramakrishnan Rajamony , Hazim Shafi , Balaram Sinharoy
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and apparatus for managing cache injection in a multiprocessor system reduces processing time associated with direct memory access transfers in a symmetrical multiprocessor (SMP) or a non-uniform memory access (NUMA) multiprocessor environment. The method and apparatus either detect the target processor for DMA completion or direct processing of DMA completion to a particular processor, thereby enabling cache injection to a cache that is coupled with processor that executes the DMA completion routine processing the data injected into the cache. The target processor may be identified by determining the processor handling the interrupt that occurs on completion of the DMA transfer. Alternatively or in conjunction with target processor identification, an interrupt handler may queue a deferred procedure call to the target processor to process the transferred data. In NUMA multiprocessor systems, the completing processor/target memory is chosen for accessibility of the target memory to the processor and associated cache.
摘要翻译：用于管理多处理器系统中的高速缓存注入的方法和装置减少与对称多处理器（SMP）或非均匀存储器访问（NUMA）多处理器环境中的直接存储器访问传输相关联的处理时间。该方法和装置可以检测目标处理器用于DMA完成或直接处理DMA完成到特定处理器，从而使高速缓存注入与执行DMA完成例程的处理器处理注入高速缓存的数据的处理器相连的高速缓存。可以通过确定处理器处理在DMA传输完成时发生的中断来识别目标处理器。或者或与目标处理器识别结合，中断处理程序可以将延迟过程调用排队到目标处理器以处理传送的数据。在NUMA多处理器系统中，选择完成的处理器/目标存储器，以便可访问目标存储器到处理器和相关联的高速缓存。

126. 发明授权

US08194638B2 Dual network types solution for computer interconnects 有权
标题翻译：用于计算机互连的双网络类型解决方案
公开(公告)号：US08194638B2
公开(公告)日：2012-06-05
申请号：US11493951
申请日：2006-07-27
申请人： Alan Benner , Ramakrishnan Rajamony , Eugen Schenfeld , Craig Brian Stunkel , Peter A. Walker
发明人： Alan Benner , Ramakrishnan Rajamony , Eugen Schenfeld , Craig Brian Stunkel , Peter A. Walker
IPC分类号： H04L12/28
CPC分类号： H04L12/4641 , H04L12/28 , H04L12/66
摘要： Briefly, according to an embodiment of the invention, a computing system comprises: a plurality of tightly coupled processing nodes; a plurality of circuit switched networks using a circuit switching mode, interconnecting the processing nodes, and for handling data transfers that meet one or more criteria; and a plurality of electronic packet switched networks, also interconnecting the processing nodes, for handling data transfers that do meet the at least one criteria. The circuit switched networks and the electronic packet switched networks operate simultaneously. The system additionally comprises a plurality of clusters which comprise the processing nodes, and a plurality of intra-cluster communication links. The electronic packet switched networks are for handling collectives and short-lived data transfers among the processing nodes and comprises one-tenth of the bandwidth of the circuit switched networks.
摘要翻译：简而言之，根据本发明的实施例，一种计算系统包括：多个紧密耦合的处理节点; 使用电路交换模式的多个电路交换网络，互连处理节点，以及用于处理满足一个或多个标准的数据传输; 以及多个电子分组交换网络，其也互连处理节点，用于处理满足至少一个标准的数据传输。电路交换网络和电子分组交换网络同时工作。该系统还包括包括处理节点的多个群集和多个群内通信链路。电子分组交换网络用于处理处理节点之间的集合和短期数据传输，并且包括电路交换网络带宽的十分之一。

127. 发明授权

US07747736B2 Rule and policy promotion within a policy hierarchy 失效
标题翻译：政策层级中的规则和政策推广
公开(公告)号：US07747736B2
公开(公告)日：2010-06-29
申请号：US11422239
申请日：2006-06-05
申请人： Rhonda L. Childress , Itzhack Goldberg , Lorraine M. Herger , Ziv Rafalovich , Ramakrishnan Rajamony , Eric Van Hensbergen , Martin J. Tross
发明人： Rhonda L. Childress , Itzhack Goldberg , Lorraine M. Herger , Ziv Rafalovich , Ramakrishnan Rajamony , Eric Van Hensbergen , Martin J. Tross
IPC分类号： G06F3/06 , G06F7/04 , G06F9/44 , G06F15/16 , G06F15/173 , G06F15/177 , G06F17/00 , G06F17/30 , G06F17/50 , H04L29/06
CPC分类号： G06Q10/06 , G06Q10/063
摘要： A computer implemented method, data processing system, and computer program product for nominating rules or policies for promotion through a policy hierarchy. An administrator at any level in a policy hierarchy may create a rule or policy. The administrator may then nominate the rule or policy for inclusion in a next higher level in the policy hierarchy. The rule or policy is evaluated at the next higher level. Responsive to an approval of the next higher level to include the rule or policy in the jurisdiction of the next higher level, the rule of policy is provided to all users under the jurisdiction. The nominating, evaluating, and providing steps may then be repeated for each higher level in the policy hierarchy.
摘要翻译：计算机实现的方法，数据处理系统和计算机程序产品，用于通过策略层次结构提名规则或策略。策略层次结构中任何级别的管理员可能会创建规则或策略。然后，管理员可以提名规则或策略以包含在策略层次结构中的下一个较高级别中。规则或策略在下一个更高级别进行评估。响应上一级批准，将规则或者政策纳入下一级管辖范围，向所有管辖的用户提供政策规则。然后可以在策略层次结构中的每个较高级别重复提名，评估和提供步骤。

128. 发明申请

US20090063826A1 Quad aware Locking Primitive 有权
标题翻译：四声识别锁定原语
公开(公告)号：US20090063826A1
公开(公告)日：2009-03-05
申请号：US12264764
申请日：2008-11-04
申请人： Paul E. McKenney , Benedict Jackson , Ramakrishnan Rajamony , Ronald L. Rockhold
发明人： Paul E. McKenney , Benedict Jackson , Ramakrishnan Rajamony , Ronald L. Rockhold
IPC分类号： G06F9/30
CPC分类号： G06F9/52
摘要： A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. At least some of the processors in the system are organized into a hierarchy, and process an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive, and an unconditional lock release primitive for releasing the lock from a particular processor. To prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized.
摘要翻译：一种用于在多处理器计算机系统中有效地处理高争用锁定的方法和计算机系统。系统中的至少一些处理器被组织成层次结构，并响应层次结构处理可中断的锁。该方法利用获取锁的两种替代方法，包括条件锁获取原语和无条件锁获取原语，以及用于从特定处理器释放锁的无条件锁释放原语。为了防止请求锁获取的处理器和释放锁的处理器之间的比赛，利用释放标志。此外，为了确保使用无条件锁定获取原语的处理器被授予锁定，则利用切换标志。

129. 发明授权

US07500036B2 Quad aware locking primitive 有权
公开(公告)号：US07500036B2
公开(公告)日：2009-03-03
申请号：US09753062
申请日：2000-12-28
申请人： Paul E. McKenney , Benedict Jackson , Ramakrishnan Rajamony , Ronald L. Rockhold
发明人： Paul E. McKenney , Benedict Jackson , Ramakrishnan Rajamony , Ronald L. Rockhold
IPC分类号： G06F12/00
CPC分类号： G06F9/52
摘要： A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. The method organizes at least some of the processors in the system into a hierarchy, and processes an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive, and an unconditional lock release primitive for releasing the lock from a particular processor. In order to prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized. Accordingly, efficiency of a computer system may be enhanced with the ability to utilize a locking primitive for an interruptible lock that determines lock selection among processors based upon a hierarchical position of the processor and the primitive utilized for lock selection.

130. 发明申请

US20070282986A1 Rule and Policy Promotion Within A Policy Hierarchy 失效
标题翻译：政策层级中的规则和政策促进
公开(公告)号：US20070282986A1
公开(公告)日：2007-12-06
申请号：US11422239
申请日：2006-06-05
申请人： Rhonda L. Childress , Itzhack Goldberg , Lorraine M. Herger , Ziv Rafalovich , Ramakrishnan Rajamony , Eric Van Hensbergen , Martin J. Tross
发明人： Rhonda L. Childress , Itzhack Goldberg , Lorraine M. Herger , Ziv Rafalovich , Ramakrishnan Rajamony , Eric Van Hensbergen , Martin J. Tross
IPC分类号： G06F15/173
CPC分类号： G06Q10/06 , G06Q10/063
摘要： A computer implemented method, data processing system, and computer program product for nominating rules or policies for promotion through a policy hierarchy. An administrator at any level in a policy hierarchy may create a rule or policy. The administrator may then nominate the rule or policy for inclusion in a next higher level in the policy hierarchy. The rule or policy is evaluated at the next higher level. Responsive to an approval of the next higher level to include the rule or policy in the jurisdiction of the next higher level, the rule of policy is provided to all users under the jurisdiction. The nominating, evaluating, and providing steps may then be repeated for each higher level in the policy hierarchy.
摘要翻译：计算机实现的方法，数据处理系统和计算机程序产品，用于通过策略层次结构提名规则或策略。策略层次结构中任何级别的管理员可能会创建规则或策略。然后，管理员可以提名规则或策略以包含在策略层次结构中的下一个较高级别中。规则或策略在下一个更高级别进行评估。响应上一级批准，将规则或者政策纳入下一级管辖范围，向所有管辖的用户提供政策规则。然后可以在策略层次结构中的每个较高级别重复提名，评估和提供步骤。

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