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121. 发明授权

US06445004B1 Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof 有权
标题翻译：配线用组合物，使用该组合物的布线及其制造方法，使用布线的显示器及其制造方法
公开(公告)号：US06445004B1
公开(公告)日：2002-09-03
申请号：US09617311
申请日：2000-07-14
申请人： Chang-Oh Jeong , Yang-Sun Kim , Myung-Koo Hur , Young-Jae Tak , Mun-Pyo Hong , Chi-Woo Kim , Jang-Soo Kim , Chun-Gi You
发明人： Chang-Oh Jeong , Yang-Sun Kim , Myung-Koo Hur , Young-Jae Tak , Mun-Pyo Hong , Chi-Woo Kim , Jang-Soo Kim , Chun-Gi You
IPC分类号： H01L2904
CPC分类号： G02F1/136286 , G02F1/136227 , G02F1/1368 , G02F2001/13629 , H01L21/28008 , H01L23/4827 , H01L29/42384 , H01L29/4908 , H01L2924/0002 , H01L2924/00
摘要： The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl(+He) or SF6+Cl2(+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched using the Mo or MoW layer as a mask, using an etch gas system that employs a gas such as hydrogen halide and at least one gas selected from CF4, CHF3, CHClF2, CH3F, and C2F6, yields good TFT characteristics, and H2 plasma treatment can further improve the TFT characteristics.
摘要翻译： Mo或MoW组合物层具有小于15μOMEGAcm的低电阻率，并且使用Al合金附魔或Cr附魔被蚀刻成具有平滑的锥角，并且Mo或MoW层用于显示器或半导体显示器以及Al层或Cr层。由于通过调节沉积压力可以沉积Mo或MoW层以便对基底施加低应力，所以可以单独使用单个MoW层作为布线。当在钝化层或栅极绝缘层中形成接触孔时，通过使用聚合物层减少横向蚀刻，使用CF 4 + O 2的蚀刻气体系统可以防止Mo或MoW合金层的蚀刻，以及蚀刻气体 SF6 + HCl（+ He）或SF6 + Cl2（+ He）可以形成要平滑的接触孔的边缘轮廓。此外，当使用Mo或MoW层作为掩模蚀刻形成在Mo或MoW层下面的非晶硅层时，使用采用诸如卤化氢和至少一种选自CF 4，CHF 3的气体的气体的蚀刻气体系统， CHClF 2，CH 3 F和C 2 F 6，产生良好的TFT特性，并且H 2等离子体处理可以进一步提高TFT特性。

122. 发明授权

US08558240B2 Thin film transistor display panel having a gate wire with different thicknesses and manufacturing method thereof 有权
标题翻译：具有不同厚度的栅极线的薄膜晶体管显示面板及其制造方法
公开(公告)号：US08558240B2
公开(公告)日：2013-10-15
申请号：US13010656
申请日：2011-01-20
申请人： Hyung-Jun Kim , Chang-Oh Jeong , Jae-Hong Kim
发明人： Hyung-Jun Kim , Chang-Oh Jeong , Jae-Hong Kim
IPC分类号： H01L27/14
CPC分类号： H01L29/6675 , G02F1/136213 , G02F1/136286 , G02F2001/13629 , H01L27/124 , H01L29/42384
摘要： A thin film transistor display panel includes a substrate, a gate wire on the substrate and including a gate line and a gate electrode; a gate insulating layer on the gate wire; a semiconductor layer on the gate insulating layer; a data wire including a source electrode on the semiconductor layer, a drain electrode opposing the source electrode with respect to the gate electrode, and a data line; a passivation layer on the data wire having a contact hole exposing the drain electrode; and a pixel electrode on the passivation layer and connected to the drain electrode through the contact hole. The gate wire has a first region and second region where the gate line and the gate electrode are positioned, respectively. The thickness of the gate wire in the first region is greater than the thickness of the gate wire in the second region.
摘要翻译：薄膜晶体管显示面板包括衬底，衬底上的栅极线，并且包括栅极线和栅电极; 栅极线上的栅极绝缘层; 栅极绝缘层上的半导体层; 数据线，包括半导体层上的源电极，与源电极相对于栅电极相对的漏电极和数据线; 数据线上的钝化层具有暴露漏电极的接触孔; 以及钝化层上的像素电极，并通过接触孔与漏电极连接。栅极线分别具有栅极线和栅电极所在的第一区域和第二区域。第一区域中的栅极线的厚度大于第二区域中的栅极线的厚度。

123. 发明授权

US08199297B2 Display panel and method for manufacturing the same 有权
标题翻译：显示面板及其制造方法
公开(公告)号：US08199297B2
公开(公告)日：2012-06-12
申请号：US12354115
申请日：2009-01-15
申请人： Joo-Ae Youn , Yang-Ho Bae , Chang-Oh Jeong , Chong-Chul Chai , Pil-Sang Yun , Honglong Ning , Byeong-Beom Kim
发明人： Joo-Ae Youn , Yang-Ho Bae , Chang-Oh Jeong , Chong-Chul Chai , Pil-Sang Yun , Honglong Ning , Byeong-Beom Kim
IPC分类号： G02F1/136 , G02F1/1343
CPC分类号： H01L33/0041 , H01L27/124 , H01L29/458
摘要： A display panel includes; a lower gate line, a lower data line disposed substantially perpendicular to the lower gate line, a thin film transistor (“TFT”) connected to the lower gate line and the lower data line, an insulating layer disposed on the lower gate line, the lower data line, and the TFT and having a plurality of trenches exposing the lower gate line and the lower data line, an upper gate line disposed in the trench on the lower gate line, an upper data line disposed in the trench on the lower data line, and a pixel electrode connected to the TFT.
摘要翻译：显示面板包括：下栅极线，基本上垂直于下栅极线设置的下数据线，连接到下栅极线和下数据线的薄膜晶体管（“TFT”），设置在下栅极线上的绝缘层，下数据线和TFT，并且具有暴露下栅极线和下数据线的多个沟槽，设置在下栅极线上的沟槽中的上栅极线，设置在下数据上的沟槽中的上数据线线和与TFT连接的像素电极。

124. 发明授权

US08198657B2 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08198657B2
公开(公告)日：2012-06-12
申请号：US12652379
申请日：2010-01-05
申请人： Dong-Hoon Lee , Do-Hyun Kim , Chang-Oh Jeong , O-Sung Seo , Xin-Xing Li
发明人： Dong-Hoon Lee , Do-Hyun Kim , Chang-Oh Jeong , O-Sung Seo , Xin-Xing Li
IPC分类号： H01L23/52 , H01L21/82
CPC分类号： H01L27/124 , H01L29/78618
摘要： A thin film transistor array panel includes an insulating substrate. A gate line is formed on the insulating substrate and has a gate electrode. A gate insulating layer is formed on the gate line. A semiconductor layer is formed on the gate insulating layer and overlaps the gate electrode. Diffusion barriers are formed on the semiconductor layer and contain nitrogen. A data line crosses the gate line and has a source electrode partially contacting the diffusion barriers and a drain electrode partially contacting the diffusion barriers and facing the source electrode. The drain electrode is on the gate electrode. A pixel electrode is electrically connected to the drain electrode.
摘要翻译：薄膜晶体管阵列面板包括绝缘基板。在绝缘基板上形成栅极线，并具有栅电极。在栅极线上形成栅绝缘层。半导体层形成在栅极绝缘层上并与栅电极重叠。在半导体层上形成扩散阻挡层并含有氮。数据线与栅极线交叉，并且具有部分地接触扩散阻挡层的源电极和部分地接触扩散阻挡层并面向源电极的漏电极。漏电极在栅电极上。像素电极电连接到漏电极。

125. 发明授权

US07968385B2 Thin film transistor panel and fabricating method thereof 有权
标题翻译：薄膜晶体管面板及其制造方法
公开(公告)号：US07968385B2
公开(公告)日：2011-06-28
申请号：US12605566
申请日：2009-10-26
申请人： Chang-Oh Jeong , Dong-Hoon Lee
发明人： Chang-Oh Jeong , Dong-Hoon Lee
IPC分类号： H01L21/00
CPC分类号： H01L27/12 , H01L27/124 , H01L29/41733 , H01L29/66765
摘要： A thin film transistor panel includes; an insulating substrate, a gate line including a gate electrode disposed on the insulating substrate, a gate insulating layer disposed on the gate electrode, a semiconductor layer disposed on the gate insulating layer, the semiconductor layer including a sidewall, a data line including a source electrode disposed on the semiconductor layer, a drain electrode disposed substantially opposite to and spaced apart from the source electrode, a first protective film disposed on the data line, the first protective film including a sidewall, a second protective film disposed on the first protective film and including a sidewall, and a pixel electrode electrically connected to the drain electrode, wherein the sidewall of the second protective film is disposed inside an area where the sidewall of the first protective film is disposed, and the source electrode and the drain electrode cover the sidewall of the semiconductor layer.
摘要翻译：薄膜晶体管面板包括：绝缘基板，包括设置在绝缘基板上的栅电极的栅极线，设置在栅极上的栅极绝缘层，设置在栅极绝缘层上的半导体层，包括侧壁的半导体层，包括源极的数据线设置在所述半导体层上的电极，与所述源极电极基本相对并间隔设置的漏电极，设置在所述数据线上的第一保护膜，所述第一保护膜包括侧壁，设置在所述第一保护膜上的第二保护膜并且包括侧壁和与漏电极电连接的像素电极，其中第二保护膜的侧壁设置在设置有第一保护膜的侧壁的区域的内侧，源电极和漏电极覆盖半导体层的侧壁。

126. 发明申请

US20110031117A1 SPUTTERING TARGET APPARATUS 有权
标题翻译：喷射目标装置
公开(公告)号：US20110031117A1
公开(公告)日：2011-02-10
申请号：US12779459
申请日：2010-05-13
申请人： Do-Hyun KIM , Dong-Hoon Lee , Chang-Oh Jeong
发明人： Do-Hyun KIM , Dong-Hoon Lee , Chang-Oh Jeong
IPC分类号： C23C14/34
CPC分类号： C23C14/3407 , C23C14/3464 , H01J37/342 , H01J37/3435
摘要： A sputtering target apparatus is provided. The sputtering target apparatus includes a first target assembly including a first target array having a first target, a second target disposed adjacent to the first target, and a first target dividing region disposed between the first and second targets, the first target assembly extending along a first direction, wherein the first target dividing region has a longitudinal cross-section that is oblique with respect to the first direction.
摘要翻译：提供溅射靶设备。溅射靶设备包括：第一目标组件，其包括具有第一靶的第一靶阵列，与第一靶相邻设置的第二靶;以及设置在第一靶和第二靶之间的第一靶分离区，第一方向，其中第一目标分割区域具有相对于第一方向倾斜的纵向横截面。

127. 发明申请

US20090090942A1 Wiring structure, array substrate, display device having the same and method of manufacturing the same 审中-公开
标题翻译：布线结构，阵列基板，显示装置及其制造方法
公开(公告)号：US20090090942A1
公开(公告)日：2009-04-09
申请号：US12231709
申请日：2008-09-04
申请人： Kyong-Sub Kim , Sang-Un Nam , Chang-Oh Jeong , Weon-Sik Oh , Sung-Lak Choi , Soo-Im Jeong , Jae-Ho Eo
发明人： Kyong-Sub Kim , Sang-Un Nam , Chang-Oh Jeong , Weon-Sik Oh , Sung-Lak Choi , Soo-Im Jeong , Jae-Ho Eo
IPC分类号： H01L29/786 , H01B5/14 , B05D5/12 , H01L21/336
CPC分类号： H01L27/124 , H01L29/458 , H01L29/4908
摘要： A wiring structure includes a substrate, a copper oxide layer having 16˜39 at % oxygen on the substrate and a copper layer on the copper oxide layer. The copper oxide layer has a thickness of 10-1000 Å and the copper layer has a thickness of 300-8000 Å. The copper layer and the copper oxide layer further have an alloy element less than 10 wt % and the alloy element is selected from the group of Ag, Ni, Mg, Zr, N.
摘要翻译：布线结构包括基板，在基板上具有16〜39at％的氧的氧化铜层和氧化铜层上的铜层。铜氧化物层的厚度为10-1000埃，铜层的厚度为300-8000埃。铜层和氧化铜层还具有小于10重量％的合金元素，合金元素选自Ag，Ni，Mg，Zr，N组。

128. 发明授权

US07396695B2 Wire structure, a thin film transistor substrate of using the wire structure and a method of manufacturing the same 失效
标题翻译：线结构，使用线结构的薄膜晶体管基板及其制造方法
公开(公告)号：US07396695B2
公开(公告)日：2008-07-08
申请号：US11170251
申请日：2005-06-29
申请人： Beom-Seok Cho , Chang-Oh Jeong
发明人： Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： H01L21/00 , H01L21/84 , H01L21/82 , H01L29/15 , H01L29/04 , H01L31/20 , H01L27/12
CPC分类号： G02F1/136227 , G02F1/136213 , G02F2001/13629
摘要： A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire include triple layers of an adhesion layer, a Ag containing layer and a protection layer. The adhesion layer includes one of Cr, Cr alloy, Ti, Ti alloy, Mo, Mo alloy, Ta and Ta alloy, the Ag containing layer includes Ag or Ag alloy, and the protection layer includes one of IZO, Mo, Mo alloy, Cr and Cr alloy.
摘要翻译：薄膜晶体管阵列面板包括绝缘基板，形成在绝缘基板上的栅极线。栅极绝缘层覆盖栅极线。在栅极绝缘层上形成半导体图形。在栅极绝缘层和半导体图案上形成具有源电极，漏电极和数据线的数据线。在数据线上形成保护层。在保护层上形成通过接触孔与漏电极连接的像素电极。栅极线和数据线包括粘合层，含Ag层和保护层的三层。粘合层包括Cr，Cr合金，Ti，Ti合金，Mo，Mo合金，Ta和Ta合金中的一种，含Ag层包括Ag或Ag合金，保护层包括IZO，Mo，Mo合金， Cr和Cr合金。

129. 发明授权

US07375373B2 Thin film transistor array panel 失效
标题翻译：薄膜晶体管阵列面板
公开(公告)号：US07375373B2
公开(公告)日：2008-05-20
申请号：US10482256
申请日：2002-07-02
申请人： Jae-Gab Lee , Bong-Joo Kang , Beom-Seok Cho , Chang-Oh Jeong
发明人： Jae-Gab Lee , Bong-Joo Kang , Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： H01L21/00 , H01L27/01 , H01L21/84
CPC分类号： H01L27/12 , H01L27/124 , H01L29/458 , H01L29/4908 , H01L29/66765
摘要： A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.
摘要翻译：薄膜晶体管阵列面板包括绝缘基板，形成在绝缘基板上的栅极线。栅极绝缘层覆盖栅极线。在栅极绝缘层上形成半导体图形。在栅极绝缘层和半导体图案上形成具有源电极，漏电极和数据线的数据线。在数据线上形成保护层。在保护层上形成通过接触孔与漏电极连接的像素电极。栅极线和数据线由含有Ag的Ag合金和包含选自Zn，In，Sn和Cr中的至少一种的添加剂制成。

130. 发明授权

US07276731B2 Wiring line assembly and method for manufacturing the same, and thin film transistor array substrate having the wiring line assembly and method for manufacturing the same 有权
标题翻译：配线组装及其制造方法以及具有布线组件的薄膜晶体管阵列基板及其制造方法
公开(公告)号：US07276731B2
公开(公告)日：2007-10-02
申请号：US11053833
申请日：2005-02-10
申请人： Chang-Oh Jeong , Bong-Joo Kang , Jae-Gab Lee
发明人： Chang-Oh Jeong , Bong-Joo Kang , Jae-Gab Lee
IPC分类号： H01L29/04
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/13629 , G02F2001/136295 , H01L23/53242 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/4908 , H01L2924/0002 , H01L2924/00
摘要： In a method for fabricating a thin film transistor array substrate, a glass substrate undergoes an oxygen plasma treatment. A silver or silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a gate line assembly proceeding in the horizontal direction. The gate line assembly includes gate lines, gate electrodes, and gate pads. Thereafter, a silicon nitride-based gate insulating layer is deposited onto the substrate, and a semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. The semiconductor layer and the ohmic contact layer are HF-treated. A silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a data line assembly. The data line assembly includes data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer based on silicon nitride or an organic material is deposited onto the substrate, and patterned through dry etching such that the protective layer bears contact holes exposing the drain electrodes, the gate pads and the data pads, respectively. An indium zinc oxide or indium tin oxide-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, and subsidiary gate and data pads. The pixel electrodes are electrically connected to the drain electrodes, and the subsidiary gate and data pads to the gate and data pads.
摘要翻译：在制造薄膜晶体管阵列基板的方法中，玻璃基板进行氧等离子体处理。将银或银合金基导电层沉积到衬底上，并被图案化，从而形成在水平方向上进行的栅极线组件。栅极线组件包括栅极线，栅电极和栅极焊盘。此后，在衬底上沉积氮化硅基栅极绝缘层，并且在栅极绝缘层上依次形成半导体层和欧姆接触层。对半导体层和欧姆接触层进行HF处理。将银合金基导电层沉积到衬底上，并被图案化从而形成数据线组件。数据线组件包括跨越栅极线，源电极，漏电极和数据焊盘的数据线。基于氮化硅或有机材料的保护层沉积到衬底上，并通过干蚀刻图案化，使得保护层分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。将氧化铟锌或铟锡氧化物基层沉积在衬底上，并被图案化，从而形成像素电极，以及辅助栅极和数据焊盘。像素电极电连接到漏电极，辅助栅极和数据焊盘电连接到栅极和数据焊盘。

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