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121. 发明授权

US07321148B2 Capacitor constructions and rugged silicon-containing surfaces 失效
标题翻译：电容器结构和坚固的含硅表面
公开(公告)号：US07321148B2
公开(公告)日：2008-01-22
申请号：US10913275
申请日：2004-08-06
申请人： Guy T. Blalock , Lyle D. Breiner , Er-Xuan Ping , Shenlin Chen
发明人： Guy T. Blalock , Lyle D. Breiner , Er-Xuan Ping , Shenlin Chen
IPC分类号： H01L27/108
CPC分类号： H01L27/10852 , H01L28/84 , Y10S438/964
摘要： The invention encompasses a method of forming a rugged silicon-containing surface. A layer comprising amorphous silicon is provided within a reaction chamber at a first temperature. The temperature is increased to a second temperature at least 40° C. higher than the first temperature while flowing at least one hydrogen isotope into the chamber. After the temperature reaches the second temperature, the layer is seeded with seed crystals. The seeded layer is then annealed to form a rugged silicon-containing surface. The rugged silicon-containing surface can be incorporated into a capacitor construction. The capacitor construction can be incorporated into a DRAM cell, and the DRAM cell can be utilized in an electronic system.
摘要翻译：本发明包括形成坚固的含硅表面的方法。在第一温度下在反应室内提供包含非晶硅的层。当将至少一个氢同位素流入室内时，将温度升高至高于第一温度至少40℃的第二温度。温度达到第二个温度后，该层用晶种接种。接种层然后退火以形成坚固的含硅表面。坚固的含硅表面可以结合到电容器结构中。电容器结构可以并入到DRAM单元中，并且可以在电子系统中使用DRAM单元。

122. 发明授权

US07291555B2 Methods of forming a reaction product and methods of forming a conductive metal silicide by reaction of metal with silicon 有权
标题翻译：形成反应产物的方法和通过金属与硅的反应形成导电金属硅化物的方法
公开(公告)号：US07291555B2
公开(公告)日：2007-11-06
申请号：US11488579
申请日：2006-07-17
申请人： Gurtej S. Sandhu , Guy T. Blalock
发明人： Gurtej S. Sandhu , Guy T. Blalock
IPC分类号： H01L21/4763
CPC分类号： C23C14/5826 , H01L21/28512 , H01L21/28518
摘要： A method of forming a reaction product includes providing a semiconductor substrate comprising a first material. A second material is formed over the first material. The first and second materials are of different compositions, and are proximate one another at an interface. The first and second materials as being proximate one another at the interface are capable of reacting with one another at some minimum reaction temperature when in an inert non-plasma atmosphere at a pressure. The interface is provided at a processing temperature which is at least 50° C. below the minimum reaction temperature, and is provided at the pressure. With the interface at the processing temperature and at the pressure, the substrate is exposed to a plasma effective to impart a reaction of the first material with the second material to form a reaction product third material of the first and second materials over the first material. Other aspects and implementations are contemplated.
摘要翻译：形成反应产物的方法包括提供包含第一材料的半导体衬底。在第一材料上形成第二材料。第一和第二材料具有不同的组成，并且在界面处彼此靠近。在惰性非等离子体气氛中在压力下，在界面处彼此接近的第一和第二材料能够在某些最小反应温度下彼此反应。界面的设置处于低于最低反应温度的至少50℃的处理温度，并且在压力下提供。利用处理温度和压力下的界面，将基板暴露于等离子体中，以有效地使第一材料与第二材料发生反应，从而在第一材料上形成第一和第二材料的反应产物第三材料。考虑了其他方面和实现。

123. 发明授权

US07262612B2 Methods for evaluating characteristics of a plasma or the effects of a plasma on a substrate 失效
标题翻译：用于评估等离子体的特性或等离子体对衬底的影响的方法
公开(公告)号：US07262612B2
公开(公告)日：2007-08-28
申请号：US11190457
申请日：2005-07-27
申请人： Guy T. Blalock
发明人： Guy T. Blalock
IPC分类号： G01R31/02
CPC分类号： G01R19/0046 , G01R31/2831 , Y10T29/49155
摘要： A method for evaluating characteristics of a plasma or the effects of the plasma on a substrate includes introducing a plasma probe into a reaction chamber. The plasma probe may be introduced into the chamber with or without a substrate. The plasma probe is exposed to substantially the same conditions to which the substrate is, has been, or will be exposed. The plasma probe may include features that represent corresponding features on the substrate. One or more characteristics of the plasma, or its effects on the plasma probe, may be evaluated at one or more locations on the plasma probe.
摘要翻译：用于评价等离子体的特性或等离子体对基板的影响的方法包括将等离子体探针引入反应室。等离子体探针可以被引入到具有或不具有基底的腔室中。等离子体探针暴露于基本上已经或将要暴露于的基本相同的条件。等离子体探针可以包括表示衬底上相应特征的特征。可以在等离子体探针上的一个或多个位置评估等离子体的一个或多个特性或其对等离子体探针的影响。

124. 发明授权

US07248063B2 Plasma probe systems 失效
标题翻译：等离子探头系统
公开(公告)号：US07248063B2
公开(公告)日：2007-07-24
申请号：US11190527
申请日：2005-07-27
申请人： Guy T. Blalock
发明人： Guy T. Blalock
IPC分类号： G01R31/02
CPC分类号： G01R19/0046 , G01R31/2831 , Y10T29/49155
摘要： A plasma probe system includes a plasma probe, at least one meter, and a diagnostic apparatus. The probe may include a substrate having substantially the same properties as those of a substrate to be processed, a bottom electrode layer located over the substrate and electrically isolated therefrom, a dielectric layer positioned over the bottom electrode layer including apertures through which one or more electrodes of the bottom electrode layer are exposed, and at least one upper electrode layer that is electrically isolated from the bottom electrode layer by way of the dielectric layer. Electrodes of the bottom and upper electrode layers communicate with meters which may provide real-time data representative of one or more properties of a region of a plasma to which the electrodes are exposed.
摘要翻译：等离子体探针系统包括等离子体探针，至少一米和诊断装置。探针可以包括具有与待处理的基底基本上相同的性质的基底，位于基底上并与之电隔离的底部电极层，位于底部电极层上方的电介质层，该电介质层包括一个或多个电极暴露出底部电极层，以及至少一个上部电极层，其通过电介质层与底部电极层电隔离。底部和上部电极层的电极与可提供表示电极暴露于其中的等离子体区域的一个或多个特性的实时数据通信。

125. 发明授权

US07215838B2 Resistive heater for thermo optic device 有权
标题翻译：用于热光器件的电阻加热器
公开(公告)号：US07215838B2
公开(公告)日：2007-05-08
申请号：US10929904
申请日：2004-08-30
申请人： Gurtej Singh Sandhu , Guy T. Blalock
发明人： Gurtej Singh Sandhu , Guy T. Blalock
IPC分类号： G02F1/295 , H01L21/00
CPC分类号： G02B6/125 , G02F1/0102 , G02F1/0147 , G02F1/2257 , G02F2201/30 , G02F2201/307 , G02F2202/104
摘要： Resistive heaters formed in two mask counts on a surface of a grating of a thermo optic device thereby eliminating one mask count from prior art manufacturing methods. The resistive heater is comprised of a heater region and a conductive path region formed together in a first mask count from a relatively high resistance material. A conductor formed from a relatively low resistance material is formed directly on the conductive path region in a second mask count. Thermo optic devices formed by these two mask count methods are also described.
摘要翻译：在热光器件的光栅的表面上形成两个掩模计数的电阻加热器，从而从现有技术的制造方法中消除一个掩模计数。电阻加热器包括加热器区域和形成在来自相对高电阻材料的第一掩模计数中的导电路径区域。由相对低电阻材料形成的导体以第二掩模计数直接形成在导电路径区域上。还描述了通过这两种掩模计数方法形成的热光学器件。

126. 发明授权

US07129724B2 Plasma probe 失效
标题翻译：等离子探针
公开(公告)号：US07129724B2
公开(公告)日：2006-10-31
申请号：US11190437
申请日：2005-07-27
申请人： Guy T. Blalock
发明人： Guy T. Blalock
IPC分类号： G01R31/02
CPC分类号： G01R19/0046 , G01R31/2831 , Y10T29/49155
摘要： A plasma probe includes a substrate having substantially the same properties as those of a substrate to be processed, a bottom electrode layer located over the substrate and electrically isolated therefrom, a dielectric layer positioned over the bottom electrode layer including apertures through which one or more electrodes of the bottom electrode layer are exposed, and at least one upper electrode layer electrically isolated from the bottom electrode layer by way of the dielectric layer. Electrodes of the bottom and upper electrode layers may communicate with meters which may provide real-time data representative of one or more properties of a region of a plasma to which the electrodes are exposed. The plasma probe may be fabricated by forming the bottom electrode layer over the substrate and separately forming one or more upper electrode layers over a sacrificial substrate. These structures are assembled with the dielectric layer therebetween.
摘要翻译：等离子体探针包括具有与待处理衬底基本相同性质的衬底，位于衬底上并与其电隔离的底电极层，位于底电极层上的电介质层，该电介质层包括一个或多个电极暴露出底部电极层，以及通过电介质层与底部电极层电隔离的至少一个上部电极层。底部电极层和上部电极层的电极可以与可提供表示电极暴露于其中的等离子体区域的一个或多个特性的实时数据的仪表通信。可以通过在衬底上形成底电极层并且在牺牲衬底上分开形成一个或多个上电极层来制造等离子体探针。这些结构与介电层组装在一起。

127. 发明授权

US07119031B2 Methods of forming patterned photoresist layers over semiconductor substrates 有权
公开(公告)号：US07119031B2
公开(公告)日：2006-10-10
申请号：US10879367
申请日：2004-06-28
申请人： Guy T. Blalock , Gurtej S. Sandhu , Jon P. Daley
发明人： Guy T. Blalock , Gurtej S. Sandhu , Jon P. Daley
IPC分类号： H01L21/31
CPC分类号： G03F7/091 , H01L21/0276
摘要： This invention includes methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a porous antireflective coating is formed over a semiconductor substrate. A photoresist footer-reducing fluid is provided within pores of the porous antireflective coating. A positive photoresist is formed over the porous antireflective coating having the fluid therein. The positive photoresist is patterned and developed to form a patterned photoresist layer, with the fluid within the pores being effective to reduce photoresist footing in the patterned photoresist layer than would otherwise occur in the absence of the fluid within the pores. Other aspects and implementations are contemplated.

128. 发明授权

US07115926B1 Capacitor constructions, DRAM constructions, and semiconductive material assemblies 有权
标题翻译：电容器结构，DRAM结构和半导体材料组件
公开(公告)号：US07115926B1
公开(公告)日：2006-10-03
申请号：US09603147
申请日：2000-06-23
申请人： John T. Moore , Guy T. Blalock , Scott Jeffrey DeBoer
发明人： John T. Moore , Guy T. Blalock , Scott Jeffrey DeBoer
IPC分类号： H01L27/108
CPC分类号： H01L28/40 , H01L21/31116 , H01L21/3146 , Y10S438/924 , Y10S438/97
摘要： In one aspect, the invention includes an etching process, comprising: a) providing a first material over a substrate, the first material comprising from about 2% to about 20% carbon (by weight); b) providing a second material over the first material; and c) etching the second material at a faster rate than the first material. In another aspect, the invention includes a capacitor forming method, comprising: a) forming a wordline over a substrate; b) defining a node proximate the wordline; c) forming an etch stop layer over the wordline, the etch stop layer comprising carbon; d) forming an insulative layer over the etch stop layer; e) etching through the insulative layer to the etch stop layer to form an opening through the insulative layer; and e) forming a capacitor construction comprising a storage node, dielectric layer and second electrode, at least a portion of the capacitor construction being within the opening. In yet another aspect, the invention includes a semiconductive material assembly, comprising: a) a semiconductive substrate; and b) a layer over the semiconductive substrate, the layer comprising silicon, nitrogen and carbon.
摘要翻译：一方面，本发明包括蚀刻工艺，其包括：a）在衬底上提供第一材料，所述第一材料包含约2％至约20％的碳（重量）; b）在第一材料上提供第二材料; 以及c）以比所述第一材料更快的速率蚀刻所述第二材料。另一方面，本发明包括电容器形成方法，包括：a）在衬底上形成字线; b）定义靠近字线的节点; c）在所述字线上形成蚀刻停止层，所述蚀刻停止层包含碳; d）在所述蚀刻停止层上形成绝缘层; e）通过绝缘层蚀刻到蚀刻停止层以形成穿过绝缘层的开口; 以及e）形成包括存储节点，电介质层和第二电极的电容器结构，所述电容器结构的至少一部分在所述开口内。在另一方面，本发明包括半导体材料组件，其包括：a）半导体衬底; 以及b）半导体衬底上的层，该层包含硅，氮和碳。

129. 发明授权

US07022618B2 Method of forming a conductive contact 失效
标题翻译：形成导电触点的方法
公开(公告)号：US07022618B2
公开(公告)日：2006-04-04
申请号：US10664739
申请日：2003-09-18
申请人： Sujit Sharan , Gurtej S. Sandhu , Guy T. Blalock
发明人： Sujit Sharan , Gurtej S. Sandhu , Guy T. Blalock
IPC分类号： H01L21/461
CPC分类号： H01L21/3065 , H01L21/02046 , H01L21/28518 , H01L21/3085 , H01L21/76814
摘要： In one implementation, an etching process includes forming a carbon containing material over a substrate and plasma etching at a temperature of at least 400° C. using a hydrogen or oxygen containing plasma. In one implementation, a plasma etching process includes forming openings in a masking layer over a substrate and etching material beneath the masking through the openings. The masking layer is removed and the substrate is plasma etched at a temperature of at least 400° C. In one implementation, an etching process includes forming a residue over the substrate during a first etching and subsequently plasma etching to remove the residue. In one implementation, a chemical vapor deposition process includes positioning a semiconductor substrate within a plasma enhanced chemical vapor deposition reactor, plasma etching using a first gas chemistry, depositing a material over the substrate within the reactor using a second gas chemistry.
摘要翻译：在一个实施方案中，蚀刻工艺包括在衬底上形成含碳材料，并使用含氢或含氧等离子体在至少400℃的温度下进行等离子体蚀刻。在一个实施方案中，等离子体蚀刻工艺包括在衬底上的掩模层中形成开口，并通过开口在掩模下方蚀刻材料。去除掩模层，并且在至少400℃的温度下对衬底进行等离子体蚀刻。在一个实施方案中，蚀刻工艺包括在第一蚀刻期间在衬底上形成残余物，随后在等离子体蚀刻中除去残余物。在一个实施方案中，化学气相沉积工艺包括将等离子体增强化学气相沉积反应器内的半导体衬底定位，使用第一气体化学的等离子体蚀刻，使用第二气体化学物质在反应器内的衬底上沉积材料。

130. 发明授权

US07006746B2 Waveguide for thermo optic device 有权
标题翻译：波导用于光电装置
公开(公告)号：US07006746B2
公开(公告)日：2006-02-28
申请号：US10233000
申请日：2002-08-29
申请人： Guy T. Blalock , Howard E. Rhodes , Vishnu K. Agarwal , Gurtej Singh Sandhu , James S. Foresi , Jean-Francois Viens , Dale G. Fried
发明人： Guy T. Blalock , Howard E. Rhodes , Vishnu K. Agarwal , Gurtej Singh Sandhu , James S. Foresi , Jean-Francois Viens , Dale G. Fried
IPC分类号： G02B6/10
CPC分类号： G02F1/025 , G02B6/125 , G02B6/136 , G02B2006/12107 , G02B2006/12164 , G02F1/0147 , G02F2203/15
摘要： A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.
摘要翻译：波导和谐振器形成在热光器件的下包层上，每个具有基本相等的形成高度。此后，波导的形成高度被衰减。以这种方式，波导和谐振器在波导和谐振器前面或彼此面对的区域（与现有技术相比）中的波导和谐振器之间的纵横比，从而恢复波导和光栅之间的同步性并允许更高的带宽配置要使用的。在形成谐振器和波导之后，通过光掩模和蚀刻波导来实现波导衰减。在一个实施例中，在沉积上部包层之后进行光掩模和蚀刻。另一方面，它是在沉积之前进行的。还教导了具有这些波导的热光器件，热光封装和光纤系统。

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