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121. 发明授权

US07499359B2 Temperature sensor instruction signal generator and semiconductor memory device having the same 失效
标题翻译：温度传感器指令信号发生器和具有相同功能的半导体存储器件
公开(公告)号：US07499359B2
公开(公告)日：2009-03-03
申请号：US11354125
申请日：2006-02-15
申请人： Jong-Hyun Choi , Dong-Il Seo , Yong-Gu Kang , Jung-Yong Choi , Young-Hun Seo
发明人： Jong-Hyun Choi , Dong-Il Seo , Yong-Gu Kang , Jung-Yong Choi , Young-Hun Seo
IPC分类号： G11C7/00
CPC分类号： G01K7/01
摘要： A temperature sensor instruction signal generator, which may drive a temperature sensor, and a semiconductor memory device including the same. The temperature sensor instruction signal generator may generate an instruction signal that instruct the operation of the temperature sensor using at least one of a master clock (CLK) signal, a clock enable (CKE) signal, a row address selection (RAS) signal, a column address selection (CAS) signal, a write enable (WE) signal, and a chip selection (CS) signal, wherein the instruction signal may be enabled corresponding to at least one of a self refresh mode, an auto refresh mode, and a long tRAS mode. The semiconductor memory device may include a temperature sensor and the temperature sensor instruction signal generator.
摘要翻译：可以驱动温度传感器的温度传感器指令信号发生器和包括该温度传感器的半导体存储器件。温度传感器指令信号发生器可以使用主时钟（CLK）信号，时钟使能（CKE）信号，行地址选择（RAS）信号，列地址选择（CAS）信号，写使能（WE）信号和芯片选择（CS）信号，其中所述指令信号可以对应于自刷新模式，自动刷新模式和长tRAS模式。半导体存储器件可以包括温度传感器和温度传感器指令信号发生器。

122. 发明申请

US20080224129A1 FLAT PANEL DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：平板显示装置及其制造方法
公开(公告)号：US20080224129A1
公开(公告)日：2008-09-18
申请号：US12047619
申请日：2008-03-13
申请人： Jong-Hyun Choi , Woo-Sik Jun
发明人： Jong-Hyun Choi , Woo-Sik Jun
IPC分类号： H01L51/56 , H01L21/77
CPC分类号： H01L27/1277 , H01L21/02532 , H01L21/02672 , H01L27/1255 , H01L27/3244
摘要： A flat panel display device, more particularly, an Organic Light Emitting Diode (OLED) display device having uniform electrical characteristics and a method of fabricating the same include: a thin film transistor of which a semiconductor layer including a source, a drain, and a channel region formed in a super grain silicon (SGS) crystallization growth region; a capacitor formed in an SGS crystallization seed region; and an OLED electrically connected to the thin film transistor. Further, a length of the channel region of the silicon layer is parallel with the growth direction in the SGS growth region to improve the electrical properties thereof.
摘要翻译：平板显示装置，特别是具有均匀电特性的有机发光二极管（OLED）显示装置及其制造方法包括：薄膜晶体管，其包括源极，漏极和漏极的半导体层形成在超晶硅（SGS）结晶生长区中的沟道区; 在SGS结晶种子区域形成的电容器; 以及电连接到薄膜晶体管的OLED。此外，硅层的沟道区域的长度与SGS生长区域中的生长方向平行，以改善其电性能。

123. 发明授权

US07397281B2 Input/output circuit of semiconductor memory device and input/output method thereof 有权
标题翻译：半导体存储器件的输入/输出电路及其输入/输出方法
公开(公告)号：US07397281B2
公开(公告)日：2008-07-08
申请号：US11348582
申请日：2006-02-06
申请人： Jong-Hyun Choi , Young-Hun Seo
发明人： Jong-Hyun Choi , Young-Hun Seo
IPC分类号： H03K19/0175
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , H03K19/0005
摘要： An input/output circuit for a semiconductor memory device, including a data output circuit configured to buffer output data in the semiconductor memory device in response to an input/output enable signal to output the buffered output data to an input/output signal line, a data input circuit configured to receive input data from the input/output signal line and buffer the input data to transfer the buffered input data to the semiconductor memory device, and a load controller configured to control a load on the input/output signal line in response to the input/output enable signal.
摘要翻译：一种用于半导体存储器件的输入/输出电路，包括数据输出电路，配置为响应于输入/输出使能信号缓冲半导体存储器件中的输出数据，以将缓冲的输出数据输出到输入/输出信号线，数据输入电路，被配置为从输入/输出信号线接收输入数据并缓冲输入数据以将缓冲的输入数据传送到半导体存储器件;以及负载控制器，被配置为响应于控制输入/输出信号线上的负载到输入/输出使能信号。

124. 发明授权

US07323894B2 Needle alignment verification circuit and method for semiconductor device 有权
标题翻译：针对对准验证电路及半导体器件的方法
公开(公告)号：US07323894B2
公开(公告)日：2008-01-29
申请号：US11360827
申请日：2006-02-23
申请人： Jong-Hyun Choi , Young-Hun Seo
发明人： Jong-Hyun Choi , Young-Hun Seo
IPC分类号： G01R31/02
CPC分类号： G01R1/06794
摘要： A needle alignment verification circuit includes a sensor pad, a first transmission line, a control element, a data pad, a second transmission line, and a response element. The sensor pad includes an insulation part and a conduction part. The first transmission line is electrically connected to the conduction part and to the interior of the semiconductor device. The control element asserts the first transmission line at a first logic state, and upon receiving the probe signal at the conduction part, transitions the logic state of the first transmission line to a second logic state. The second transmission line provides a predetermined signal to the data pad. The response element controls the second transmission line so that the second transmission line has the state of a verification result voltage for a misalignment state in response to the second logic state.
摘要翻译：针对准验证电路包括传感器焊盘，第一传输线，控制元件，数据焊盘，第二传输线和响应元件。传感器垫包括绝缘部分和导电部分。第一传输线电连接到导电部分和半导体器件的内部。控制元件在第一逻辑状态下使第一传输线断言，并且在接收到导通部分的探测信号时，将第一传输线的逻辑状态转换到第二逻辑状态。第二传输线向数据焊盘提供预定的信号。响应元件控制第二传输线，使得第二传输线响应于第二逻辑状态具有用于不对准状态的验证结果电压的状态。

125. 发明申请

US20070238223A1 Apparatus and method for signal bus line layout in semiconductor device 失效
标题翻译：半导体器件中信号总线布线的装置和方法
公开(公告)号：US20070238223A1
公开(公告)日：2007-10-11
申请号：US11809593
申请日：2007-06-01
申请人： Chang-Ho Lee , Jong-Hyun Choi
发明人： Chang-Ho Lee , Jong-Hyun Choi
IPC分类号： H01L21/00
CPC分类号： H01L23/5286 , H01L24/06 , H01L2224/02166 , H01L2224/05554 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01024 , H01L2924/01033 , H01L2924/01068 , H01L2924/01074 , H01L2924/14
摘要： A device and method for layout and fabrication of power supply bus lines in an integrated circuit such as a memory circuit are described. In accordance with the present invention, power bus lines and bonding pads of the circuit are not necessarily formed in both edge regions and center regions of the device. The bonding pads are formed in the region according to the package being used, and the power bus lines are formed in the other region. This is accomplished by forming the bonding pads over landing pads. Landing pads are formed in both the center region and the edge region under the top surface of the device. If the device is to be packaged in an edge pad configuration, the bonding pads are formed over the landing pads in the edge region, and power supply bus lines can be formed over the landing pads in the center region. Similarly, if the device is to be packaged in a center pad configuration, the bonding pads are formed over the landing pads in the center region, and the power supply bus lines can be formed over the landing pads in the edge region. The bonding pads are connected to the landing pads by conductive vias. Because the power bus lines are not formed in the same region as bonding pads, they can occupy a relatively large portion of the region in which they are formed. That is, they can be made much larger than they would be using the conventional approach in which both bonding pads and power bus lines are formed in the same region. As a result, the power noise drawbacks of the conventional approach are eliminated.
摘要翻译：描述了诸如存储器电路的集成电路中的电源总线布线和制造的装置和方法。根据本发明，电路的电源总线线路和接合焊盘不一定形成在器件的两个边缘区域和中心区域中。接合焊盘形成在根据使用的封装的区域中，并且电力总线线路形成在另一区域中。这通过在着陆垫上形成接合垫来实现。着陆垫形成在装置的上表面下方的中心区域和边缘区域中。如果将该器件封装在边缘焊盘配置中，则焊接区形成在边缘区域的着陆焊盘之上，并且电源总线可以形成在中心区域的着陆焊盘上。类似地，如果要将器件封装在中心焊盘结构中，则接合焊盘形成在中心区域的着陆焊盘之上，并且电源总线可以形成在边缘区域的着陆焊盘上。接合焊盘通过导电通孔连接到着陆焊盘。由于电力总线线路不形成在与接合焊盘相同的区域中，所以它们可以占据其形成区域的较大部分。也就是说，它们可以比使用在相同区域中形成接合焊盘和电力总线线路的常规方法大得多。结果，消除了常规方法的功率噪声缺点。

126. 发明授权

US07260002B2 Methods and devices for preventing data stored in memory from being read out 有权
标题翻译：用于防止存储在存储器中的数据被读出的方法和装置
公开(公告)号：US07260002B2
公开(公告)日：2007-08-21
申请号：US10761396
申请日：2004-01-22
申请人： Jong-Hyun Choi , Dong-Il Seo , Kyu-Chan Lee , Young-Hun Seo
发明人： Jong-Hyun Choi , Dong-Il Seo , Kyu-Chan Lee , Young-Hun Seo
IPC分类号： G11C7/00 , G11C11/24
CPC分类号： G11C11/4078 , G11C7/24
摘要： A dynamic random access memory (DRAM) device, including a DRAM core having memory cells for storing data information, and a read protection unit, prevents data stored in the memory cells before power-off, from being read out at power-on.
摘要翻译：包括具有用于存储数据信息的存储单元的DRAM内核的动态随机存取存储器（DRAM）装置以及读取保护单元，防止在断电时存储在存储单元中的数据在通电时被读出。

127. 发明申请

US20070147081A1 Blacklight unit, liquid crystal display device having the same, and method for providing substantially white light for liquid crystal display device 有权
标题翻译：黑光单元，具有该液晶显示装置的液晶显示装置，以及用于为液晶显示装置提供基本白色的光的方法
公开(公告)号：US20070147081A1
公开(公告)日：2007-06-28
申请号：US11475942
申请日：2006-06-28
申请人： Jong-Hyun Choi
发明人： Jong-Hyun Choi
IPC分类号： F21V7/04
CPC分类号： G02F1/133603 , G02F1/133609
摘要： A backlight unit as embodied includes a plurality of unit groups, each unit group having a plurality of light emitting diodes (LEDs); and a light mixing layer formed over the unit groups, for mixing lights emitted from the LEDs to provide substantially white light.
摘要翻译：所实现的背光单元包括多个单元组，每个单元组具有多个发光二极管（LED）; 以及形成在单元组上的光混合层，用于混合从LED发射的光以提供基本上白色的光。

128. 发明申请

US20070133320A1 Circuit and method of boosting voltage for a semiconductor memory device 审中-公开
标题翻译：用于半导体存储器件的升压电压的电路和方法
公开(公告)号：US20070133320A1
公开(公告)日：2007-06-14
申请号：US11634599
申请日：2006-12-06
申请人： Young-Sun Min , Jong-Hyun Choi
发明人： Young-Sun Min , Jong-Hyun Choi
IPC分类号： G11C7/00
CPC分类号： G11C5/145
摘要： A voltage boosting circuit of a semiconductor memory device for decreasing power consumption can include a first precharge circuit, a second precharge circuit, a first capacitive element, a second capacitive element and a coupling circuit. The first precharge circuit precharges a first node using a first supply voltage and the second precharge circuit precharges a second node using a second supply voltage. The first capacitive element boosts a voltage level of the first node in response to a first pulse signal and the second capacitive element boosts a voltage level of the second node in response to a second pulse signal. The coupling circuit electrically couples the first node to the second node in response to a boosting enable signal and a self-refresh control signal.
摘要翻译：用于降低功耗的半导体存储器件的升压电路可以包括第一预充电电路，第二预充电电路，第一电容元件，第二电容元件和耦合电路。第一预充电电路使用第一电源电压对第一节点进行预充电，并且第二预充电电路使用第二电源电压预充电第二节点。第一电容元件响应于第一脉冲信号而升高第一节点的电压电平，并且第二电容元件响应于第二脉冲信号而升高第二节点的电压电平。响应于升压使能信号和自刷新控制信号，耦合电路将第一节点电耦合到第二节点。

129. 发明申请

US20070133318A1 Circuit and method of driving sub-word lines of a semiconductor memory device 失效
标题翻译：驱动半导体存储器件的子字线的电路和方法
公开(公告)号：US20070133318A1
公开(公告)日：2007-06-14
申请号：US11634428
申请日：2006-12-06
申请人： Young-Sun Min , Jong-Hyun Choi
发明人： Young-Sun Min , Jong-Hyun Choi
IPC分类号： G11C5/14
CPC分类号： G11C8/08
摘要： A circuit and method of driving a sub-word line of a semiconductor memory device capable of reducing power consumption is disclosed. The sub-word line driving circuit includes a first transistor, a second transistor and a third transistor. The first transistor pre-charges a boost node to a first voltage in response to a main word line driving signal. The second transistor boosts the boost node to a second voltage in response to a sub-word line driving signal, and provides the sub-word line driving signal to a sub-word line. The third transistor provides the main word line driving signal to the sub-word line in response to a third voltage that has a lower level than a logic “high” state of the sub-word line driving signal.
摘要翻译：公开了一种驱动能够降低功耗的半导体存储器件的子字线的电路和方法。子字线驱动电路包括第一晶体管，第二晶体管和第三晶体管。第一晶体管响应于主字线驱动信号而将升压节点预充电到第一电压。第二晶体管响应于子字线驱动信号将升压节点升压到第二电压，并将子字线驱动信号提供给子字线。第三晶体管响应于具有比子字线驱动信号的逻辑“高”状态低的电平的第三电压，将主字线驱动信号提供给子字线。

130. 发明授权

US07180808B2 Semiconductor memory device for performing refresh operation 有权
标题翻译：用于执行刷新操作的半导体存储器件
公开(公告)号：US07180808B2
公开(公告)日：2007-02-20
申请号：US10954530
申请日：2004-09-29
申请人： Jong-Hyun Choi , Dong-Il Seo , Young-Hun Seo
发明人： Jong-Hyun Choi , Dong-Il Seo , Young-Hun Seo
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/40618 , G11C11/406 , G11C11/40622
摘要： A memory device according to the present invention includes multiple refresh modes and a refresh controller. A first refresh mode can respectively select one more memory block among a plurality of banks comprising a plurality of blocks and each of all banks. In addition, the first refresh mode may perform a refresh operation with respect to selected memory blocks. The second refresh mode can select a part of the banks and perform a refresh operation of data with a selected bank. The controller may select one of the first and second refresh modes in a refresh operation.
摘要翻译：根据本发明的存储器件包括多个刷新模式和刷新控制器。第一刷新模式可以分别在包括多个块和所有存储体中的每一个的多个存储体中选择一个存储器块。此外，第一刷新模式可以针对所选择的存储块执行刷新操作。第二刷新模式可以选择一个存储体的一部分并执行与所选存储体的数据的刷新操作。控制器可以在刷新操作中选择第一和第二刷新模式之一。

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