专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

121. 发明申请

US20040212962A1 Lateral airflow fan-sink for electronic devices 审中-公开
标题翻译：电子设备横向气流风扇接收器
公开(公告)号：US20040212962A1
公开(公告)日：2004-10-28
申请号：US10609594
申请日：2003-07-01
申请人： Via Technologies, Inc.
发明人： Shih-Chang Ku
IPC分类号： H05K007/20
CPC分类号： H01L23/467 , H01L2924/0002 , H01L2924/00
摘要： A lateral airflow fan-sink for electronic devices is introduced to comprise a heat-fin with inter-fin slots and a plurality of axial fans surrounding the heat-fin. The axial fans are mounted individually at ventilating sides of the heat-fin for generating respective forced flow wiping through the inter-fin slots. Thereby, overall heat-dissipation efficiency of the fan-sink can be improved and operational jeopardy from breakdown of all axial fans can be totally removed.
摘要翻译：引入用于电子设备的侧向气流风扇散热器以包括具有间翅片狭槽的散热片和围绕散热片的多个轴流风扇。轴流式风扇分别安装在散热片的通风侧，用于通过散热片间隙产生相应的强制流动擦拭。因此，可以提高风扇凹槽的整体散热效率，并且可以完全去除所有轴流风扇的击穿的操作危险。

122. 发明申请

US20040172521A1 Apparatus and method for performing a detached load operation in a pipeline microprocessor 有权
标题翻译：在管道微处理器中执行分离的负载操作的装置和方法
公开(公告)号：US20040172521A1
公开(公告)日：2004-09-02
申请号：US10776751
申请日：2004-02-11
申请人： VIA Technologies, Inc.
发明人： Rodney E. Hooker , Daniel W.J. Johnson , Albert J. Loper
IPC分类号： G06F009/00
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3861
摘要： A pipeline microprocessor that distributes the instruction dispatching function between a main instruction dispatcher and dispatching logic within a plurality of execution units is disclosed. If the main instruction dispatcher requests load data from a data cache that indicates the data is unavailable, the instruction dispatcher provides to the appropriate execution unit the load instruction (without the load data), a tag (also known by the cache) uniquely identifying the unavailable data, and a false data valid indicator. The cache subsequently obtains the data and outputs it on a bus along with the tag. The dispatching logic in the execution unit is monitoring the bus looking for a valid tag that matches tags of entries in its queue with invalid data indicators. Upon a match, the dispatching logic obtains the data from the bus and subsequently dispatches the instruction along with the data to a functional unit for execution.
摘要翻译：公开了一种在主指令分派器和多个执行单元内的调度逻辑之间分配指令调度功能的流水线微处理器。如果主指令分派器请求从指示数据不可用的数据高速缓存中加载数据，则指令分派器向适当的执行单元提供加载指令（无加载数据），唯一标识不可用数据，以及虚假数据有效指标。缓存随后获得数据并将其与标签一起在总线上输出。执行单元中的调度逻辑正在监视总线，寻找与无效数据指示符匹配其队列中条目的标签的有效标签。在匹配时，调度逻辑从总线获得数据，随后将指令与数据一起发送到功能单元以供执行。

123. 发明申请

US20040164408A1 Noise eliminating system on chip and method of making same 审中-公开
公开(公告)号：US20040164408A1
公开(公告)日：2004-08-26
申请号：US10785094
申请日：2004-02-25
申请人： VIA TECHNOLOGIES INC.
发明人： Chih An Yang
IPC分类号： H01L029/00 , H01L023/48
CPC分类号： H01L23/552 , H01L23/3128 , H01L24/48 , H01L24/73 , H01L25/16 , H01L2224/05599 , H01L2224/32225 , H01L2224/45099 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19104 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A noise eliminating system on chip and method of fabricating the same are provided. A noise eliminating system is connected to a chip. There are guiding units provided on the chip for connecting with the noise eliminating system, thereby reducing simultaneous switching noise of the chip.

124. 发明申请

US20040105955A1 Lamination process and structure of high layout density substrate 有权
标题翻译：层压工艺和结构高的布局密度基板
公开(公告)号：US20040105955A1
公开(公告)日：2004-06-03
申请号：US10717116
申请日：2003-11-19
申请人： VIA TECHNOLOGIES, INC.
发明人： Kwun Yao Ho , Moriss Kung
IPC分类号： B32B003/06
CPC分类号： H05K3/4617 , H01L2224/16225 , H01L2224/48091 , H01L2224/48228 , H01L2224/48464 , H01L2924/3011 , H05K3/062 , H05K3/064 , H05K3/423 , H05K3/4602 , H05K3/4647 , H05K2201/0355 , H05K2201/0361 , H05K2201/09881 , H05K2203/0384 , H05K2203/0733 , Y10S428/901 , Y10T428/24025 , Y10T428/24917 , H01L2924/00014 , H01L2924/00
摘要： A lamination process and structure of a high layout density substrate is disclosed. The lamination process comprises the following steps. First of all, a plurality of laminating layers are individually formed, wherein each laminating layer has a first dielectric layer, a plurality of first vias and a patterned conducting layer. Next, a bottom layer having a second dielectric layer and a plurality of second vias is formed. Then, the laminating layers and the bottom layer are stacked. Finally, the laminating layers and the bottom layer are laminated simultaneously to form a multiplayer substrate at one time.
摘要翻译：公开了一种高布局密度衬底的叠层工艺和结构。层压方法包括以下步骤。首先，分别形成多个层压层，其中每个层压层具有第一介电层，多个第一通孔和图案化的导电层。接下来，形成具有第二电介质层和多个第二通孔的底层。然后层叠层叠体和底层。最后，层压层和底层同时层压以形成多层底板。

125. 发明申请

US20040037425A1 Method for realizing virtual multi-channel output by spectrum analysis 有权
标题翻译：通过频谱分析实现虚拟多通道输出的方法
公开(公告)号：US20040037425A1
公开(公告)日：2004-02-26
申请号：US10639434
申请日：2003-08-13
申请人： VIA Technologies, Inc.
发明人： Ta-Jung Yeh , Wen-Lung Tseng , Ching-Jung Chu
IPC分类号： H04R005/00
CPC分类号： H04S5/005
摘要： A method for realizing virtual multi-channel by spectrum analysis is disclosed. The low-frequency-effect sound data is obtained by averaging sound data of left and right channels in the two-channel sound source and filtering the average by a first low pass filter. The central channel sound data is obtained by averaging sound data of the left and the right channels in the two-channel sound source and filtering the average by a second low pass filter. The surround right and left sound data is obtained by copying sound data of the left and the right channels in the two-channel sound source, respectively.
摘要翻译：公开了一种通过频谱分析实现虚拟多通道的方法。通过对双声道声源的左右声道的声音数据进行平均，并通过第一低通滤波器对平均值进行滤波，得到低频效果声音数据。通过对双声道声源中的左右声道的声音数据进行平均，并通过第二低通滤波器对平均值进行滤波，得到中央声道声音数据。通过在双声道声源中分别复制左右声道的声音数据来获得环绕左右声音数据。

126. 发明申请

US20030221050A1 Method and system for reading data from a memory 有权
标题翻译：从存储器读取数据的方法和系统
公开(公告)号：US20030221050A1
公开(公告)日：2003-11-27
申请号：US10404425
申请日：2003-04-02
申请人： Via Technologies, Inc.
发明人： Chen-Kuan Eric Hong , Yi-Jung Su
IPC分类号： G06F012/00
CPC分类号： G06F13/1684 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C2207/105 , G11C2207/108
摘要： Methods and systems consistent with this invention comprise a control circuit for reading data from a memory comprising a plurality of data channels. Such control circuits comprise at least one multiplexer, wherein the at least one multiplexer is configured to route a data strobe signal to a first number of the plurality of data channels for reading the data from the memory when the at least one multiplexer is in a first selected state, and wherein the at least one multiplexer is configured to route the data strobe signal to a second number of the plurality of data channels, wherein the second number is greater than the first number, for reading the data from the memory when the at least one multiplexer is in a second selected state. Such methods and systems may also comprise a clock for generating a data strobe signal, and a flip-flop for latching the data from the memory into the control circuit with the data strobe signal, wherein the data strobe signal does not leave the control circuit.
摘要翻译：与本发明一致的方法和系统包括用于从包括多个数据通道的存储器读取数据的控制电路。这样的控制电路包括至少一个多路复用器，其中至少一个多路复用器配置成将数据选通信号路由到多个数据通道的第一数目，以便当至少一个多路复用器处于第一并且其中所述至少一个多路复用器被配置为将所述数据选通信号路由到所述多个数据信道的第二数目，其中所述第二数目大于所述第一数量，用于当所述第二数目在所述第一数量时从所述存储器读取数据，至少一个多路复用器处于第二选择状态。这样的方法和系统还可以包括用于产生数据选通信号的时钟，以及用于使用数据选通信号将来自存储器的数据锁存到控制电路中的触发器，其中数据选通信号不离开控制电路。

127. 发明申请

US20030218944A1 Method for controlling optical pickup head upon switching from following mode to seeking mode 有权
标题翻译：用于在从后续模式切换到寻找模式时控制光学拾取头的方法
公开(公告)号：US20030218944A1
公开(公告)日：2003-11-27
申请号：US10411788
申请日：2003-04-11
申请人： Via Technologies, Inc.
发明人： Keng-Lon Lei , Ronnie Lai
IPC分类号： G11B007/085
CPC分类号： G11B7/08529 , G11B7/0941 , G11B7/0945
摘要： A method for controlling an optical pickup head of an optical processing apparatus is provided. A first lead-lag compensator is disabled and a second lead-lag compensator is enabled when the optical pickup head switches from a following mode to a seeking mode. Then, an initial operating factor of the second lead-lag compensator is determined according to a last input value and a last output value of the first lead-lag compensator. An initial kick force of the actuator in the seeking mode is calculated by realizing the last input value and the last output value of the first lead-lag compensator immediately before the first lead-lag compensator is disabled. Finally, the optical pickup head is actuated to perform a seeking operation with the initial kick force.
摘要翻译：提供了一种用于控制光学处理装置的光学拾取头的方法。第一引导滞后补偿器被禁止，并且当光学拾取头从后续模式切换到寻找模式时，启用第二引导滞后补偿器。然后，根据第一引导滞后补偿器的最后输入值和最后输出值来确定第二引导滞后补偿器的初始操作系数。通过在第一超前滞后补偿器被禁用之前实现最后的输入值和第一超前滞后补偿器的最后一个输出值来计算寻求模式下的致动器的初始踢力。最后，光学拾取头被致动以用初始踢力执行寻找操作。

128. 发明申请

US20030193424A1 Serial-to-parallel data converter and method of conversion 有权
标题翻译：串行到并行数据转换器和转换方法
公开(公告)号：US20030193424A1
公开(公告)日：2003-10-16
申请号：US10287662
申请日：2002-11-05
申请人： Via Technologies, Inc.
发明人： Chin-Yi Chiang
IPC分类号： H03M009/00
CPC分类号： H03M9/00
摘要： The present invention improves the drawback of requiring more clock signals in conventional high-frequency serial-to-parallel conversions that often use multi-phase clock circuits. The needed number of phase clocks is the bit width of the parallel data. In addition to effectively reduce the number of required clocks, the present invention can further solve the setup time problem associated with the switching one of two parallel data receivers as the parallel data output. A pre-register is employed in the converter of the present invention. Since this pre-register does not need switch control, it does not have the setup time problem during parallel data switching.
摘要翻译：本发明改进了在常规使用多相时钟电路的常规高频串并转换中需要更多时钟信号的缺点。所需的相位时钟数是并行数据的位宽。除了有效地减少所需时钟的数量之外，本发明还可以解决与并行数据输出两个并行数据接收机之一切换相关联的建立时间问题。在本发明的转换器中采用预寄存器。由于该预寄存器不需要开关控制，因此在并行数据切换期间不具有设置时间问题。

129. 发明申请

US20030174245A1 Clock signal synthesizer with multiple frequency outputs and method for synthesizing clock signal 有权
标题翻译：具有多个频率输出的时钟信号合成器和用于合成时钟信号的方法
公开(公告)号：US20030174245A1
公开(公告)日：2003-09-18
申请号：US10231847
申请日：2002-08-30
申请人： VIA TECHNOLOGIES, INC.
发明人： Chuan-Chen Lee , Chia-Liang Tai , Yi-Chieh Huang
IPC分类号： H04N011/20
CPC分类号： H04N7/012 , H04N5/06 , H04N9/641
摘要： A method for synthesizing a clock signal with multiple frequency outputs for use in a converter for converting a non-interlacing scan data into an interlacing scan data is disclosed. The converter provides a first reference clock signal with a frequency F1. The method includes the steps of receiving the first reference clock signal with the frequency F1 to generate and output a clock signal with a frequency F1nullN, proceeding a divided-by-P1 and a divided-by-P2 operations on the clock signal with a frequency F1nullN, respectively, to output a first output clock signal with a frequency F1nullN/P1 and a second output clock signal with a frequency F1nullN/P2, respectively. The value P2/P1 correlates to a ratio of the pixel number of a horizontal scan line in the non-interlacing scan data to that in the interlacing scan data. In addition, a clock signal synthesizer with multiple frequency outputs is also disclosed.
摘要翻译：公开了一种用于将用于将非隔行扫描数据转换为隔行扫描数据的转换器中用于多个频率输出的时钟信号的方法。转换器提供频率为F1的第一个参考时钟信号。该方法包括以频率F1接收第一参考时钟信号以产生和输出具有频率F1xN的时钟信号的步骤，以频率进行P1分频和P2分频操作 F1xN，以分别输出频率为F1xN / P1的第一输出时钟信号和频率为F1xN / P2的第二输出时钟信号。值P2 / P1与非隔行扫描数据中的水平扫描线的像素数与隔行扫描数据中的水平扫描线的像素数的比率相关。此外，还公开了具有多个频率输出的时钟信号合成器。

130. 发明申请

US20030147359A1 Long-distance network transmission structure and associated device 审中-公开
标题翻译：长距离网络传输结构及相关设备
公开(公告)号：US20030147359A1
公开(公告)日：2003-08-07
申请号：US10338733
申请日：2003-01-09
申请人： VIA TECHNOLOGIES, INC.
发明人： Murphy Chen
IPC分类号： H04B003/36
CPC分类号： H04B3/36
摘要： This invention discloses a long-distance network transmission structure and associated device thereof. The invention utilizes the CAT-5 transmission line network to achieve a high-speed long-distance network tranceiving. A DSP PHY (Digital Signal Processing Physical) is employed in the long-distance network transmission structure to receive a data signal from the transmission line. The signal is then driven to clients with a common PHY without DSP capability or a DSP PHY. Through such a DSP PHY, the signal can be transmitted over 3000 ft and the transmission rate can reach duplex 100 Mbps. Two pairs of cords inside the CAT-5 network transmission line are used to provide the full duplex data tranceiving and the other two spare cords provide electrical power for a repeater. Therefore, the long-distance transmission structure and associated device thereof can effectively reduce the cost for both network service providers and clients and facilitate the installation.
摘要翻译：本发明公开了一种长距离网络传输结构及其相关装置。本发明利用CAT-5传输线网络实现高速长途网络的恍惚。在长距离网络传输结构中采用DSP PHY（数字信号处理物理）来从传输线接收数据信号。然后，该信号被驱动到具有不具有DSP能力的公共PHY的客户端或DSP PHY。通过这样的DSP PHY，信号可以在3000英尺以上传输，传输速率可以达到双工100 Mbps。 CAT-5网络传输线内的两条电线用于提供全双工数据保护，另外两条备用电缆为中继器提供电源。因此，长距离传输结构及其相关设备可以有效降低网络服务提供商和客户端的成本，便于安装。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式