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121. 发明申请

US20140054711A1 System and Method for a Vertical Tunneling Field-Effect Transistor Cell 有权
标题翻译：垂直隧道场效应晶体管单元的系统和方法
公开(公告)号：US20140054711A1
公开(公告)日：2014-02-27
申请号：US13594289
申请日：2012-08-24
申请人： Harry Hak-Lay Chuang , Ming Zhu
发明人： Harry Hak-Lay Chuang , Ming Zhu
IPC分类号： H01L27/088 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7391 , H01L21/823418 , H01L21/823885 , H01L27/092 , H01L29/0657 , H01L29/42356 , H01L29/4238 , H01L29/7889
摘要： A semiconductor device cell is disclosed. The semiconductor device cell includes a transistor gate having a gating surface and a contacting surface and a source region contacted by a source contact. The semiconductor device cell further includes a drain region contacted by a drain contact, wherein the drain contact is not situated opposite the source contact with respect to the gating surface of the transistor gate. Additional semiconductor device cells in which the gate contact is closer to the source contact than to the drain contact are disclosed.
摘要翻译：公开了一种半导体器件单元。半导体器件单元包括晶体管栅极，其具有门控表面和接触表面以及与源极接触的源极区域。半导体器件单元还包括与漏极接触接触的漏极区，其中漏极接触件不相对于晶体管栅极的选通表面与源极接触相对。公开了其中栅极接触比漏极接触更靠近源极接触的其它半导体器件单元。

122. 发明申请

US20140042524A1 Device with a Vertical Gate Structure 有权
标题翻译：具有垂直门结构的装置
公开(公告)号：US20140042524A1
公开(公告)日：2014-02-13
申请号：US13568997
申请日：2012-08-07
申请人： Hak-Lay Chuang , Ming Zhu , Yi-Ren Chen
发明人： Hak-Lay Chuang , Ming Zhu , Yi-Ren Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L21/28114 , H01L21/76885 , H01L21/823821 , H01L21/823828 , H01L21/823885 , H01L29/42376
摘要： A device includes a wafer substrate, a conical frustum structure formed in the wafer substrate, and a gate all-around (GAA) structure circumscribing the middle portion of the conical frustum structure. The conical frustum structure includes a drain formed at a bottom portion of the conical frustum, a source formed at a top portion of the vertical conical frustum, and a channel formed at a middle portion of the conical frustum connecting the source and the drain. The GAA structure overlaps with the source at one side of the GAA structure, crosses over the channel, and overlaps with the drain at another side of the GAA structure.
摘要翻译：一种器件包括晶片衬底，形成在晶片衬底中的锥形截头锥体结构，以及围绕锥形截头锥体结构的中间部分的栅极全能（GAA）结构。锥形截头锥体结构包括形成在锥形截头锥体的底部处的排水口，形成在垂直锥形截头锥体的顶部处的源和形成在连接源极和漏极的锥形截头锥体的中间部分处的通道。 GAA结构与GAA结构一侧的源重叠，与沟道交叉，并与GAA结构另一侧的漏极重叠。

123. 发明授权

US08634203B2 Latch assembly for connecting two boards 有权
标题翻译：用于连接两个板的闩锁组件
公开(公告)号：US08634203B2
公开(公告)日：2014-01-21
申请号：US13283566
申请日：2011-10-27
申请人： Chi-An Yu , Yan-Hao Li , Xing Xia , Xiao-Ming Zhu
发明人： Chi-An Yu , Yan-Hao Li , Xing Xia , Xiao-Ming Zhu
IPC分类号： H05K1/14
CPC分类号： F16B5/0016
摘要： A latch assembly for securing two boards together includes a male section and a female section. The male section includes a base to be fixed to one board, a tab protruding from a first side surface of the base. The tab includes at least one latching portion protruding therefrom. The female section includes a support block fixed to the other one board and defining a chamber, a movable block slidably retained within the chamber of the support block, and the at least one elastic member is retained within the chamber. The movable block includes a stop portion capable of latching with the at least one latching portion when the movable block is retained in a securing position by the tab. The at least one elastic member applies a push force to the movable block to movably retain the movable block in the normal position.
摘要翻译：用于将两个板固定在一起的闩锁组件包括一个凸形部分和一个凹形部分。阳部包括固定到一个板的基部，从基部的第一侧表面突出的突出部。突片包括从其突出的至少一个闩锁部分。阴部分包括固定到另一个板并限定腔室的支撑块，可滑动地保持在支撑块的腔室内的可动块，并且至少一个弹性构件保持在腔室内。可移动块包括当可移动块通过突片保持在固定位置时能够与至少一个闩锁部分锁定的止挡部分。所述至少一个弹性构件向所述可移动块施加推力以将所述可移动块可移动地保持在正常位置。

124. 发明申请

US20130264652A1 Cost-Effective Gate Replacement Process 有权
公开(公告)号：US20130264652A1
公开(公告)日：2013-10-10
申请号：US13440848
申请日：2012-04-05
申请人： Ming Zhu , Jyun-Ming Lin , Wei Cheng Wu , Bao-Ru Young , Hak-Lay Chuang
发明人： Ming Zhu , Jyun-Ming Lin , Wei Cheng Wu , Bao-Ru Young , Hak-Lay Chuang
IPC分类号： H01L21/28 , H01L21/283 , H01L27/092
CPC分类号： H01L29/4941 , H01L21/28088 , H01L21/283 , H01L21/28518 , H01L21/76814 , H01L21/76843 , H01L21/76855 , H01L21/823443 , H01L21/82345 , H01L21/823842 , H01L21/82385 , H01L27/092 , H01L27/0922 , H01L29/401 , H01L29/4236 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device.

125. 发明申请

US20130260547A1 METHOD OF FABRICATING A METAL GATE SEMICONDUCTOR DEVICE 有权
标题翻译：制造金属栅极半导体器件的方法
公开(公告)号：US20130260547A1
公开(公告)日：2013-10-03
申请号：US13434344
申请日：2012-03-29
申请人： Sheng-Chen Chung , Ming Zhu , Jyun-Ming Lin , Bao-Ru Young , Hak-Lay Chuang
发明人： Sheng-Chen Chung , Ming Zhu , Jyun-Ming Lin , Bao-Ru Young , Hak-Lay Chuang
IPC分类号： H01L21/336
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/28202 , H01L21/82385 , H01L21/823857 , H01L29/4966 , H01L29/517
摘要： A method of semiconductor device fabrication including providing a substrate having a gate dielectric layer such as a high-k dielectric disposed thereon. A tri-layer element is formed on the gate dielectric layer. The tri-layer element includes a first capping layer, a second capping layer, and a metal gate layer interposing the first and second capping layer. One of an nFET and a pFET gate structure are formed using the tri-layer element, for example, the second capping layer and the metal gate layer may form a work function layer for one of an nFET and a pFET device. The first capping layer may be a sacrificial layer used to pattern the metal gate layer.
摘要翻译：一种半导体器件制造方法，包括提供具有栅极电介质层的衬底，例如设置在其上的高k电介质。在栅介质层上形成三层元件。三层元件包括第一覆盖层，第二覆盖层和插入第一和第二覆盖层的金属栅极层。使用三层元件形成nFET和pFET栅极结构之一，例如，第二覆盖层和金属栅极层可以形成nFET和pFET器件中的一个的功函数层。第一覆盖层可以是用于图案化金属栅极层的牺牲层。

126. 发明申请

US20130241641A1 SIGNAL AMPLIFIER CIRCUIT FOR USB PORT 审中-公开
标题翻译：用于USB端口的信号放大器电路
公开(公告)号：US20130241641A1
公开(公告)日：2013-09-19
申请号：US13678679
申请日：2012-11-16
申请人： ZHI-MING ZHU , TING WANG
发明人： ZHI-MING ZHU , TING WANG
IPC分类号： H03F3/45 , H03F3/68
CPC分类号： H03F3/45 , G06F13/4072 , G06F2213/0042 , H03F3/68
摘要： A signal amplifier circuit for USB port includes a USB controller, an amplifier circuit and a USB port. The USB controller includes a super speed transmitter differential pair and a super speed receiver differential pair. The amplifier circuit includes two first input terminals, two second input terminals, two first output terminals, and two second output terminals. The USB port includes two first differential signal receiving terminals and two first differential signal transmitting terminals. The super speed transmitter differential pair and the super speed receiver differential pair are electrically connected to the first input terminals and the second output terminals. The first output terminals and the second input terminals are electrically connected to the first differential signal receiving terminals and the first differential signal transmitting terminals. The amplifier circuit amplifies differential signals transmitted between the USB controller and the USB port.
摘要翻译：用于USB端口的信号放大器电路包括USB控制器，放大器电路和USB端口。 USB控制器包括超速发射机差分对和超速接收器差分对。放大器电路包括两个第一输入端子，两个第二输入端子，两个第一输出端子和两个第二输出端子。 USB端口包括两个第一差分信号接收端和两个第一差分信号发送端。超速发送器差分对和超速接收器差分对电连接到第一输入端子和第二输出端子。第一输出端子和第二输入端子电连接到第一差分信号接收端子和第一差分信号发送端子。放大器电路放大USB控制器和USB端口之间传输的差分信号。

127. 发明授权

US08378428B2 Metal gate structure of a semiconductor device 有权
标题翻译：半导体器件的金属栅极结构
公开(公告)号：US08378428B2
公开(公告)日：2013-02-19
申请号：US12893338
申请日：2010-09-29
申请人： Han-Guan Chew , Lee-Wee Teo , Ming Zhu , Bao-Ru Young , Harry-Hak-Lay Chuang
发明人： Han-Guan Chew , Lee-Wee Teo , Ming Zhu , Bao-Ru Young , Harry-Hak-Lay Chuang
IPC分类号： H01L21/02
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28088 , H01L21/82385 , H01L29/66545
摘要： The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ⅔ of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ⅓ of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region.
摘要翻译：应用公开了一种半导体器件，其包括具有第一有源区，第二有源区和具有介于第一和第二有源区之间的第一宽度的隔离区的衬底; 在所述第一有源区上方的P金属栅电极，并且延伸至所述隔离区的第一宽度的至少;; 以及在第二有源区上方的N极金属栅电极，并延伸超过第一宽度的1/3。 N型金属栅电极在隔离区域上电连接到P金属栅电极。

128. 发明申请

US20130032884A1 INTEGRATED CIRCUIT DEVICE HAVING DEFINED GATE SPACING AND METHOD OF DESIGNING AND FABRICATING THEREOF 有权
标题翻译：具有定义的间隙的集成电路装置及其设计和制造方法
公开(公告)号：US20130032884A1
公开(公告)日：2013-02-07
申请号：US13195628
申请日：2011-08-01
申请人： Hak-Lay Chuang , Ming Zhu , Po-Nien Chen , Bao-Ru Young
发明人： Hak-Lay Chuang , Ming Zhu , Po-Nien Chen , Bao-Ru Young
IPC分类号： H01L27/088 , G06F17/50 , H01L21/336
CPC分类号： H01L29/42376 , G06F17/5068 , G06F17/5072 , G06F17/5081 , H01L21/823437 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/785 , H01L2223/58
摘要： A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (√{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 μm2).
摘要翻译：一种器件，以及制造和/或设计这种器件的方法，包括具有宽度（W）和长度（L）的第一栅极结构以及与第一栅极结构分离大于的距离的第二栅极结构： √{平方根（W * W + L * L）}）/ 10。第二栅极结构是与第一栅极结构相邻的下一个栅极结构。还描述了一种用于设计集成电路的方法和装置，包括实现限定栅极结构分离的设计规则。在实施例中，对于相对于衬底上的其它栅极结构（例如，大于3μm2）较大的栅极结构，实现分离距离。

129. 发明申请

US20130020651A1 METAL GATE STRUCTURE OF A CMOS SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译： CMOS半导体器件的金属栅结构及其形成方法
公开(公告)号：US20130020651A1
公开(公告)日：2013-01-24
申请号：US13189232
申请日：2011-07-22
申请人： Ming ZHU , Bao-Ru YOUNG , Harry Hak-Lay CHUANG
发明人： Ming ZHU , Bao-Ru YOUNG , Harry Hak-Lay CHUANG
IPC分类号： H01L27/092 , H01L21/283
CPC分类号： H01L21/823814 , H01L21/3212 , H01L21/82385 , H01L21/823864 , H01L21/823878 , H01L27/0922 , H01L27/0928 , H01L29/0642
摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate, an N-metal gate electrode, and a P-metal gate electrode. The substrate comprises an isolation region surrounding a P-active region and an N-active region. The N-metal gate electrode comprises a first metal composition over the N-active region. The P-metal gate electrode comprises a bulk portion over the P-active region and an endcap portion over the isolation region. The endcap portion comprises the first metal composition and the bulk portion comprises a second metal composition different from the first metal composition.
摘要翻译：本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括衬底，N金属栅电极和P金属栅电极。衬底包括围绕P活性区域和N-活性区域的隔离区域。所述N-金属栅电极包括在所述N-活性区上的第一金属组合物。 P型金属栅电极包括位于P有源区上的本体部分和在隔离区上方的端盖部分。端盖部分包括第一金属组合物，并且本体部分包含不同于第一金属组合物的第二金属组合物。

130. 发明申请

US20130008616A1 CORDLESS WINDOW CURTAIN 审中-公开
标题翻译：无窗窗帘
公开(公告)号：US20130008616A1
公开(公告)日：2013-01-10
申请号：US13176938
申请日：2011-07-06
申请人： Chien-Chih Huang , Ming-Zhu Chiang
发明人： Chien-Chih Huang , Ming-Zhu Chiang
IPC分类号： A47H23/04 , A47H5/032
CPC分类号： E06B9/32 , E06B9/327 , E06B2009/3222
摘要： A cordless window curtain has a window curtain rod, a curtain body, lateral rails, a locating rope assembly and an elastic tension component. The reducing guide slots are set at one side of the lateral rails facing the curtain body and connected with the hollow slot. The width of the reducing guide slot must be smaller than that of the lateral rail and the width of the reducing guide slot is preferably between 2 mm and 5.9 mm. Two flanged guide shafts are protruded from both ends of the hollow bottom rod of the curtain body. These two flanged guide shafts are provided with a through-hole for threading of two lower locating sections of the locating rope assembly. The outer end of two flanged guide shafts is inserted into the reducing guide slot, such that the flanged guide shaft can slide vertically along the path of the reducing guide slot.
摘要翻译：无绳窗帘具有窗帘杆，帘体，侧轨，定位绳组件和弹性张力部件。还原引导槽设置在面向帘体的侧轨的一侧，并与中空槽连接。还原引导槽的宽度必须小于侧轨的宽度，并且减速导槽的宽度优选在2mm至5.9mm之间。两个法兰导向轴从帘体的中空底杆的两端突出。这两个带凸缘的引导轴设置有用于穿过定位绳组件的两个下定位部分的通孔。两个凸缘引导轴的外端插入到减速导槽中，使得带凸缘的引导轴可沿着还原引导槽的路径垂直滑动。

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