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    • 121. 发明申请
    • METHOD FOR FORMING SURFACE STRAP
    • 形成表面带的方法
    • US20080305605A1
    • 2008-12-11
    • US11940308
    • 2007-11-14
    • Chih-Hao ChengTzung-Han LeeChung-Yuan Lee
    • Chih-Hao ChengTzung-Han LeeChung-Yuan Lee
    • H01L21/20
    • H01L27/10867
    • A method for forming a surface strap includes forming a deep trench capacitor having a conductive connection layer on its surface in the substrate and the conductive connection layer in contact with the conductive layer; forming a poly-Si layer covering the pad layer and the conductive connection layer; performing a selective ion implantation with an angle to make part of the poly-Si layer an undoped poly-Si layer; removing the undoped poly-Si layer to expose part of the conductive connection layer; etching the exposed conductive connection layer to form a recess; removing the poly-Si layer to make the exposed conductive connection layer a conductive connection strap; filling the recess with an insulation material to form a shallow trench isolation; exposing the conductive layer; and selectively removing the conductive layer to form a first conductive strap which forms the surface strap together with the conductive connection strap.
    • 一种形成表面带的方法包括:在其基板的表面上形成具有导电连接层的深沟槽电容器和与导电层接触的导电连接层; 形成覆盖所述焊盘层和所述导电连接层的多晶硅层; 以角度进行选择性离子注入,以使多晶硅层的一部分成为未掺杂的多晶硅层; 去除未掺杂的多晶硅层以暴露部分导电连接层; 蚀刻暴露的导电连接层以形成凹部; 去除所述多晶硅层以使所述暴露的导电连接层成为导电连接带; 用绝缘材料填充凹槽以形成浅沟槽隔离; 暴露导电层; 并且选择性地去除导电层以形成与导电连接带一起形成表面带的第一导电带。
    • 122. 发明授权
    • Single-gate non-volatile memory and operation method thereof
    • 单门非易失性存储器及其操作方法
    • US07423903B2
    • 2008-09-09
    • US11403858
    • 2006-04-14
    • Hsin-Chang LinWen-Chien HuangMing-Tsang YangHao-Cheng ChangCheng-Ying Wu
    • Hsin-Chang LinWen-Chien HuangMing-Tsang YangHao-Cheng ChangCheng-Ying Wu
    • G11C14/00
    • H01L27/115
    • A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and a second on-doped region; the first electrically-conductive gate and the second electrically-conductive gate are interconnected to form a single floating gate of a memory cell; a reverse bias is used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of a single-gate non-volatile memory with an isolation well, positive and negative voltages are applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer so that the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.
    • 一种单栅极非易失性存储器及其操作方法,其中晶体管和电容器结构嵌入在半导体衬底中; 所述晶体管包括:第一导电栅极,第一介电层和多个离子掺杂区域; 电容器结构包括:第二导电栅极,第二介电层和第二掺杂区域; 第一导电栅极和第二导电栅极互连以形成存储单元的单个浮置栅极; 使用反向偏置来实现单浮栅存储单元的读,写和擦除操作; 在具有隔离阱的单栅极非易失性存储器的操作中,正和负电压施加到漏极,栅极和硅衬底/隔离阱以产生反型层,使得绝对电压 升压电路的面积,可以减少电流消耗。
    • 124. 发明申请
    • ADIP demodulation method and apparatus
    • ADIP解调方法和装置
    • US20080013429A1
    • 2008-01-17
    • US11902310
    • 2007-09-20
    • Hao-Cheng ChenWen-Yi Wu
    • Hao-Cheng ChenWen-Yi Wu
    • G11B7/00
    • G11B7/0053
    • An ADIP demodulation method and apparatus, which are used in an optical disk driver to generate the ADIP information according to a wobble signal. The apparatus includes a slicing unit for receiving the wobble signal and generating a wobble pulse, a phase locked loop for generating a reference wobble signal with the same frequency and phase as the wobble pulse and a reference clock with frequency higher than the wobble pulse, a channel bit generator for generating a channel bit signal according to the reference wobble signal and the wobble pulse, and a decoder for decoding to ADIP information according to the channel bit signal. The channel bit generator generates a difference signal between the wobble pulse and the reference wobble signal, and outputs the channel bit signal according to the difference signal.
    • 一种ADIP解调方法和装置,用于光盘驱动器中以根据摆动信号产生ADIP信息。 该装置包括用于接收摆动信号并产生摆动脉冲的切片单元,用于产生具有与摆动脉冲相同的频率和相位的参考摆动信号和频率高于摆动脉冲的参考时钟的锁相环, 信道位发生器,用于根据参考摆动信号和摆动脉冲产生信道位信号;以及解码器,用于根据信道位信号对ADIP信息进行解码。 通道位发生器产生摆动脉冲与参考摆动信号之间的差分信号,并根据差分信号输出通道位信号。
    • 130. 发明申请
    • Programmable logic analyzer data analyzing method
    • 可编程逻辑分析仪数据分析方法
    • US20060075212A1
    • 2006-04-06
    • US10541190
    • 2002-12-31
    • Chiu-Hao ChengMing-Gwo ChengChun-Feng Tzu
    • Chiu-Hao ChengMing-Gwo ChengChun-Feng Tzu
    • G06F9/44
    • G01R31/3177
    • A programmable logic analyzer data analyzing method includes the step of controlling a control circuit to fetch waveform data from the test sample and to store fetched waveform data in a memory, the step of controlling the control circuit to transmit the waveform data from the memory to a computer through a transmission interface when the memory space of the memory used up (fully occupied), the step of driving the computer to write the received waveform data in a buffer thereof, and the step of running a test sample test signal auxiliary analyzing procedure for enabling the user to use the displayed on the display screen of the computer for making debugging data analysis, comparison data analysis and search data analysis, to store the analyzed data in the form of a file, or to print out the analyzed data through a printer.
    • 一种可编程逻辑分析仪数据分析方法,包括以下步骤:控制电路从所述测试样本取出波形数据并将获取的波形数据存储在存储器中;控制所述控制电路以将所述波形数据从所述存储器发送到 计算机通过传输接口,当存储器的存储空间用尽(完全占用)时,驱动计算机将接收到的波形数据写入其缓冲器的步骤,以及运行测试样本测试信号辅助分析程序的步骤 使用户能够使用显示在计算机的显示屏上进行调试数据分析,比较数据分析和搜索数据分析,以文件的形式存储所分析的数据,或通过打印机打印分析的数据 。