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111. 发明授权

US07948872B2 Backplane interface adapter with error control and redundant fabric 有权
公开(公告)号：US07948872B2
公开(公告)日：2011-05-24
申请号：US12400645
申请日：2009-03-09
申请人： Ronak Patel , Ming G. Wong , Yu-Mei Lin , Andrew Chang , Yuen Fai Wong
发明人： Ronak Patel , Ming G. Wong , Yu-Mei Lin , Andrew Chang , Yuen Fai Wong
IPC分类号： G06F11/00
CPC分类号： H04L45/74 , H04L47/50 , H04L47/6225 , H04L49/153 , H04L49/1538 , H04L49/25 , H04L49/30 , H04L49/3063 , H04L49/352 , H04L49/90 , H04L49/901
摘要： A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.

112. 发明授权

US07715419B2 Pipelined packet switching and queuing architecture 有权
标题翻译：流水线分组交换和排队架构
公开(公告)号：US07715419B2
公开(公告)日：2010-05-11
申请号：US11368776
申请日：2006-03-06
申请人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
发明人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
IPC分类号： H04L12/56 , H04J1/16
CPC分类号： H04L49/1546 , H04L49/201 , H04L49/3045 , H04L49/3063 , H04L49/3072 , H04L49/503 , H04L49/506
摘要： An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports of a network interface. A high priority buffer and a low priority buffer can be assigned to each port of the network interface. The network interface can perform packet prioritization through buffer selection based on priority. High priority packets will be transmitted to an ingress packet processor before low priority packets for a given port.
摘要翻译：提供了一种网络路由设备中线路卡的架构。线路卡架构在路由设备和网络之间提供双向接口，两者接收来自网络的分组，并通过网络接口的一个或多个连接端口将分组发送到网络。可以将高优先级缓冲区和低优先级缓冲区分配给网络接口的每个端口。网络接口可以通过基于优先级的缓冲区选择来执行分组优先级。高优先级数据包将在给定端口的低优先级数据包之前传输到入口数据包处理器。

113. 发明授权

US07684431B1 System and method for arbitration in a packet switch 有权
标题翻译：分组交换机仲裁的系统和方法
公开(公告)号：US07684431B1
公开(公告)日：2010-03-23
申请号：US11407321
申请日：2006-04-18
申请人： David Gibson
发明人： David Gibson
IPC分类号： H04L12/56
CPC分类号： H04L49/30 , H04L45/52 , H04L47/70 , H04L49/10 , H04L49/109 , H04L49/1546 , H04L49/251 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/3063 , H04L49/35
摘要： A packet switch arbitration system and method for arbitration in a packet switch. In one aspect, a method of issuing grants to an ingress port is disclosed in which a first grant request and burst signal are activated at an ingress port having more than one word available for transfer through the switch. A first grant is issued to the ingress port on a first interval. A subsequent grant is issued to the ingress port on a subsequent interval, where the subsequent grant is issued before the ingress port has validated the first grant request.
摘要翻译：分组交换仲裁系统和方法，用于在分组交换机中进行仲裁。一方面，公开了向入口端口发放授权的方法，其中在具有多于一个可用于通过交换机传送的字的入口端口处激活第一准许请求和突发信号。在第一个时间间隔内向入口端口发出第一个授权。在接下来的间隔内向进入端口发出后续授权，其中在入口端口已经验证了第一授权请求之前发出后续授权。

114. 发明授权

US07680943B2 Methods and apparatus for implementing multiple types of network tunneling in a uniform manner 有权
标题翻译：以统一的方式实现多种类型的网络隧道的方法和装置
公开(公告)号：US07680943B2
公开(公告)日：2010-03-16
申请号：US10691109
申请日：2003-10-20
申请人： Alex Conta , Srihari Varada
发明人： Alex Conta , Srihari Varada
IPC分类号： G06F15/16 , G06F15/173
CPC分类号： H04L49/3063 , H04L47/2491 , H04L69/18
摘要： A uniform method for implementing multiple tunneling protocols in a switch or router is disclosed. The method is based on the realization that although the tunneling protocols are very different, they do share a similar overall structure which can be exploited to create a unified method of dealing with multiple protocols. By using similar data structures to implement multiple protocols, the invention makes data management and programming simple and, therefore, cost effective. According to the invention, all tunneling protocols are abstracted as the mapping of input L2 or L3 streams with output L2 or L3 streams. Mapping is provided by a finite set of tunnel interfaces. The tunnel interfaces map the input streams to output interfaces. As traffic streams flow through these interfaces, they are processed according to defined attributes of these interfaces.
摘要翻译：公开了一种在交换机或路由器中实现多个隧道协议的统一方法。该方法基于这样的认识：虽然隧道协议是非常不同的，但是它们共享一个类似的整体结构，可以利用这种结构来创建一个处理多种协议的统一方法。通过使用类似的数据结构来实现多个协议，本发明使得数据管理和编程变得简单，因而成本有效。根据本发明，所有隧道协议被抽象为输入L2或L3流与输出L2或L3流的映射。映射由一组有限的隧道接口提供。隧道接口将输入流映射到输出接口。随着流量流经这些接口，它们根据这些接口的定义属性进行处理。

115. 发明申请

US20100061393A1 System and Method for High Speed Packet Transmission 有权
公开(公告)号：US20100061393A1
公开(公告)日：2010-03-11
申请号：US12608972
申请日：2009-10-29
申请人： Yuen Fai Wong
发明人： Yuen Fai Wong
IPC分类号： H04L12/56
CPC分类号： H04L49/352 , H04L5/14 , H04L12/4645 , H04L45/745 , H04L45/7453 , H04L49/30 , H04L49/3063 , H04Q11/0428
摘要： The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane.

116. 发明申请

US20100034215A1 Backplane Interface Adapter with Error Control 审中-公开
标题翻译：具有错误控制的背板接口适配器
公开(公告)号：US20100034215A1
公开(公告)日：2010-02-11
申请号：US12505390
申请日：2009-07-17
申请人： Ronak Patel , Ming G. Wong , Yu-mei Lin , Andrew Chang , Yuen Fai A. Wong
发明人： Ronak Patel , Ming G. Wong , Yu-mei Lin , Andrew Chang , Yuen Fai A. Wong
IPC分类号： H04L12/66 , H04J3/06
CPC分类号： H04L45/74 , H04L47/50 , H04L47/6225 , H04L49/153 , H04L49/1538 , H04L49/25 , H04L49/30 , H04L49/3063 , H04L49/352 , H04L49/90 , H04L49/901
摘要： A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.
摘要翻译：具有错误控制和冗余结构的背板接口适配器，用于高性能网络交换机。错误控制可以由包括电平监视器，条带同步错误检测器，流量控制器和控制字符存在跟踪器的管理模块来提供。背板接口适配器的冗余结构收发器改善了适配器正确和一致地接收携带数据分组的窄输入单元并向交换结构输出宽条带单元的能力。

117. 发明申请

US20090287952A1 Backplane Interface Adapter with Error Control and Redundant Fabric 有权
公开(公告)号：US20090287952A1
公开(公告)日：2009-11-19
申请号：US12400594
申请日：2009-03-09
申请人： Ronak Patel , Ming G. Wong , Yu-mei Lin , Andrew Z. Chang , Yuen Fai A. Wong
发明人： Ronak Patel , Ming G. Wong , Yu-mei Lin , Andrew Z. Chang , Yuen Fai A. Wong
IPC分类号： G06F11/07 , G06F11/30
CPC分类号： H04L45/74 , H04L47/50 , H04L47/6225 , H04L49/153 , H04L49/1538 , H04L49/25 , H04L49/30 , H04L49/3063 , H04L49/352 , H04L49/90 , H04L49/901
摘要： A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.

118. 发明申请

US20090279561A1 Backplane Interface Adapter 有权
标题翻译：背板接口适配器
公开(公告)号：US20090279561A1
公开(公告)日：2009-11-12
申请号：US12372390
申请日：2009-02-17
申请人： Andrew Chang , Ronak Patel , Ming G. Wong
发明人： Andrew Chang , Ronak Patel , Ming G. Wong
IPC分类号： H04L12/66
CPC分类号： H04L49/25 , H04L47/50 , H04L47/6225 , H04L49/153 , H04L49/1538 , H04L49/30 , H04L49/3063 , H04L49/352 , H04L49/90 , H04L49/901 , Y10S370/907
摘要： A backplane interface adapter for a network switch. The backplane interface adapter includes at least one receiver that receives input cells carrying packets of data; at least one cell generator that generates encoded cells which include the packets of data from the input cells; and at least one transmitter that transmits the generated cells to a switching fabric. The cell includes a destination slot identifier that identifies a slot of the switching fabric towards which the respective input cell is being sent. The generated cells include in-band control information.
摘要翻译：用于网络交换机的背板接口适配器。背板接口适配器包括至少一个接收器，接收携带数据包的输入单元; 至少一个单元发生器，其生成包括来自输入单元的数据分组的编码单元; 以及至少一个将生成的小区发送到交换结构的发射机。小区包括目的地时隙标识符，其标识正在发送相应输入小区的交换结构的时隙。所生成的小区包括带内控制信息。

119. 发明授权

US07602790B2 Two-dimensional pipelined scheduling technique 有权
标题翻译：二维流水线调度技术
公开(公告)号：US07602790B2
公开(公告)日：2009-10-13
申请号：US11842075
申请日：2007-08-20
申请人： Satoshi Kamiya , Hirokazu Ozaki
发明人： Satoshi Kamiya , Hirokazu Ozaki
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L47/50 , H04L47/60 , H04L47/6225 , H04L49/101 , H04L49/1546 , H04L49/254 , H04L49/3045 , H04L49/3063 , H04L49/3072 , H04L49/503 , H04L49/90 , H04L49/9047
摘要： A scheduler allowing high-speed scheduling scalable with the number of input and output ports of a crosspoint switch and suppressed unfairness among inputs is disclosed. The scheduler includes an M×M matrix of scheduling modules, each of which schedules packet forwarding connections from a corresponding input group of input ports to selected ones of a corresponding output group of output ports based on reservation information. A diagonal module pattern is used to determine a set of M scheduling modules to avoid coming into collision with each other. Each determined scheduling module performs reservation of packet forwarding connections based on current reservation information and transfers updated reservation information in row and column directions of the M×M matrix.
摘要翻译：公开了一种允许高速调度随着交叉点开关的输入和输出端口的数量可扩展并且抑制输入之间不公平的调度器。调度器包括调度模块的MxM矩阵，每个调度模块基于预留信息，将分组转发连接从对应的输入端口组输入到对应的输出端口组中的所选择的调度模块。对角模块模式用于确定一组M个调度模块，以避免相互碰撞。每个确定的调度模块基于当前预约信息执行分组转发连接的预约，并且按照MxM矩阵的行和列方向传送更新的预约信息。

120. 发明申请

US20090216829A1 NETWORK EQUIPMENT 审中-公开
标题翻译：网络设备
公开(公告)号：US20090216829A1
公开(公告)日：2009-08-27
申请号：US12388310
申请日：2009-02-18
申请人： Yasunori Terasaki
发明人： Yasunori Terasaki
IPC分类号： G06F15/16
CPC分类号： H04L45/60 , H04L49/10 , H04L49/1546 , H04L49/3063
摘要： A network equipment has a group of first stage computing units that perform first stage processing on a packet, and has a group of second stage computing units that perform second stage processing on a packet after the first stage processing. The network equipment assigns the first stage processing that is to be performed on the packet to a computing unit in the group of first stage computing units; generates control information for determining which computing unit in the group of second stage computing units is to be assigned the second stage processing when the computing unit in the group of first stage computing units performs the first stage processing; and determines which computing unit in the group of second stage computing units is to be assigned the second stage processing on the packet based on the control information.
摘要翻译：网络设备具有对分组执行第一阶段处理的一组第一阶段计算单元，并且具有在第一阶段处理之后对分组执行第二阶段处理的一组第二阶段计算单元。网络设备将要对分组执行的第一阶段处理分配给第一阶段计算单元组中的计算单元; 产生控制信息，用于当第一级计算单元组中的计算单元执行第一级处理时，确定要分配第二级计算单元组中的哪个计算单元被分配第二级处理; 并且基于控制信息确定要对第二级计算单元组中的哪个计算单元分配关于分组的第二级处理。

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