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111. 发明授权

US06954885B2 Method and apparatus for coding bits of data in parallel 失效
标题翻译：并行编码数据位的方法和装置
公开(公告)号：US06954885B2
公开(公告)日：2005-10-11
申请号：US10020532
申请日：2001-12-14
申请人： James Y. Hurt , Michael A. Howard , Robert J. Fuchs
发明人： James Y. Hurt , Michael A. Howard , Robert J. Fuchs
IPC分类号： H03M13/27 , H03M13/00 , H03M13/29 , H04L1/00
CPC分类号： H04L1/005 , H03M13/235 , H03M13/275 , H03M13/2764 , H03M13/2903 , H03M13/2972 , H03M13/6561 , H03M13/6563 , H03M13/6575 , H04L1/0043 , H04L1/0065 , H04L1/0066 , H04L1/0069 , H04L1/0071
摘要： A method and apparatus for encoding multiple bits in parallel wherein outputs are generated recursively. During each clock cycle, the encoder processes multiple bits and generates outputs consistent with those generated sequentially over multiple clock cycles in a conventional convolutional encoder. In one embodiment, input data is stored in multiple memory storage units, which are then each uniquely addressed to provide data to parallel encoders.
摘要翻译：并行地编码多个比特的方法和装置，其中递归生成输出。在每个时钟周期期间，编码器处理多个比特并且产生与常规卷积编码器中的多个时钟周期顺序生成的输出一致的输出。在一个实施例中，输入数据存储在多个存储器存储单元中，然后每个存储单元被唯一地寻址以向并行编码器提供数据。

112. 发明申请

US20050071729A1 Interleaving.deinterleaving device and method for communication system 有权
标题翻译：交错设备和通信系统的方法
公开(公告)号：US20050071729A1
公开(公告)日：2005-03-31
申请号：US10975661
申请日：2004-10-28
申请人： Min-Goo Kim
发明人： Min-Goo Kim
IPC分类号： G06F11/10 , H03M13/27 , H04B7/26 , H04L1/00 , H03M13/00
CPC分类号： H03M13/2789 , H03M13/2703 , H03M13/275 , H03M13/2764
摘要： A device for sequentially storing input bit symbols of a given interleaver size N in a memory at an address from 0 to N-1 and reading the stored bit symbols from the memory. The device comprises a look-up table for providing a first variable m and a second variable J satisfying the equation N=2m×J; and an address generator for generating a read address depending on the first and second variables m and J provided from the look-up table. The read address is determined by 2m(K mod J)+BROm(K/J), where K (0≦K≦(N-1)) denotes a reading sequence, BROm(y) is the bit-reversed m-bit value of y and/is a function in which a quotient of K divided by d is obtained, the quotient being an integer.
摘要翻译：一种用于在0至N-1的地址处将存储器中的给定交织器大小N的输入比特符号顺序存储并从存储器读取存储的比特符号的装置。该装置包括用于提供第一变量m的查找表和满足方程式N = 2·xJ的第二变量J; 以及用于根据从查找表提供的第一和第二变量m和J生成读取地址的地址发生器。读取地址由2 （K mod J）+ BROm（K / J）确定，其中K（0 <= K <=（N-1））表示读取序列，BROm（y）反转的m位的值和/是其中得到K除以d的商的函数，商是整数。

113. 发明授权

US06857087B2 High-performance low-memory interleaver banks for turbo-codes 有权
标题翻译：用于turbo码的高性能低内存交织器组
公开(公告)号：US06857087B2
公开(公告)日：2005-02-15
申请号：US10165122
申请日：2002-06-07
申请人： Stewart N. Crozier , Paul Guinand
发明人： Stewart N. Crozier , Paul Guinand
IPC分类号： H03M13/27 , H03M13/29 , G06F29/00 , H03M13/00
CPC分类号： H03M13/2789 , H03M13/275 , H03M13/276 , H03M13/2771 , H03M13/2957
摘要： An interleaver for interleaving a set of K ordered elements is disclosed herein. The disclosed interleaver can be expressed as a single permutation that corresponds to two local dithering operations and a global permutation operation. The single permutation can be represented as a small collection of short vectors, and can be calculated recursively, allowing the interleaver to be both stored and implemented using a smaller amount of memory than conventionally possible.
摘要翻译：本文公开了用于交织一组K个有序元素的交织器。所公开的交织器可以表示为对应于两个局部抖动操作和全局置换操作的单个置换。单个排列可以表示为小矢量的小集合，并且可以递归地计算，从而允许使用比传统可能的更少量的存储器来存储和实现交织器。

114. 发明授权

US06785859B2 Interleaver for variable block size 有权
标题翻译：可变块大小的交织器
公开(公告)号：US06785859B2
公开(公告)日：2004-08-31
申请号：US09923468
申请日：2001-08-06
申请人： Haim Goldman
发明人： Haim Goldman
IPC分类号： H03M1329
CPC分类号： H03M13/2789 , H03M13/275 , H03M13/276 , H03M13/2771 , H03M13/2957
摘要： An interleaver structure for turbo codes with variable block size. The interleaver permutes symbols through multiplication by a parameter followed by modulus by the block size. A table of the multiplication parameter as a function of the block size permits adaptability to a wide range of block sizes without significant memory consumption.
摘要翻译：具有可变块大小的turbo码的交织器结构。交织器通过乘以一个参数后跟随模块的块大小来排列符号。作为块大小的函数的乘法参数的表允许对宽范围的块大小的适应性，而没有显着的存储器消耗。

115. 发明申请

US20040146029A1 Rate matching and channel interleaving for a communications system 审中-公开
标题翻译：通信系统的速率匹配和信道交织
公开(公告)号：US20040146029A1
公开(公告)日：2004-07-29
申请号：US10753546
申请日：2004-01-08
发明人： Wen Tong , Catherine Leretaille , Stephane Gosne
IPC分类号： H04B007/216
CPC分类号： H03M13/2739 , H03M13/00 , H03M13/271 , H03M13/275 , H03M13/276 , H03M13/2764 , H03M13/2792 , H03M13/2957 , H03M13/635 , H04L1/0041 , H04L1/0052 , H04L1/0068 , H04L1/0071
摘要： A method of and apparatus for matching a rate of data bits, in a matrix of data bits interleaved by a predetermined interleaving process, to a desired rate by deletion of redundant data bits or repetition of data bits derived from the matrix, includes steps of determining in a non-interleaved matrix of the data bits a pattern of bits to be deleted or repeated to provide the desired data rate, decoding an address of each bit in said pattern in a manner inverse to the interleaving process to produce a respective address of the bit in the matrix of interleaved data bits, and deleting or repeating the respective bit in the interleaved data bits in dependence upon the respective address. The address decoding is performed in the same manner as a coding of addresses for producing the interleaved data bits from the non-interleaved matrix of the data bits. The specification also discloses an advantageous interleaving process for channel interleaving in a 3rd generation CDMA wireless communications system, a shuffling method for a second stage of interleaving in such a system, and how the rate matching can be conveniently applied to turbo-coded data.
摘要翻译：一种方法和装置，用于通过删除冗余数据位或从该矩阵导出的数据比特的重复，将由预定交织处理交织的数据比特矩阵中的数据比特速率匹配到期望速率，包括以下步骤：确定在数据比特的非交织矩阵中，要删除或重复的比特模式以提供期望的数据速率，以与交织处理相反的方式对所述模式中的每个比特的地址进行解码，以产生相应的地址并且根据相应的地址删除或重复交织的数据比特中的各个比特。以与用于从数据比特的非交织矩阵产生交错数据比特的地址的编码相同的方式执行地址解码。本说明书还公开了一种用于第三代CDMA无线通信系统中的信道交织的有利的交织过程，在这种系统中用于第二级交织的混洗方法，以及如何将速率匹配方便地应用于turbo编码数据。

116. 发明申请

US20040114596A1 Method and apparatus for deinterleaving interleaved data stream in a communication system 有权
标题翻译：用于在通信系统中对交错数据流进行解交织的方法和装置
公开(公告)号：US20040114596A1
公开(公告)日：2004-06-17
申请号：US10695390
申请日：2003-10-29
发明人： Sang-Hyuck Ha , Seo-Weon Heo , Nam-Yul Yu , Min-Goo Kim , Seong-Woo Ahn
IPC分类号： H04L012/56
CPC分类号： H04L1/0066 , H03M13/271 , H03M13/275 , H03M13/276 , H03M13/2764 , H04L1/0045 , H04L1/0071
摘要： An apparatus and method for reading written symbols by deinterleaving to decode a written encoder packet in a receiver for a mobile communication system supporting turbo coding and interleaving, such that a turbo-coded/interleaved encoder packet has a bit shift value m, an up-limit value J and a remainder R, and a stream of symbols of the encoder packet is written in order of column to row. The apparatus and method perform the operations of generating an interim address by bit reversal order (BRO) assuming that the remainder R is 0 for the received symbols; calculating an address compensation factor for compensating the interim address in consideration of a column formed with the remainder; and generating a read address by adding the interim address and the address compensation factor for a decoding-required symbol, and reading a symbol written in the generated read address.
摘要翻译：一种用于通过解交织来读取写入的符号的装置和方法，用于解码支持turbo编码和交织的移动通信系统的接收机中的书写编码器分组，使得turbo编码/交织的编码器分组具有比特移位值m，限制值J和余数R，并且编码器分组的符号流以列到行的顺序写入。该装置和方法执行假设所接收的符号的余数R为0，通过比特反转顺序（BRO）生成中间地址的操作; 考虑到与其余部分形成的列，计算补偿中间地址的地址补偿因子; 以及通过添加用于解码所需符号的临时地址和地址补偿因子以及读取写入所生成的读取地址中的符号来生成读取地址。

117. 发明申请

US20040030985A1 Cross interleave reed-solomon code correction 审中-公开
标题翻译：交叉交织芦苇代码校正
公开(公告)号：US20040030985A1
公开(公告)日：2004-02-12
申请号：US10620738
申请日：2003-07-16
发明人： Alexander Kravtchenko , Marten Kabutz , Vijaya Ramadoss , Amit Singh
IPC分类号： H03M013/00
CPC分类号： H03M13/6566 , G11B20/1809 , G11B2020/1836 , H03M13/15 , H03M13/151 , H03M13/2732 , H03M13/275 , H03M13/276 , H03M13/2785
摘要： The invention relates to a method for cross interleave Reed-Solomon code correction comprising the steps of: inputting of a first C1 codeword into C1 decoder means from a first memory means, outputting of a second C1 codeword into a second memory means from the C1 decoder means, de-interleaving the second C1 codeword to produce a first C2 codeword in the second memory means.
摘要翻译：本发明涉及一种用于交叉交织里德 - 所罗门码校正的方法，包括以下步骤：从第一存储器装置输入第一C1码字到C1解码器装置，从C1解码器输出第二C1码字到第二存储器装置意味着，对第二C1码字进行解交织以在第二存储器装置中产生第一C2码字。

118. 发明申请

US20040025100A1 System with interleaver and de-interleaver 失效
标题翻译：具有交织器和解交织器的系统
公开(公告)号：US20040025100A1
公开(公告)日：2004-02-05
申请号：US10628278
申请日：2003-07-29
申请人： ALCATEL
发明人： Kris Gilbert Achiel Demuynck , Frank Octaaf Van der Putten
IPC分类号： H04L001/18 , H03M013/00
CPC分类号： H03M13/6566 , H03M13/2732 , H03M13/275 , H03M13/276 , H03M13/2785
摘要： Systems (1) with interleavers (2) for interleaving data units and with de-interleavers (3) for de-interleaving data units, are made more efficient and less complex by storing data units in the form of stacks in the memories (29,39) of said interleavers (2) and said de-interleavers (3), by calculating stack positions for data units to be (de)interleaved, and by adapting stacks through shifting before the interleaving or after the de-interleaving. Such a system (1) does not require more than null(Nnull1)(Dnull1)null/2 memory elements, the theoretical memory size for the block length N and the interleaving depth D. Said data units are stored at subsequent positions, with said data units at said subsequent positions being adapted through shifting before the interleaving or after the de-interleaving to further subsequent positions. An interleaver (2) comprises a calculator (21), a shifter (23) and an inserter (24). A de-interleaver (3) comprises a calculator (31), an extracter (34) and a shifter (33).
摘要翻译：具有用于交织数据单元的交织器（2）和用于解交织数据单元的解交织器（3）的系统（1）通过以堆栈的形式将数据单元存储在存储器（29，通过计算要交织的数据单元的堆栈位置，以及通过在交错之前或解交织之后通过移位来适配堆栈，所述交织器（2）和所述去交织器（3）的所述交织器（3）这样的系统（1）不需要多于[（N-1）（D-1）] / 2个存储器元件，块长度N的理论存储器大小和交织深度D.所述数据单元在后续存储位置，其中在所述后续位置处的所述数据单元通过在交错之前或解交织之后的移位来适应于进一步的后续位置。交织器（2）包括计算器（21），移位器（23）和插入器（24）。解交织器（3）包括计算器（31），扩展器（34）和移位器（33）。

119. 发明授权

US06637000B2 Turbo code interleaver using linear congruential sequences 有权
公开(公告)号：US06637000B2
公开(公告)日：2003-10-21
申请号：US09933979
申请日：2001-08-20
申请人： Douglas N. Rowitch , Fuyun Ling
发明人： Douglas N. Rowitch , Fuyun Ling
IPC分类号： H03M1300
CPC分类号： H03M13/2789 , H03M13/271 , H03M13/275 , H03M13/2764 , H03M13/2771 , H03M13/2957
摘要： A turbo code interleaver using linear congruential sequences may be employed as a two-dimensional interleaver in a turbo coder that also includes first and second constituent encoders. The interleaver and the first encoder are each configured to receive input bits. The first encoder produces output symbols therefrom. The interleaver receives the input bits sequentially by row. A linear congruential sequence recursion algorithm within the interleaver serves to pseudo-randomly rearrange, or shuffle, the bits within each row of the interleaver. The bits are then output from the interleaver sequentially by column. The second encoder is configured to receive the interleaved bits from the interleaver. The second encoder produces output symbols therefrom. The two streams of output symbols are multiplexed together, with appropriate puncturing. If desired, the linear congruential recursion sequence can be generated in reverse.

120. 发明申请

US20030140304A1 Method and apparatus for coding bits of data in parallel 失效
标题翻译：并行编码数据位的方法和装置
公开(公告)号：US20030140304A1
公开(公告)日：2003-07-24
申请号：US10020532
申请日：2001-12-14
发明人： James Y. Hurt , Michael A. Howard , Robert J. Fuchs
IPC分类号： H03M013/03
CPC分类号： H04L1/005 , H03M13/235 , H03M13/275 , H03M13/2764 , H03M13/2903 , H03M13/2972 , H03M13/6561 , H03M13/6563 , H03M13/6575 , H04L1/0043 , H04L1/0065 , H04L1/0066 , H04L1/0069 , H04L1/0071
摘要： A method and apparatus for encoding multiple bits in parallel wherein outputs are generated recursively. During each clock cycle, the encoder processes multiple bits and generates outputs consistent with those generated sequentially over multiple clock cycles in a conventional convolutional encoder. In one embodiment, input data is stored in multiple memory storage units, which are then each uniquely addressed to provide data to parallel encoders.
摘要翻译：并行地编码多个比特的方法和装置，其中递归生成输出。在每个时钟周期期间，编码器处理多个比特并且产生与常规卷积编码器中的多个时钟周期顺序生成的输出一致的输出。在一个实施例中，输入数据存储在多个存储器存储单元中，然后每个存储单元被唯一地寻址以向并行编码器提供数据。

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