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111. 发明授权

US08158475B2 Gate electrodes of HVMOS devices having non-uniform doping concentrations 有权
标题翻译：具有不均匀掺杂浓度的HVMOS器件的栅电极
公开(公告)号：US08158475B2
公开(公告)日：2012-04-17
申请号：US12879777
申请日：2010-09-10
申请人： Ru-Yi Su , Puo-Yu Chiang , Jeng Gong , Tsung-Yi Huang , Chun-Lin Tsai , Chien-Chih Chou
发明人： Ru-Yi Su , Puo-Yu Chiang , Jeng Gong , Tsung-Yi Huang , Chun-Lin Tsai , Chien-Chih Chou
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L29/0653 , H01L29/0847 , H01L29/086 , H01L29/1045 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.
摘要翻译：半导体结构包括半导体衬底; 覆盖半导体衬底的第一导电类型的第一高电压阱（HVW）区域; 第二导电类型的第二阱区域，与覆盖半导体衬底并横向邻接第一阱区的第一导电类型相反; 栅极电介质，其从所述第一阱区域上延伸到所述第二阱区域上方; 第二阱区中的漏极区; 栅极电介质的与漏极区相反的一侧的源极区; 和栅电极上的栅电极。栅电极包括直接在第二阱区上的第一部分和直接在第一阱区上的第二部分。第一部分具有低于第二部分的第二杂质浓度的第一杂质浓度。

112. 发明申请

US20120003803A1 Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance 有权
标题翻译：具有高击穿电压和低导通电阻的侧向功率MOSFET
公开(公告)号：US20120003803A1
公开(公告)日：2012-01-05
申请号：US13175246
申请日：2011-07-01
申请人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
发明人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; HVW中的场环，占据HVW的顶部，其中场环是第一导电类型; 与场环和HVW的一部分接触的绝缘区域; 位于所述绝缘区域上的栅电极; 所述HVW中的漏极区域，其中所述漏极区域是所述第二导电类型; 并且其中所述HVW水平地延伸到所述漏极区域比所述预HVW; 以及与漏极区域相邻并且在与栅极电极相反的一侧的源极区域。

113. 发明申请

US20110220997A1 LDMOS Device Having Increased Punch-Through Voltage and Method For Making Same 有权
标题翻译：具有增加穿通电压的LDMOS器件和制造相同的方法
公开(公告)号：US20110220997A1
公开(公告)日：2011-09-15
申请号：US12720834
申请日：2010-03-10
申请人： Tsung-Yi Huang , Huan-Ping Chu , Ching-Yao Yang , Hung-Der Su
发明人： Tsung-Yi Huang , Huan-Ping Chu , Ching-Yao Yang , Hung-Der Su
IPC分类号： H01L29/78 , H01L21/8249
CPC分类号： H01L29/7816 , H01L29/0878 , H01L29/66681
摘要： The present invention discloses an LDMOS device having an increased punch-through voltage and a method for making same. The LDMOS device includes: a substrate; a well of a first conductive type formed in the substrate; an isolation region formed in the substrate; a body region of a second conductive type in the well; a source in the body region; a drain in the well; a gate structure on the substrate; and a first conductive type dopant region beneath the body region, for increasing a punch-through voltage.
摘要翻译：本发明公开了一种具有增加的穿通电压的LDMOS器件及其制造方法。 LDMOS器件包括：衬底; 在基板中形成的第一导电类型的阱; 形成在衬底中的隔离区; 井中的第二导电类型的体区; 身体的一个来源; 井中排水基板上的栅极结构; 以及在身体区域下面的第一导电型掺杂区域，用于增加穿通电压。

114. 发明申请

US20110215403A1 High Voltage Metal Oxide Semiconductor Device and Method for Making Same 有权
标题翻译：高压金属氧化物半导体器件及其制造方法
公开(公告)号：US20110215403A1
公开(公告)日：2011-09-08
申请号：US12715501
申请日：2010-03-02
申请人： Tsung-Yi Huang , Huan-Ping Chu , Ching-Yao Yang , Hug-Der Su
发明人： Tsung-Yi Huang , Huan-Ping Chu , Ching-Yao Yang , Hug-Der Su
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L29/0847 , H01L29/1045 , H01L29/7833 , H01L29/7835
摘要： The present invention discloses a high voltage metal oxide semiconductor (HVMOS) device and a method for making same. The high voltage metal oxide semiconductor device comprises: a substrate; a gate structure on the substrate; a well in the substrate, the well defining a device region from top view; a first drift region in the well; a source in the well; a drain in the first drift region, the drain being separated from the gate structure by a part of the first drift region; and a P-type dopant region not covering all the device region, wherein the P-type dopant region is formed by implanting a P-type dopant for enhancing the breakdown voltage of the HVMOS device (for N-type HVMOS device) or reducing the ON resistance of the HVMOS device (for P-type HVMOS device).
摘要翻译：本发明公开了一种高电压金属氧化物半导体（HVMOS）器件及其制造方法。高电压金属氧化物半导体器件包括：衬底; 基板上的栅极结构; 在衬底中的阱，阱从顶视图限定器件区域; 井中的第一漂移区; 井中的来源所述第一漂移区域中的漏极，所述漏极由所述第一漂移区域的一部分与所述栅极结构分离; 以及不覆盖所有器件区域的P型掺杂剂区域，其中通过注入用于增强HVMOS器件的击穿电压（对于N型HVMOS器件）的P型掺杂剂形成P型掺杂剂区域，或者减少 HVMOS器件的导通电阻（P型HVMOS器件）。

115. 发明授权

US07977743B2 Alternating-doping profile for source/drain of a FET 有权
标题翻译： FET的源极/漏极的交替掺杂分布
公开(公告)号：US07977743B2
公开(公告)日：2011-07-12
申请号：US12392343
申请日：2009-02-25
申请人： Chen-Liang Chu , Chun-Ting Liao , Fei-Yuh Chen , Tsung-Yi Huang
发明人： Chen-Liang Chu , Chun-Ting Liao , Fei-Yuh Chen , Tsung-Yi Huang
IPC分类号： H01L29/06
CPC分类号： H01L29/0847 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-doping profile region. The alternating-doping profile region may include alternating regions of high and low concentrations of a dopant. In an embodiment, the transistor is a high voltage transistor.
摘要翻译：提供半导体器件。在一个实施例中，该器件包括衬底和形成在衬底上的晶体管。晶体管可以包括栅极结构，源极区和漏极区。漏极区域包括交替掺杂分布区域。交变掺杂剖面区域可以包括掺杂剂的高浓度和低浓度的交替区域。在一个实施例中，晶体管是高压晶体管。

116. 发明申请

US20110008944A1 Gate Electrodes of HVMOS Devices Having Non-Uniform Doping Concentrations 有权
标题翻译：具有不均匀掺杂浓度的HVMOS器件的栅极电极
公开(公告)号：US20110008944A1
公开(公告)日：2011-01-13
申请号：US12879777
申请日：2010-09-10
申请人： Ru-Yi Su , Puo-Yu Chiang , Jeng Gong , Tsung-Yi Huang , Chun-Lin Tsai , Chien-Chih Chou
发明人： Ru-Yi Su , Puo-Yu Chiang , Jeng Gong , Tsung-Yi Huang , Chun-Lin Tsai , Chien-Chih Chou
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L29/0653 , H01L29/0847 , H01L29/086 , H01L29/1045 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.
摘要翻译：半导体结构包括半导体衬底; 覆盖半导体衬底的第一导电类型的第一高电压阱（HVW）区域; 第二导电类型的第二阱区域，与覆盖半导体衬底并横向邻接第一阱区的第一导电类型相反; 栅极电介质，其从所述第一阱区域上延伸到所述第二阱区域上方; 第二阱区中的漏极区; 栅极电介质的与漏极区相反的一侧的源极区; 和栅电极上的栅电极。栅电极包括直接在第二阱区上的第一部分和直接在第一阱区上的第二部分。第一部分具有低于第二部分的第二杂质浓度的第一杂质浓度。

117. 发明申请

US20100213542A1 ALTERNATING-DOPING PROFILE FOR SOURCE/DRAIN OF A FET 有权
标题翻译： FET的源/漏极的替代配置
公开(公告)号：US20100213542A1
公开(公告)日：2010-08-26
申请号：US12392343
申请日：2009-02-25
申请人： Chen-Liang Chu , Chun-Ting Liao , Fei-Yuh Chen , Tsung-Yi Huang
发明人： Chen-Liang Chu , Chun-Ting Liao , Fei-Yuh Chen , Tsung-Yi Huang
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-doping profile region. The alternating-doping profile region may include alternating regions of high and low concentrations of a dopant. In an embodiment, the transistor is a high voltage transistor.
摘要翻译：提供半导体器件。在一个实施例中，该器件包括衬底和形成在衬底上的晶体管。晶体管可以包括栅极结构，源极区和漏极区。漏极区域包括交替掺杂分布区域。交变掺杂剖面区域可以包括掺杂剂的高浓度和低浓度的交替区域。在一个实施例中，晶体管是高压晶体管。

118. 发明申请

US20100197098A1 METHOD OF FABRICATING A HIGH PERFORMANCE POWER MOS 有权
标题翻译：制造高性能功率MOS的方法
公开(公告)号：US20100197098A1
公开(公告)日：2010-08-05
申请号：US12757242
申请日：2010-04-09
申请人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
发明人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
IPC分类号： H01L21/336
CPC分类号： H01L29/7816 , H01L21/26586 , H01L29/086 , H01L29/0878 , H01L29/402 , H01L29/66689 , H01L29/7817
摘要： A method of fabricating a semiconductor device includes forming in the substrate a well region comprising a first type of dopant; forming in the well region a base region comprising a second type of dopant different from the first type of dopant; and forming in the substrate source and drain regions comprising the first type of dopant. The method further includes forming on the substrate a gate electrode interposed laterally between the source and drain regions; and forming on the substrate a gate spacer disposed laterally between the source region and the gate electrode adjacent a side of the gate electrode and having a conductive feature embedded therein. The well region surrounds the drain region and the base region, and the base region is disposed partially underlying the gate electrode surrounding the source region defining a channel under the gate electrode of having a length substantially less than half the length of the gate electrode.
摘要翻译：制造半导体器件的方法包括在衬底中形成包括第一类掺杂剂的阱区; 在所述阱区中形成包含不同于所述第一类型掺杂剂的第二类型掺杂剂的基极区; 以及在包括第一类型掺杂剂的衬底源极和漏极区域中形成。该方法还包括在衬底上形成横向插入在源区和漏区之间的栅电极; 以及在所述衬底上形成栅极间隔件，所述栅极间隔件横向设置在所述源区域和所述栅电极之间，邻近所述栅电极的一侧并且具有嵌入其中的导电特征。阱区域围绕漏极区域和基极区域，并且基极区域部分地设置在围绕源极区域的栅极电极周围，该源极区域限定栅极电极下方的沟道，其长度基本上小于栅电极的长度的一半。

119. 发明申请

US20100006934A1 Gate Electrodes of HVMOS Devices Having Non-Uniform Doping Concentrations 有权
标题翻译：具有不均匀掺杂浓度的HVMOS器件的栅极电极
公开(公告)号：US20100006934A1
公开(公告)日：2010-01-14
申请号：US12170133
申请日：2008-07-09
申请人： Ru-Yi Su , Puo-Yu Chiang , Jeng Gong , Tsung-Yi Huang , Chun-Lin Tsai , Chien-Chih Chou
发明人： Ru-Yi Su , Puo-Yu Chiang , Jeng Gong , Tsung-Yi Huang , Chun-Lin Tsai , Chien-Chih Chou
IPC分类号： H01L29/78
CPC分类号： H01L29/4983 , H01L29/0653 , H01L29/0847 , H01L29/086 , H01L29/1045 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.
摘要翻译：半导体结构包括半导体衬底; 覆盖半导体衬底的第一导电类型的第一高电压阱（HVW）区域; 第二导电类型的第二阱区域，与覆盖半导体衬底并横向邻接第一阱区的第一导电类型相反; 栅极电介质，其从所述第一阱区域上延伸到所述第二阱区域上方; 第二阱区中的漏极区; 栅极电介质的与漏极区相反的一侧的源极区; 和栅电极上的栅电极。栅电极包括直接在第二阱区上的第一部分和直接在第一阱区上的第二部分。第一部分具有低于第二部分的第二杂质浓度的第一杂质浓度。

120. 发明申请

US20100006933A1 Stabilizing Breakdown Voltages by Forming Tunnels for Ultra-High Voltage Devices 有权
标题翻译：通过形成用于超高压器件的隧道来稳定击穿电压
公开(公告)号：US20100006933A1
公开(公告)日：2010-01-14
申请号：US12170285
申请日：2008-07-09
申请人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Puo-Yu Chiang
发明人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Puo-Yu Chiang
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/266 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW; and a tunnel of the first conductivity type in the pre-HVW and the HVW, and electrically connecting the field ring and the semiconductor substrate.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; 第一导电类型的场环占据HVW的顶部; 以及预HVW和HVW中的第一导电类型的隧道，并且电场连接场环和半导体衬底。

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