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111. 发明授权

US07072222B2 Nonvolatile memory system, semiconductor memory and writing method 失效
公开(公告)号：US07072222B2
公开(公告)日：2006-07-04
申请号：US11075813
申请日：2005-03-10
申请人： Tatsuya Ishii , Hitoshi Miwa , Osamu Tsuchiya , Shooji Kubono
发明人： Tatsuya Ishii , Hitoshi Miwa , Osamu Tsuchiya , Shooji Kubono
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C16/0491 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3431 , G11C16/3459 , G11C2216/18
摘要： A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

112. 发明申请

US20050157550A1 Nonvolatile memory system, semiconductor memory and writing method 失效
标题翻译：非易失性存储器系统，半导体存储器和写入方法
公开(公告)号：US20050157550A1
公开(公告)日：2005-07-21
申请号：US11075813
申请日：2005-03-10
申请人： Tatsuya Ishii , Hitoshi Nina , Osamu Tsuchiya , Shooji Kubono
发明人： Tatsuya Ishii , Hitoshi Nina , Osamu Tsuchiya , Shooji Kubono
IPC分类号： G11C16/02 , G11C7/00 , G11C11/34 , G11C16/04 , G11C16/10
CPC分类号： G11C16/3427 , G11C16/0491 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3431 , G11C16/3459 , G11C2216/18
摘要： A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.
摘要翻译：非易失性半导体存储器由于与字线相关的干扰而恢复存储器单元的阈值的变化。非易失性存储器在每次写入操作之后连续执行许多写入操作，而不执行单扇区擦除，执行比通常的写入操作更快的附加写入操作，以及减轻用于附加写入的软件的负担。存储在指定扇区中的数据在保存在寄存器中之前被读出，并且当给出预定命令时，所选扇区被进行单扇区擦除。然后写入预期值数据由保存的数据和要另外编写的数据形成，完成写入操作。

113. 发明授权

US06873552B2 Nonvolatile memory system, semiconductor memory, and writing method 失效
标题翻译：非易失性存储器系统，半导体存储器和写入方法
公开(公告)号：US06873552B2
公开(公告)日：2005-03-29
申请号：US10681280
申请日：2003-10-09
申请人： Tatsuya Ishii , Hitoshi Miwa , Osamu Tsuchiya , Shooji Kubono
发明人： Tatsuya Ishii , Hitoshi Miwa , Osamu Tsuchiya , Shooji Kubono
IPC分类号： G11C16/02 , G11C7/00 , G11C11/34 , G11C16/04 , G11C16/10
CPC分类号： G11C16/3427 , G11C16/0491 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3431 , G11C16/3459 , G11C2216/18
摘要： A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.
摘要翻译：非易失性半导体存储器由于与字线相关的干扰而恢复存储器单元的阈值的变化。非易失性存储器在每次写入操作之后连续执行许多写入操作，而不执行单扇区擦除，执行比通常的写入操作更快的附加写入操作，以及减轻用于附加写入的软件的负担。存储在指定扇区中的数据在保存在寄存器中之前被读出，并且当给出预定命令时，所选扇区被进行单扇区擦除。然后写入预期值数据由保存的数据和要另外编写的数据形成，完成写入操作。

114. 发明授权

US06385092B1 Nonvolatile memory system, semiconductor memory, and writing method 有权
公开(公告)号：US06385092B1
公开(公告)日：2002-05-07
申请号：US09961300
申请日：2001-09-25
申请人： Tatsuya Ishii , Hitoshi Miwa , Osamu Tsuchiya , Shooji Kubono
发明人： Tatsuya Ishii , Hitoshi Miwa , Osamu Tsuchiya , Shooji Kubono
IPC分类号： G11C1604
CPC分类号： G11C16/3427 , G11C16/0491 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3431 , G11C16/3459 , G11C2216/18
摘要： A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

115. 发明授权

US5675172A Metal-insulator-semiconductor device having reduced threshold voltage and high mobility for high speed/low-voltage operation 失效
标题翻译：金属绝缘体半导体器件具有降低的阈值电压和用于高速/低电压操作的高迁移率
公开(公告)号：US5675172A
公开(公告)日：1997-10-07
申请号：US441707
申请日：1995-05-15
申请人： Masafumi Miyamoto , Tatsuya Ishii
发明人： Masafumi Miyamoto , Tatsuya Ishii
IPC分类号： H01L29/43 , H01L21/265 , H01L21/336 , H01L21/8238 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/66575 , H01L21/823807 , H01L29/1033 , H01L29/1083 , H01L29/66659 , H01L29/7802 , H01L29/7838 , H01L21/2652 , H01L21/26586 , H01L29/0847 , H01L29/1095 , H01L29/66537
摘要： A MIS device comprising a pair of first doped layers of a second conductivity type forming source/drain regions in a semiconductor base structure of a first conductivity type, and a gate electrode formed in a region between the first doped layers of the second conductivity type on a gate insulating film formed on the semiconductor base structure having a three-layer structure consisting of a second doped layer of the first conductivity type, a third doped layer of the second conductivity type and a fourth doped layer of the first conductivity type having an impurity concentration higher than that of the semiconductor base structure, which are formed in that order in the direction of depth from the surface of a channel region extending between the source/drain regions, the thickness of the third doped layer is determined so that the third doped layer is depleted by the respective built-in potentials of pn junctions formed by the second doped layer and the third doped layer and by the fourth doped layer and the third doped layer, respectively. Even when the MIS device of this structure is miniaturized, the subthreshold swing can be reduced to a value small enough to enable the lowering of the threshold voltage, the electric field intensity in the interface of the gate insulating film is reduced to enhance the carrier mobility and hence the MIS device is suitable for low-voltage operation.
摘要翻译：一种MIS器件，包括在第一导电类型的半导体基底结构中形成源极/漏极区的第二导电类型的一对第一掺杂层和形成在第二导电类型的第一掺杂层之间的区域中的栅电极形成在具有由第一导电类型的第二掺杂层，第二导电类型的第三掺杂层和具有杂质的第一导电类型的第四掺杂层组成的三层结构的半导体基底结构上的栅绝缘膜浓度高于半导体基底结构的浓度，其从在源/漏区之间延伸的沟道区的表面的深度方向依次形成，第三掺杂层的厚度被确定为使得第三掺杂层被由第二掺杂层和第三掺杂层形成的pn结的相应内置电位以及由fo 第二掺杂层和第三掺杂层。即使当这种结构的MIS器件小型化时，亚阈值摆幅也可以减小到足以使阈值电压降低的值，从而降低栅极绝缘膜的界面中的电场强度，从而提高载流子迁移率因此MIS器件适用于低电压工作。

116. 发明授权

US5393998A Semiconductor memory device containing junction field effect transistor 失效
标题翻译：包含结型场效应晶体管的半导体存储器件
公开(公告)号：US5393998A
公开(公告)日：1995-02-28
申请号：US65334
申请日：1993-05-21
申请人： Tatsuya Ishii , Tatsuo Shinohara
发明人： Tatsuya Ishii , Tatsuo Shinohara
IPC分类号： H01L27/10 , G11C11/404 , H01L21/337 , H01L27/108 , H01L29/10 , H01L29/80 , G11C11/24 , H01L31/112
CPC分类号： H01L29/66901 , G11C11/404 , H01L27/10805 , H01L29/1058
摘要： The miniaturization of junction field effect transistors constituting memory cells and higher integration of a dynamic semiconductor memory device are attained. Word lines composed of a p-type impurity diffusion layer are formed on an n-type silicon substrate. An n-type impurity diffusion layer is formed within the p-type impurity diffusion layer. The n-type impurity diffusion layer constitutes two source-drain regions and a channel region, and the p-type impurity diffusion layer constitutes a gate region in each junction field effect transistor. The diffusion layer depth of the channel region is less than that of the source-drain regions. Bit lines are connected to one source-drain region, and storage nodes are connected to the other source-drain region. Each capacitor is made of a storage node, a dielectric film and a cell plate electrode.
摘要翻译：实现了构成存储单元的结型场效应晶体管的小型化和动态半导体存储器件的更高集成度。由p型杂质扩散层构成的字线形成在n型硅衬底上。在p型杂质扩散层内形成n型杂质扩散层。 n型杂质扩散层构成两个源极 - 漏极区域和沟道区域，并且p型杂质扩散层在每个结场效应晶体管中构成栅极区域。沟道区的扩散层深度小于源极 - 漏极区的扩散层深度。位线连接到一个源极 - 漏极区域，并且存储节点连接到另一个源极 - 漏极区域。每个电容器由存储节点，电介质膜和单元板电极制成。

117. 发明授权

US5243209A Semiconductor memory device including junction field effect transistor and capacitor and method of manufacturing the same 失效
标题翻译：包括结场效应晶体管和电容器的半导体存储器件及其制造方法
公开(公告)号：US5243209A
公开(公告)日：1993-09-07
申请号：US788396
申请日：1991-11-06
申请人： Tatsuya Ishii
发明人： Tatsuya Ishii
IPC分类号： G11C11/404 , H01L21/82 , H01L27/10 , H01L27/108 , H01L29/808
CPC分类号： H01L29/8083 , H01L21/82 , H01L27/10808 , H01L27/10823
摘要： A dynamic random access memory includes a memory cell including a junction field effect transistor and a capacitor. A first conductivity-type semiconductor layer is formed on a main surface of a semiconductor substrate. The semiconductor layer includes a columnar part extending from the main surface of the semiconductor substrate and having a top surface and a sidewall surface. The junction field effect transistor is formed in the columnar part, and the capacitor is formed on the top surface of the columnar part. The junction field effect transistor includes a second conductivity-type impurity region and a gate electrode. The second conductivity-type impurity region is formed on the sidewall surface of the columnar part. The gate electrode is formed to surround the sidewall surface of the columnar part to be electrically in contact with the second conductivity-type impurity, region. The capacitor includes a storage node, a dielectric film, and a cell plate electrode. The storage node is formed to be electrically in contact with the top surface of the columnar part. The dielectric film is formed on the storage node. The cell plate electrode is formed on the dielectric film. It is possible to attain higher degree of integration and higher density of the memory cell without causing variation in the characteristics of the transistor included in the memory cell and without decreasing the noise margin of operation of the semiconductor substrate.
摘要翻译：动态随机存取存储器包括具有结型场效应晶体管和电容器的存储单元。第一导电型半导体层形成在半导体衬底的主表面上。半导体层包括从半导体衬底的主表面延伸并具有顶表面和侧壁表面的柱状部分。结型场效应晶体管形成在柱状部分中，电容器形成在柱状部分的顶表面上。结型场效应晶体管包括第二导电型杂质区和栅电极。第二导电型杂质区域形成在柱状部分的侧壁表面上。栅电极被形成为围绕柱状部分的侧壁表面与第二导电型杂质区电接触。电容器包括存储节点，电介质膜和电池板电极。存储节点形成为与柱状部件的顶表面电接触。电介质膜形成在存储节点上。电池板电极形成在电介质膜上。可以获得更高的集成度和更高密度的存储单元，而不会引起包括在存储单元中的晶体管的特性的变化，并且不会降低半导体衬底的工作噪声容限。

118. 发明授权

US5010379A Semiconductor memory device with two storage nodes 失效
标题翻译：半导体存储器件具有两个存储节点
公开(公告)号：US5010379A
公开(公告)日：1991-04-23
申请号：US369965
申请日：1989-06-22
申请人： Tatsuya Ishii
发明人： Tatsuya Ishii
IPC分类号： H01L27/04 , G11C11/404 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10829 , G11C11/404
摘要： A semiconductor memory device includes a p-type semiconductor substrate (1), a trench (16) formed on the substrate (1), a first region (19) of a capacitor cell plate formed on the side walls and the bottom surface of the trench (16) and formed by an n-type impurity layer, two capacitor storage nodes (2a) having their surfaces covered by capacitor dielectric films (7a, 8a) and formed along the side walls of the trench (16) for facing to each other, a second region (3a) of the cell plate formed of an electrically conductive material, the second region (3a) being interposed between the two storage nodes (2a) and connected to the first region (19) of the cell plate at the bottom surface of the trench (16), and n-channel type field effect transistors (9, 10, 12, 18, 28) each connected to one of the storage nodes (2a) and formed on the substrate (1).
摘要翻译：半导体存储器件包括p型半导体衬底（1），形成在衬底（1）上的沟槽（16），形成在侧壁上的电容器单元板的第一区域（19）和沟槽（16）并由n型杂质层形成，其两个电容器存储节点（2a）的表面被电容器电介质膜（7a，8a）覆盖并且沿着沟槽（16）的侧壁形成，以面对每个另一方面，由导电材料形成的电池板的第二区域（3a），第二区域（3a）插入在两个存储节点（2a）之间并且连接到电池板的第一区域（19）沟槽（16）的底表面和分别连接到一个存储节点（2a）并形成在衬底（1）上）的n沟道型场效应晶体管（9,10,12,18,28）。

119. 发明授权

US11381702B2 Image reading device, image reading method, and computer-readable medium 有权
公开(公告)号：US11381702B2
公开(公告)日：2022-07-05
申请号：US17141240
申请日：2021-01-05
申请人： Daisuke Nikaku , Tatsuya Ishii , Hideki Hashimoto , Yutaka Ohmiya , Takayuki Kawamoto
发明人： Daisuke Nikaku , Tatsuya Ishii , Hideki Hashimoto , Yutaka Ohmiya , Takayuki Kawamoto
IPC分类号： H04N1/028 , H04N1/00
摘要： An image reading device includes a light source configured to irradiate a subject; a reading unit configured to detect reflected light generated by a subject reflecting light emitted from the light source, to perform reading; and a control unit configured to perform turn-on control on the light source. The control unit is configured to perform the turn-on control to change a turn-on condition such that the light source is turned on during a period when at least a detection region including an image pattern on the subject passes through a reading position of a reading unit, based on position information of the image pattern of the subject in a first operation mode for reading the subject, and perform the turn-on control to make the turn-on condition of the light source constant regardless of the image pattern of the subject in a second operation mode for reading the subject.

120. 发明申请

US20210080888A1 IMAGE READING DEVICE, IMAGE INSPECTION DEVICE, AND IMAGE FORMING APPARATUS 有权
公开(公告)号：US20210080888A1
公开(公告)日：2021-03-18
申请号：US17005279
申请日：2020-08-27
申请人： Tatsuya Ishii , Yoshio Konno
发明人： Tatsuya Ishii , Yoshio Konno
IPC分类号： G03G15/00 , G03G21/18
摘要： An image reading device includes a reader, a first background part, a second background part, and circuitry. The reader reads a pattern formed on a medium. The first and second background parts are disposed opposite the reader via a conveyance passage of the medium. The second background part has a higher light reflectance than that of the first background part. The circuitry moves one of the first and second background parts to a facing position at which the one faces the reader via the conveyance passage of the medium. The circuitry moves the first background part to the facing position in a case in which the pattern is a light color and the medium is transparent. The circuitry moves the second background part to the facing position in a case in which the pattern is a dark color darker than the light color or the medium is not transparent.

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