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    • 112. 发明授权
    • Flash memory devices with flash fuse cell arrays
    • 带闪存保险丝单元阵列的闪存设备
    • US07561486B2
    • 2009-07-14
    • US11346520
    • 2006-02-02
    • Tae-Seong KimGyu-Hong Kim
    • Tae-Seong KimGyu-Hong Kim
    • G11C17/18
    • G11C29/021G11C16/04G11C16/0425G11C29/028G11C29/789G11C29/82
    • A flash memory device includes a flash cell array, a first flash fuse cell fusing circuit, a second flash fuse cell fusing circuit, a third flash fuse cell fusing circuit and a plurality of fuse sense amplifying circuits. The first, second and third flash fuse cell fusing circuits all share bit lines with a flash cell array and have flash fuse cells. The first flash fuse cell fusing circuit may be used to control a connection between the flash cell array and an external logic circuit. The second flash fuse cell fusing circuit may be used to change an address of a defective cell into an address of a redundancy cell. The third flash fuse cell fusing circuit may be used to control a DC level for adjusting a reference value used in a manufacturing process of the flash memory device. The fuse sense amplifying circuits are coupled to the bit lines to read data from the bit lines, respectively.
    • 闪存器件包括闪存单元阵列,第一闪存熔丝单元熔丝电路,第二闪存熔丝单元熔丝电路,第三闪存熔丝单元熔断电路和多个熔丝读出放大电路。 第一,第二和第三闪存熔丝单元熔断电路都与闪存单元阵列共享位线并具有闪存熔丝单元。 第一闪存熔丝单元熔断电路可用于控制闪存单元阵列和外部逻辑电路之间的连接。 第二闪存熔丝单元熔断电路可用于将有缺陷单元的地址改变为冗余单元的地址。 第三闪存熔丝单元熔断电路可以用于控制DC电平以调整在闪速存储器件的制造过程中使用的参考值。 熔丝读出放大电路分别耦合到位线以从位线读取数据。