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111. 发明授权

US5854796A Method of and apparatus for testing semiconductor memory 失效
标题翻译：半导体存储器的测试方法和设备
公开(公告)号：US5854796A
公开(公告)日：1998-12-29
申请号：US861344
申请日：1997-05-21
申请人： Shinya Sato
发明人： Shinya Sato
IPC分类号： G01R31/28 , G01R31/3193 , G11C29/00 , G11C29/40 , G11C29/44 , G06F11/00
CPC分类号： G11C29/44 , G01R31/31935
摘要： A failure analysis memory for storing failure information representative of a test result of a semiconductor memory under test is divided into a plurality of blocks with compacted addresses, and a compaction memory having areas corresponding respectively to the blocks of the failure analysis memory is prepared. Data indicative of a failure cell in any one of the blocks of the failure analysis memory is written in an area of the compaction memory which corresponds to the any one of the blocks. Minimum and maximum addresses of addresses at which failure cells are present in the blocks are determined, and failure data is read from the failure analysis memory in a range between the minimum and maximum addresses of each of the blocks, which correspond to the areas of the compaction memory which store the data indicative of a failure cell.
摘要翻译：用于存储表示被测半导体存储器的测试结果的故障信息的故障分析存储器被分成具有压缩地址的多个块，并且准备具有分别对应于故障分析存储器的块的区域的压缩存储器。指示故障分析存储器的任何一个块中的故障单元的数据被写入对应于任一个块的压缩存储器的区域中。确定块中存在故障单元的地址的最小和最大地址，并且在每个块的最小和最大地址之间的范围内，从故障分析存储器中读取故障数据，这些区域对应于压缩存储器，其存储指示故障单元的数据。

112. 发明授权

US5790559A Semiconductor memory testing apparatus 失效
标题翻译：半导体存储器测试仪器
公开(公告)号：US5790559A
公开(公告)日：1998-08-04
申请号：US825356
申请日：1997-03-28
申请人： Shinya Sato
发明人： Shinya Sato
IPC分类号： G01R31/3193 , G11C29/00 , G11C29/10 , G11C29/44 , G06F11/60
CPC分类号： G11C29/76 , G01R31/31935 , G11C29/10 , G11C29/44
摘要： A memory unit for storing failure data of a semiconductor memory under test comprises a plurality of interleaved DRAMs. A buffer memory temporarily stores failure data to be stored into the DRAMs and addresses thereof. The DRAMs are associated respectively with storage controllers which store failure addresses whose row addresses correspond to the DRAMs, among inputted failure addresses, into buffer memories associated respectively with the DRAMs. Write controllers are associated respectively with the DRAMs, for reading the failure data from the buffer memories and writing the failure data into the DRAMs in a high-speed write mode.
摘要翻译：用于存储被测半导体存储器的故障数据的存储单元包括多个交错DRAM。缓冲存储器临时存储要存储到DRAM中的故障数据及其地址。 DRAM分别与存储控制器相关联，存储控制器将其地址对应于输入的故障地址中的DRAM的故障地址存储到与DRAM相关联的缓冲存储器中。写控制器分别与DRAM相关联，用于从缓冲存储器读取故障数据并将故障数据以高速写入模式写入DRAM。

113. 发明授权

US5689392A Tape cassette 失效
标题翻译：磁带盒
公开(公告)号：US5689392A
公开(公告)日：1997-11-18
申请号：US715779
申请日：1991-06-14
申请人： Shinya Sato
发明人： Shinya Sato
IPC分类号： G11B23/087 , G11B23/02
CPC分类号： G11B23/08757 , G11B23/08785
摘要： A tape cassette having a tape guide for contacting with a magnetic tape provided as a tape coil within a main cassette body, and guiding the running of the magnetic tape, is disclosed. The tape guide for guiding the magnetic tape is molded with a lower cassette half integrally from an ultra high molecular resin having a molecular weight ranging from 500,000 to 1,000,000 for simplifying the assembling process and reducing production costs as well as preventing adverse effects of deviation from true verticality of the tape guide on the magnetic tape during recording/reproduction or fast feed/rewind to assure stable tape running.
摘要翻译：公开了一种带盒，其具有用于与在主盒体内设置为带状线圈的磁带接触并引导磁带的运行的磁带引导件。用于引导磁带的磁带引导件由分子量为500,000至1,000,000的超高分子量树脂整体模制成下盒式磁带，以简化组装过程并降低生产成本，并防止偏离真实的不利影响记录/再现期间磁带上的磁带引导件的垂直度或快速进给/重绕以确保磁带运行稳定。

114. 发明授权

US5539699A Flash memory testing apparatus 失效
标题翻译：闪存测试仪
公开(公告)号：US5539699A
公开(公告)日：1996-07-23
申请号：US304583
申请日：1994-09-12
申请人： Shinya Sato , Hiromi Ohshima
发明人： Shinya Sato , Hiromi Ohshima
IPC分类号： G01R31/28 , G01R31/3193 , G11C17/00 , G11C29/00 , G11C29/44 , G11C29/56
CPC分类号： G11C29/44 , G01R31/31935 , G06F2201/88
摘要： A flash memory testing apparatus is capable of testing a flash memory while maintaining the conventional memory test functions. The flash memory testing apparatus obtains the number of programming pulses applied to each address of the flash memory. The flash memory testing apparatus executes the following steps: comparing a readout data of the flash memory under test under a writing or erasing test with an expected data output from a test pattern generator, outputting a failure signal to a failure analysis memory to store the failure data in a memory part in the failure memory in case where readout data does not coincide with an expected data, and outputting a pass signal when the readout data coincides with the expected data. The flash memory testing system has a counter for counting the number of programming pulses or erasing pulses and supplying the count data to the memory part of the failure analysis memory.
摘要翻译：闪存测试装置能够在保持常规存储器测试功能的同时测试闪存。闪速存储器测试装置获得施加到闪速存储器的每个地址的编程脉冲的数量。闪速存储器测试装置执行以下步骤：在写入或擦除测试下将被测试闪存的读出数据与从测试模式发生器输出的期望数据进行比较，将故障信号输出到故障分析存储器以存储故障在读出数据与期望数据不一致的情况下，在故障存储器的存储器部分中的数据，并且当读出数据与期望数据一致时，输出通过信号。闪存测试系统具有用于对编程脉冲或擦除脉冲的数量进行计数的计数器，并将计数数据提供给故障分析存储器的存储器部分。

115. 发明授权

US4901171A Optical tape end sensing arrangement for magnetic tape cassette 失效
标题翻译：用于磁带盒的光带末端感测装置
公开(公告)号：US4901171A
公开(公告)日：1990-02-13
申请号：US174206
申请日：1988-03-28
申请人： Kiyoshi Urayama , Shinya Sato , Yuji Iwahashi
发明人： Kiyoshi Urayama , Shinya Sato , Yuji Iwahashi
IPC分类号： G11B23/30 , G11B15/18 , G11B23/04 , G11B23/087
CPC分类号： G11B23/0875 , G11B23/08714
摘要： A tape cassette arrangement includes structures formed integrally with the cassette halves or simply fitted into the light transmission apertures. Specific embodiments of the invention include light polarizing elements which are fitted into apertures formed in the sides of the cassette, corrugations on the interior of the cassette proximate the apertures, and shielding walls which are located to block light and in particular that light which tends to enter through a large window provided in the upper surface of the cassette and through which the status of the tape is visible.

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