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111. 发明申请

US20050130454A1 METHOD FOR IMPROVING TRANSISTOR PERFORMANCE THROUGH REDUCING THE SALICIDE INTERFACE RESISTANCE 有权
标题翻译：通过减少绝缘体接触电阻来提高晶体管性能的方法
公开(公告)号：US20050130454A1
公开(公告)日：2005-06-16
申请号：US10731269
申请日：2003-12-08
申请人： Anand Murthy , Boyan Boyanov , Glenn Glass , Thomas Hoffmann
发明人： Anand Murthy , Boyan Boyanov , Glenn Glass , Thomas Hoffmann
IPC分类号： H01L21/285 , H01L21/336 , H01L29/78 , H01L21/28
CPC分类号： H01L29/7848 , H01L21/28518 , H01L21/823807 , H01L21/823814 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41725 , H01L29/6628 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7833 , H01L29/7842 , Y10S438/933
摘要： An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
摘要翻译：本发明的一个实施例通过利用用于源极和漏极区域的硅锗合金和镍硅锗自对准硅化物（即，自对准硅化物）层来形成源极和漏极区域的接触表面来降低晶体管的外部电阻。基于硅锗和硅化物之间的金属半导体功函数降低，硅锗与硅硅锗硅的界面具有较低的比接触电阻率，并且硅锗与硅中的载流子迁移率增加。可以掺杂硅锗以进一步调整其电性能。降低晶体管的外部电阻等同于在开关速度和功耗方面提高晶体管的性能。

112. 发明申请

US20050087801A1 Epitaxially deposited source/drain 有权
标题翻译：外延沉积源/漏极
公开(公告)号：US20050087801A1
公开(公告)日：2005-04-28
申请号：US10692696
申请日：2003-10-24
申请人： Nick Lindert , Anand Murthy , Justin Brask
发明人： Nick Lindert , Anand Murthy , Justin Brask
IPC分类号： H01L21/336 , H01L31/119
CPC分类号： H01L29/66628 , H01L29/66636
摘要： An epitaxially deposited source/drain extension may be formed for a metal oxide semiconductor field effect transistor. A sacrificial layer may be formed and etched away to undercut under the gate electrode. Then a source/drain extension of epitaxial silicon may be deposited to extend under the edges of the gate electrode. As a result, the extent by which the source/drain extension extends under the gate may be controlled by controlling the etching of the sacrificial material. Its thickness and depth may be controlled by controlling the deposition process. Moreover, the characteristics of the source/drain extension may be controlled independently of those of the subsequently formed deep or heavily doped source/drain junction.
摘要翻译：可以为金属氧化物半导体场效应晶体管形成外延沉积的源极/漏极延伸。可以形成牺牲层并蚀刻掉在栅电极下方的底切。然后，可以沉积外延硅的源极/漏极延伸部，以在栅电极的边缘下延伸。结果，可以通过控制牺牲材料的蚀刻来控制源极/漏极延伸在栅极下延伸的程度。其厚度和深度可以通过控制沉积过程来控制。此外，可以独立于后续形成的深度或重掺杂源极/漏极结的特性来控制源极/漏极延伸的特性。

113. 发明授权

US06703291B1 Selective NiGe wet etch for transistors with Ge body and/or Ge source/drain extensions 有权
标题翻译：具有Ge体和/或Ge源极/漏极延伸的晶体管的选择性NiGe湿法蚀刻
公开(公告)号：US06703291B1
公开(公告)日：2004-03-09
申请号：US10322390
申请日：2002-12-17
申请人： Boyan Boyanov , Steven Keating , Anand Murthy
发明人： Boyan Boyanov , Steven Keating , Anand Murthy
IPC分类号： H01L2974
CPC分类号： H01L29/665 , C23F1/26 , H01L21/28255 , H01L21/28518 , H01L21/32134 , H01L21/324
摘要： The wet etch stage of the salicide process normally used to fabricate polysilicon and silicon-based semiconductor transistors may not be appropriate for germanium-based transistors because the wet etch chemicals at such temperatures will dissolve the germanium leaving no source, gate, or drain for the transistor. In embodiments of the invention, nickel is blanket deposited over the source, drain, and gate regions of the germanium-based transistor, annealed to cause the nickel to react with the germanium, and wet etched to remove un-reacted nickel from dielectric regions (e.g., shallow trench isolation (STI) regions) but leave NiGe in the source, gate, and drain regions. The wet etch is a mild oxidizing solution at room temperature.
摘要翻译：通常用于制造多晶硅和硅基半导体晶体管的自对准硅化物工艺的湿蚀刻阶段可能不适用于基于锗的晶体管，因为在这样的温度下的湿蚀刻化学品将溶解锗，不会留下源，栅极或漏极晶体管。在本发明的实施例中，镍被覆盖地沉积在锗基晶体管的源极，漏极和栅极区域上，退火以使镍与锗反应，并进行湿式蚀刻以从电介质区域去除未反应的镍（例如浅沟槽隔离（STI）区域），而在源极，栅极和漏极区域留下NiGe。湿蚀刻在室温下是温和的氧化溶液。

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