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111. 发明授权

US08612676B2 Two-level system main memory 有权
标题翻译：二级系统主存
公开(公告)号：US08612676B2
公开(公告)日：2013-12-17
申请号：US12976545
申请日：2010-12-22
申请人： Eric J. Dahlen , Glenn J. Hinton , Raj K. Ramanujan
发明人： Eric J. Dahlen , Glenn J. Hinton , Raj K. Ramanujan
IPC分类号： G06F12/00
CPC分类号： G06F3/0611 , G06F3/0647 , G06F3/0685 , G06F11/0766 , G06F12/0246 , G06F12/0638 , G06F12/0868 , G06F12/0893 , G06F2212/1024 , G06F2212/313 , G06F2212/7203 , G06F2212/7208 , G06F2212/7209 , G06F2212/7211 , G11C14/009
摘要： Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
摘要翻译：本发明的实施例描述了包括两级存储器的系统主存储器，其包括系统盘级存储器的缓存子集。该主存储器包括包括由易失性存储器构成的存储器的“近存储器”，以及包括比近存储器更大和更慢的易失性或非易失性存储器存储器的“远存储器”。远端存储器被呈现为主机OS的“主存储器”，而近端存储器是对于对OS是透明的远存储器的高速缓存，因此与OS显示与现有技术主存储器解决方案相同的高速缓存。两级存储器的管理可以通过经由主机CPU执行的逻辑和模块的组合来完成。靠近存储器可以通过高带宽，低延迟的方式耦合到主机系统CPU，用于有效处理。远存储器可以经由低带宽，高延迟装置耦合到CPU。

112. 发明授权

US07523323B2 Method and apparatus for quick resumption 有权
标题翻译：快速恢复的方法和装置
公开(公告)号：US07523323B2
公开(公告)日：2009-04-21
申请号：US11229126
申请日：2005-09-15
申请人： Michael A. Rothman , Glenn J. Hinton , Mark S. Doran , Vincent J. Zimmer , Michael D. Kinney
发明人： Michael A. Rothman , Glenn J. Hinton , Mark S. Doran , Vincent J. Zimmer , Michael D. Kinney
IPC分类号： G06F1/00
CPC分类号： G06F1/3234 , G06F9/4418
摘要： When transitioning from sleep mode to active mode, a processing system loads first stage resume content and second stage resume content into a volatile memory of the processing system. The first stage resume content may contain contextual data for a first program that was in use before the processing system transitioned to sleep mode. The second stage resume content may contain contextual data for another program that was in use before the processing system transitioned to sleep mode. The processing system may provide a user interface for the first program before all of the second stage resume content has been loaded into the volatile memory. Other embodiments are described and claimed.
摘要翻译：当从睡眠模式转换到活动模式时，处理系统将第一级恢复内容和第二级恢复内容加载到处理系统的易失性存储器中。第一阶段恢复内容可以包含在处理系统转换到睡眠模式之前正在使用的第一程序的上下文数据。第二阶段恢复内容可以包含在处理系统转换到睡眠模式之前正在使用的另一程序的上下文数据。处理系统可以在所有第二阶段恢复内容已经被加载到易失性存储器之前为第一程序提供用户界面。描述和要求保护其他实施例。

113. 发明授权

US07480791B2 Method and apparatus for quick resumption where the system may forego initialization of at least one memory range identified in the resume descriptor 有权
标题翻译：用于快速恢复的方法和装置，其中系统可以放弃在恢复描述符中标识的至少一个存储器范围的初始化
公开(公告)号：US07480791B2
公开(公告)日：2009-01-20
申请号：US11229203
申请日：2005-09-15
申请人： Michael A. Rothman , Glenn J. Hinton , Mark S. Doran , Vincent J. Zimmer , Michael D. Kinney
发明人： Michael A. Rothman , Glenn J. Hinton , Mark S. Doran , Vincent J. Zimmer , Michael D. Kinney
IPC分类号： G06F9/00
CPC分类号： G06F9/4418
摘要： During a process of transitioning a processing system from sleep mode to active mode, system firmware of the processing system may automatically determine whether an initialization task has been assigned to a component other than system firmware, based on data obtained from a resume descriptor stored in nonvolatile storage of the processing system. The system firmware may skip the initialization task if the initialization task has been assigned to a component other than the system firmware. For example, in one embodiment, the system firmware may determine whether the resume descriptor identifies one or more memory ranges. If so, the system firmware may forego initialization of at least one memory range identified in the resume descriptor when initializing a random access memory (RAM) of the processing system. Other embodiments are described and claimed.
摘要翻译：在将处理系统从睡眠模式转换到活动模式的过程中，处理系统的系统固件可以基于从存储在非易失性存储器中的恢复描述符获得的数据自动地确定初始化任务是否已被分配给系统固件以外的组件存储处理系统。如果将初始化任务分配给系统固件以外的组件，系统固件可能会跳过初始化任务。例如，在一个实施例中，系统固件可以确定恢复描述符是否识别一个或多个存储器范围。如果是这样，当初始化处理系统的随机存取存储器（RAM）时，系统固件可以放弃在恢复描述符中标识的至少一个存储器范围的初始化。描述和要求保护其他实施例。

114. 发明授权

US07398372B2 Fusing load and alu operations 有权
标题翻译：定影负载和alu操作
公开(公告)号：US07398372B2
公开(公告)日：2008-07-08
申请号：US10180391
申请日：2002-06-25
申请人： Nicholas G. Samra , Stephan J. Jourdan , David J. Sager , Glenn J. Hinton
发明人： Nicholas G. Samra , Stephan J. Jourdan , David J. Sager , Glenn J. Hinton
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3017 , G06F9/3853
摘要： Fusing a load micro-operation (uop) together with an arithmetic uop. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in a cache memory, un-fused, executed in parallel, and retired in order to optimized cost and performance.
摘要翻译：将负载微操作（uop）与算术空间融合。内部指令融合可以在微处理器内提高高速缓冲存储器存储效率和计算机指令处理带宽，而不会导致重大的计算机系统成本。 Uops被融合，存储在缓存中，未融合，并行执行并退出，以优化成本和性能。

115. 发明授权

US06735688B1 Processor having replay architecture with fast and slow replay paths 有权
标题翻译：具有重放架构的处理器具有快速和慢速的重放路径
公开(公告)号：US06735688B1
公开(公告)日：2004-05-11
申请号：US09503853
申请日：2000-02-14
申请人： Michael D. Upton , David J. Sager , Darrell Boggs , Glenn J. Hinton
发明人： Michael D. Upton , David J. Sager , Darrell Boggs , Glenn J. Hinton
IPC分类号： G06F900
CPC分类号： G06F9/3865 , G06F9/3824 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： According to one aspect of the invention, a microprocessor is provided that includes an execution core, a first replay mechanism and a second replay mechanism. The execution core performs data speculation in executing a first instruction. The first replay mechanism is used to replay the first instruction via a first replay path if an error of a first type is detected which indicates that the data speculation is erroneous. The second replay mechanism is used to replay the first instruction via a second replay path if an error of a second type is detected which indicates that the data speculation is erroneous.
摘要翻译：根据本发明的一个方面，提供一种包括执行核心，第一重放机制和第二重放机构的微处理器。执行核心在执行第一条指令时执行数据推测。如果检测到第一类型的错误，指示数据猜测是错误的，则第一重放机制用于经由第一重放路径重放第一指令。如果检测到第二类型的错误，指示数据猜测是错误的，则第二重播机制用于经由第二重放路径重播第一指令。

116. 发明授权

US06687810B2 Method and apparatus for staggering execution of a single packed data instruction using the same circuit 有权
标题翻译：用于使用相同电路交错执行单个打包数据指令的方法和装置
公开(公告)号：US06687810B2
公开(公告)日：2004-02-03
申请号：US10164976
申请日：2002-06-06
申请人： Patrice Roussel , Glenn J. Hinton , Shreekant S. Thakkar , Brent R. Boswell , Karol F. Menezes
发明人： Patrice Roussel , Glenn J. Hinton , Shreekant S. Thakkar , Brent R. Boswell , Karol F. Menezes
IPC分类号： G06F1500
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3826 , G06F9/3828 , G06F9/3875 , G06F9/3885
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
摘要翻译：公开了一种用于交错执行指令的方法和装置。根据本发明的一个实施例，接收单个宏指令，其中单个宏指令指定至少两个逻辑寄存器，并且其中两个逻辑寄存器分别存储具有相应数据元素的第一和第二压缩数据操作数。然后，使用相同的电路，在来自所述第一和第二打包数据操作数的第一和第二多个相应数据元素上独立地执行由单个宏指令指定的操作，以独立地生成第一和第二多个结果数据元素。第一和第二多个结果数据元素作为第三打包数据操作数存储在单个逻辑寄存器中。

117. 发明授权

US06216234B1 Processor having execution core sections operating at different clock rates 失效
标题翻译：具有执行核心部分以不同时钟速率工作的处理器
公开(公告)号：US06216234B1
公开(公告)日：2001-04-10
申请号：US09092353
申请日：1998-06-05
申请人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
发明人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
IPC分类号： G06F104
CPC分类号： G06F9/3842 , G06F1/08 , G06F9/30145 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3863 , G06F9/3869 , G06F15/7832
摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
摘要翻译：一种处理器，包括以第一时钟频率执行执行操作的第一执行核心部分和第二执行核心部分，其被计时以在与第一时钟频率不同的第二时钟频率执行执行操作。第二个执行核心部分运行速度更快，包括数据高速缓存和关键的ALU功能，而第一个执行核心部分包括延迟容忍功能，如指令提取和解码单元以及非关键ALU功能。处理器还可以包括可能仍然比第一执行核心部分慢的I / O环。可选地，第一执行核心部分可以包括其时钟速率在第一执行核心部分和第二执行核心部分之间的第三执行核心部分。可以在各部分之间使用时钟乘法器/分频器，以从单个源（例如I / O时钟）导出其时钟。

118. 发明授权

US06105111A Method and apparatus for providing a cache management technique 失效
标题翻译：用于提供高速缓存管理技术的方法和装置
公开(公告)号：US06105111A
公开(公告)日：2000-08-15
申请号：US53527
申请日：1998-03-31
申请人： Per H. Hammarlund , Glenn J. Hinton
发明人： Per H. Hammarlund , Glenn J. Hinton
IPC分类号： G06F12/12 , G06F12/00
CPC分类号： G06F12/123
摘要： A cache technique for maximizing cache efficiency by assigning ages to elements which access the cache, is described. In one embodiment, the cache technique includes receiving a first element of a first type by a cache and writing the first element in a set of the cache. The first element has a first age. The cache technique further includes receiving a second element of a second type by the cache and writing the second element in the set of the cache. The second element has a middle age, where the first age is a more recently used age than the middle age. In another embodiment, the cache technique includes receiving a first element of a first stream by a cache and writing the first element in a set of the cache. The first element has a first age. The cache technique further includes receiving a second element of a second stream by the cache and writing the second element in the set of the cache. The second element has a middle age, where the first age is a more recently used age than the middle age.
摘要翻译：描述了通过将访问高速缓存的元素分配年龄来最大化高速缓存效率的高速缓存技术。在一个实施例中，高速缓存技术包括通过高速缓存接收第一类型的第一元素并将第一元素写入高速缓存的集合。第一个元素有第一个年龄。高速缓存技术还包括由高速缓存接收第二类型的第二元素，并将第二元素写入高速缓存的集合。第二个元素有一个中年，第一个年龄是比中年更近的年龄。在另一个实施例中，高速缓存技术包括由高速缓存接收第一流的第一元素，并将第一元素写入高速缓存的集合。第一个元素有第一个年龄。高速缓存技术还包括由高速缓存接收第二流的第二元素，并将第二元素写入高速缓存的集合。第二个元素有一个中年，第一个年龄是比中年更近的年龄。

119. 发明授权

US5828868A Processor having execution core sections operating at different clock rates 失效
公开(公告)号：US5828868A
公开(公告)日：1998-10-27
申请号：US746606
申请日：1996-11-13
申请人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
发明人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
IPC分类号： G06F1/08 , G06F9/30 , G06F9/38 , G06F15/78 , G06F1/06
CPC分类号： G06F9/3842 , G06F1/08 , G06F15/7832 , G06F9/30145 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3863 , G06F9/3869
摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

120. 发明授权

US5689674A Method and apparatus for binding instructions to dispatch ports of a reservation station 失效
标题翻译：用于绑定指令以分配保留站的端口的方法和装置
公开(公告)号：US5689674A
公开(公告)日：1997-11-18
申请号：US550745
申请日：1995-10-31
申请人： James S. Griffith , Shantanu R. Gupta , Glenn J. Hinton
发明人： James S. Griffith , Shantanu R. Gupta , Glenn J. Hinton
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for binding instructions to dispatch ports in a reservation station includes a counter mechanism and a port identifier. The counter mechanism maintains a count of instructions which are pending dispatch from at least one of the dispatch ports. The port identifier receives an instruction and identifies to which of the dispatch ports the instruction is to be bound, based on the count of instructions maintained by the counter mechanism.
摘要翻译：用于绑定指令以在保留站中分派端口的方法和装置包括计数器机制和端口标识符。计数器机构保持正在从至少一个调度端口发送的指令的计数。端口标识符基于由计数器机制保持的指令的计数，接收指令并且识别指令将被绑定到哪个调度端口。

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