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111. 发明授权

US6034877A Semiconductor memory array having sublithographic spacing between adjacement trenches and method for making the same 失效
标题翻译：具有辅助沟槽之间的亚光刻间隔的半导体存储器阵列及其制造方法
公开(公告)号：US6034877A
公开(公告)日：2000-03-07
申请号：US93902
申请日：1998-06-08
申请人： Gary Bela Bronner , Jack Allan Mandelman , Donald James Samuels
发明人： Gary Bela Bronner , Jack Allan Mandelman , Donald James Samuels
IPC分类号： H01L21/8242 , G11C11/24
CPC分类号： H01L27/1087
摘要： Disclosed herein is an arrangement of memory cells in which the spacing between back-to-back trench capacitors is defined at less than 1 F spacing. A pure phase edge mask is used to define such trench patterns having less than 1 F spacing. The reduction in the trench-to-trench spacing results in increased separation between the trench and the near edge of the gate conductor. This increase in the trench to gate conductor spacing, in turn, permits the channel doping concentration to be decreased, with a corresponding increase in ON current to be realized. In alternative embodiments, a pure phase edge mask or a blocked phase edge mask can be used to define trench patterns in which the width of trenches is increased to form storage capacitors having higher capacitance. In such embodiments, the spacing between back-to-back trenches can be reduced, such that the total separation between the outer edges of adjacent trenches is maintained at about 3 F or less.
摘要翻译：本文公开了一种存储单元的布置，其中背对背沟槽电容器之间的间隔被限定在小于1F的间隔。使用纯相边缘掩模来限定具有小于1F间距的这种沟槽图案。沟槽间距的减小导致沟槽和栅极导体的近边缘之间的间隔增加。沟槽与栅极导体间隔的增加又使得沟道掺杂浓度降低，同时实现ON电流的相应增加。在替代实施例中，可以使用纯相边缘掩模或阻挡相边缘掩模来限定其中沟槽宽度增加以形成具有较高电容的存储电容器的沟槽图案。在这样的实施例中，可以减小背对背沟槽之间的间隔，使得相邻沟槽的外边缘之间的总间隔保持在约3°F或更小。

112. 发明授权

US5793075A Deep trench cell capacitor with inverting counter electrode 失效
标题翻译：具有反相对电极的深沟槽电容器
公开(公告)号：US5793075A
公开(公告)日：1998-08-11
申请号：US688345
申请日：1996-07-30
申请人： Johann Alsmeier , Jack Allan Mandelman , James Anthony O'Neill , Christopher Parks , Paul Christian Parries
发明人： Johann Alsmeier , Jack Allan Mandelman , James Anthony O'Neill , Christopher Parks , Paul Christian Parries
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10829
摘要： The preferred embodiment provides an integrated circuit capacitor that achieves a high capacitance by using an inversion layer in the substrate as the plate counter electrode for the capacitor. The inversion layer is created by forming a trench capacitor in a lightly doped substrate. With a sufficient workfunction difference between the storage node material and the isolation band the surface of the lightly doped substrate inverts, with the inversion charge being supplied by the isolation band. This inversion layer serves as the plate counter electrode for the capacitor.
摘要翻译：优选实施例提供一种集成电路电容器，其通过使用基板中的反转层作为用于电容器的板对电极来实现高电容。通过在轻掺杂衬底中形成沟槽电容器来产生反型层。在存储节点材料和隔离带之间具有足够的功函数差异时，轻掺杂衬底的表面反转，反转电荷由隔离带提供。该反转层用作电容器的板对置电极。

113. 发明授权

US5789276A Optical FET 失效
公开(公告)号：US5789276A
公开(公告)日：1998-08-04
申请号：US569823
申请日：1995-12-08
申请人： James Marc Leas , Jack Allan Mandelman
发明人： James Marc Leas , Jack Allan Mandelman
IPC分类号： H01L25/04 , H01L31/112 , H01L21/00 , H01L2/336
CPC分类号： H01L25/043 , H01L31/1126 , H01L2924/0002
摘要： An optical FET includes one or more light-responsive diodes stacked on the gate. Each diode includes a planar (horizontal) junction. The number of diodes is chosen to achieve a desired gate to source potential difference. An electrical connection connects the diode(s) to the source of the FET.

114. 发明授权

US08772876B2 High-voltage silicon-on-insulator transistors and methods of manufacturing the same 失效
标题翻译：高压硅绝缘体晶体管及其制造方法
公开(公告)号：US08772876B2
公开(公告)日：2014-07-08
申请号：US11929694
申请日：2007-10-30
申请人： William Hsioh-Lien Ma , Jack Allan Mandelman , Carl John Radens , William Robert Tonti
发明人： William Hsioh-Lien Ma , Jack Allan Mandelman , Carl John Radens , William Robert Tonti
IPC分类号： H01L23/62
CPC分类号： H01L29/66772 , H01L29/78612 , H01L29/78624 , H01L2924/0002 , H01L2924/00
摘要： In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer. A portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了制造高压晶体管的第一种方法。第一种方法包括以下步骤：（1）提供包括在绝缘体上硅（SOI）层之下的绝缘体层下面的体硅层的衬底; 以及（2）形成包括SOI层中的晶体管的扩散区域的晶体管节点的一个或多个部分。晶体管节点的一部分适于将晶体管内的大于约5V的电压减小到小于约3V的电压。提供了许多其它方面。

115. 发明授权

US07928436B2 Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods 有权
标题翻译：使用多孔层形成绝缘体上半导体结构的方法和通过这些方法形成的半导体结构的方法
公开(公告)号：US07928436B2
公开(公告)日：2011-04-19
申请号：US12120455
申请日：2008-05-14
申请人： Kangguo Cheng , Brian Joseph Greene , Jack Allan Mandelman
发明人： Kangguo Cheng , Brian Joseph Greene , Jack Allan Mandelman
IPC分类号： H01L29/04 , H01L29/10
CPC分类号： H01L21/76251 , H01L21/76245 , Y10S438/933
摘要： A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.
摘要翻译：一种半导体结构，其包括单晶含锗层，优选基本上纯的锗，衬底和将锗含量层与衬底分离的掩埋绝缘体层。在基板上形成可以是多孔硅的多孔层，在多孔硅层上形成含锗层。多孔层可以转化成一层氧化物，这提供了埋层绝缘体层。或者，含锗层可以从多孔层转移到另一衬底上的绝缘层。在转移之后，绝缘层被埋在后面的衬底和含锗层之间。

116. 发明授权

US07791145B2 Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures 有权
标题翻译：用于闭锁抑制的半导体结构和形成这种半导体结构的方法
公开(公告)号：US07791145B2
公开(公告)日：2010-09-07
申请号：US11764571
申请日：2007-06-18
申请人： Toshiharu Furukawa , Robert J. Gauthier, Jr. , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
发明人： Toshiharu Furukawa , Robert J. Gauthier, Jr. , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L27/092
CPC分类号： H01L21/76237 , H01L21/26533 , H01L21/76213 , H01L21/76229 , H01L21/76232 , H01L21/823878 , H01L27/0921 , H01L29/1087 , H01L29/78
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.
摘要翻译：用于抑制大量CMOS器件中的闩锁的半导体结构和方法。该半导体结构包括成形修饰的隔离区，其形成在通常在制造本体CMOS器件的衬底的两个掺杂阱之间的沟槽中。成形改进的隔离区域可以包括沟槽的加宽的电介质填充部分，其可以可选地包括分隔两个掺杂阱之间的损伤区域的沟槽的附近损伤区域或狭窄的电介质填充部分。也可以通过在沟槽中的沟槽基底和介电填料之间提供晶格不匹配的层来抑制闩锁。

117. 发明授权

US07790527B2 High-voltage silicon-on-insulator transistors and methods of manufacturing the same 失效
标题翻译：高压硅绝缘体晶体管及其制造方法
公开(公告)号：US07790527B2
公开(公告)日：2010-09-07
申请号：US11347413
申请日：2006-02-03
申请人： William Hsioh-Lien Ma , Jack Allan Mandelman , Carl John Radens , William Robert Tonti
发明人： William Hsioh-Lien Ma , Jack Allan Mandelman , Carl John Radens , William Robert Tonti
IPC分类号： H01L21/84
CPC分类号： H01L29/66772 , H01L29/78612 , H01L29/78624 , H01L2924/0002 , H01L2924/00
摘要： In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer. A portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了制造高压晶体管的第一种方法。第一种方法包括以下步骤：（1）提供包括在绝缘体上硅（SOI）层之下的绝缘体层下面的体硅层的衬底; 以及（2）形成包括SOI层中的晶体管的扩散区域的晶体管节点的一个或多个部分。晶体管节点的一部分适于将晶体管内的大于约5V的电压减小到小于约3V的电压。提供了许多其它方面。

118. 发明授权

US07737504B2 Well isolation trenches (WIT) for CMOS devices 失效
标题翻译：用于CMOS器件的隔离沟槽（WIT）
公开(公告)号：US07737504B2
公开(公告)日：2010-06-15
申请号：US11759981
申请日：2007-06-08
申请人： Toshiharu Furukawa , Mark Charles Hakey , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
发明人： Toshiharu Furukawa , Mark Charles Hakey , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L29/772
CPC分类号： H01L21/823892 , H01L21/76229 , H01L21/823878 , H01L27/11
摘要： A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.
摘要翻译： CMOS器件的良好隔离沟槽及其形成方法。 CMOS器件包括（a）半导体衬底，（b）半导体衬底中的P阱和N阱，（c）夹在P阱和N阱之间并与P阱和N阱直接物理接触的阱隔离区域。 P阱包括第一浅沟槽隔离（STI）区域，并且N阱包括第二STI区域。阱隔离区域的底表面处于比第一和第二STI区域的底表面更低的水平面。当从隔离区域的顶部到底部进行时，阱隔离区域的水平横截面的区域是基本上连续的函数。

119. 发明授权

US07655985B2 Methods and semiconductor structures for latch-up suppression using a conductive region 失效
公开(公告)号：US07655985B2
公开(公告)日：2010-02-02
申请号：US12125381
申请日：2008-05-22
申请人： Toshiharu Furukawa , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
发明人： Toshiharu Furukawa , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L27/0921 , H01L21/823878 , H01L29/78
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.

120. 发明授权

US07651902B2 Hybrid substrates and methods for forming such hybrid substrates 失效
标题翻译：混合基板和形成这种混合基板的方法
公开(公告)号：US07651902B2
公开(公告)日：2010-01-26
申请号：US11737989
申请日：2007-04-20
申请人： Ethan Harrison Cannon , Toshiharu Furukawa , John Gerard Gaudiello , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
发明人： Ethan Harrison Cannon , Toshiharu Furukawa , John Gerard Gaudiello , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L21/338 , H01L23/62
CPC分类号： H01L21/76243 , H01L21/76251 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.
摘要翻译：以不同晶体取向的半导体岛为特征的混合基板和形成这种混合基板的方法。该方法涉及使用SIMOX工艺来形成绝缘层。绝缘层可以将不同晶体取向中的至少一个的岛分成相互排列的器件和体区。身体区域可以相对于装置区域电浮动。

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