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111. 发明授权

US5844849A Dynamic semiconductor memory device having fast operation mode and operating with low current consumption 失效
标题翻译：动态半导体存储器件具有快速运行模式，低电流运行
公开(公告)号：US5844849A
公开(公告)日：1998-12-01
申请号：US878076
申请日：1997-06-18
申请人： Kiyohiro Furutani
发明人： Kiyohiro Furutani
IPC分类号： G11C11/401 , G11C7/10 , G11C7/22 , G11C8/18 , G11C11/409 , G11C7/00
CPC分类号： G11C7/1069 , G11C7/1033 , G11C7/1045 , G11C7/1051 , G11C7/1072 , G11C7/22 , G11C8/18
摘要： A semiconductor memory device includes a delay stage for delaying a row address strobe signal ZRAS by a predetermined time, a first signal generating circuit for generating a signal instructing activation/precharge of an array in accordance with the row address strobe signal ZRAS, and a second signal generating circuit for generating a signal setting the output stage to an output high impedance state in accordance with a delayed row address strobe signal ZRAS from the delay stage and a column address strobe signal ZCAS. Even if both the column address strobe signal and row address strobe signal may be simultaneously set to the high and low levels, respectively, the column address strobe signal and the delayed row address strobe signal are not simultaneously set to the high level, so that the output stage is prevented from attaining the high impedance state, and data output is allowed. Therefore, the semiconductor memory device can operate fast with a low current consumption.
摘要翻译：半导体存储器件包括用于将行地址选通信号ZRAS延迟预定时间的延迟级，用于根据行地址选通信号ZRAS产生指示阵列的激活/预充电的信号的第一信号产生电路，以及第二信号发生电路，用于根据来自延迟级的延迟行地址选通信号ZRAS和列地址选通信号ZCAS产生将输出级设置为输出高阻抗状态的信号。即使列地址选通信号和行地址选通信号都可以分别同时设置为高电平和低电平，列地址选通信号和延迟行地址选通信号也不会同时设置为高电平，防止输出级达到高阻态，允许数据输出。因此，半导体存储器件可以以低电流消耗快速运行。

112. 发明授权

US5841705A Semiconductor memory device having controllable supplying capability of internal voltage 失效
公开(公告)号：US5841705A
公开(公告)日：1998-11-24
申请号：US924501
申请日：1997-09-05
申请人： Takeshi Hamamoto , Kiyohiro Furutani , Yoshikazu Morooka
发明人： Takeshi Hamamoto , Kiyohiro Furutani , Yoshikazu Morooka
IPC分类号： G11C11/407 , G11C5/14 , G11C11/403 , G11C11/406 , G11C11/4074 , G11C11/408 , G11C11/409 , G11C13/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C11/4074 , G11C5/146
摘要： When an external RAS and external CAS are input to a RAS buffer and a CAS buffer, an internal RAS and an internal CAS are generated. The internal RAS is input to a clock generating circuit and a CBR mode determination circuit and the internal CAS is input to the CBR mode determination circuit. The clock generating circuit outputs a pump clock to first and second WL pumps upon input of internal RAS, and the first WL pump supplies charge to a Vpp power supply. If CAS is input prior to RAS during refresh operation, CBR mode determination circuit inputs a CBR mode signal to the second WL pump which supplies charge to Vpp power supply together with the first WL pump when the pump clock and the CBR mode signal is input thereto.

113. 发明授权

US5796287A Output driver circuit for suppressing noise generation and integrated circuit device for burn-in test 失效
标题翻译：用于抑制噪声产生的输出驱动电路和用于老化测试的集成电路器件
公开(公告)号：US5796287A
公开(公告)日：1998-08-18
申请号：US145710
申请日：1993-11-04
申请人： Kiyohiro Furutani , Hideyuki Ozaki
发明人： Kiyohiro Furutani , Hideyuki Ozaki
IPC分类号： G01R31/28 , G11C7/10 , G11C29/50 , H03G11/04 , H03K5/01 , H03K5/13 , H03K19/003 , H03K19/0185 , H03K17/04
CPC分类号： H03K19/018585 , G01R31/2879 , G11C29/50 , G11C7/1051 , G11C7/1057 , H03G11/04 , H03K19/00361 , H03K5/01 , H03K5/133 , G01R31/2856 , G11C11/401
摘要： An improved output driver circuit for a semiconductor integrated circuit device is provided. The output driver circuit receives a type select signal (.phi.1,/.phi.1) determined by bonding selection. When a heavy load circuit is connected to an output terminal (DQ), a signal (.phi.1) of low level and a signal (/.phi.1) of high level are provided, whereby transistors (18, 19) are turned on simultaneously in response to a data signal (Mo). When a light load circuit is connected to the terminal (DQ), a signal (.phi.1) of high level and a signal (/.phi.1) of low level are provided, whereby transistors (18, 19) are turned on at a different timing. More specifically, following charging of a light load by a transistor (18) having low mutual conductance, a transistor (19) is turned on. Therefore, noise generation can be flexibly suppressed by bonding selection.
摘要翻译：提供了一种用于半导体集成电路器件的改进的输出驱动器电路。输出驱动器电路接收通过键合选择确定的类型选择信号（phi 1，/ phi 1）。当重负载电路连接到输出端（DQ）时，提供低电平的信号（phi 1）和高电平的信号（/ phi 1），由此晶体管（18,19）同时导通对数据信号（Mo）的响应。当轻负载电路连接到端子（DQ）时，提供高电平的信号（phi 1）和低电平的信号（/ phi 1），由此晶体管（18,19）以不同的方式导通定时。更具体地，在通过具有低互导性的晶体管（18）对轻负载充电之后，晶体管（19）导通。因此，可以通过接合选择灵活地抑制噪声产生。

114. 发明授权

US5757228A Output driver circuit for suppressing noise generation and integrated circuit device for burn-in test 失效
标题翻译：用于抑制噪声产生的输出驱动电路和用于老化测试的集成电路器件
公开(公告)号：US5757228A
公开(公告)日：1998-05-26
申请号：US792127
申请日：1997-01-31
申请人： Kiyohiro Furutani , Hideyuki Ozaki
发明人： Kiyohiro Furutani , Hideyuki Ozaki
IPC分类号： G01R31/28 , G11C7/10 , G11C29/50 , H03G11/04 , H03K5/01 , H03K5/13 , H03K19/003 , H03K19/0185 , G05F1/10
CPC分类号： H03K19/018585 , G01R31/2879 , G11C29/50 , G11C7/1051 , G11C7/1057 , H03G11/04 , H03K19/00361 , H03K5/01 , H03K5/133 , G01R31/2856 , G11C11/401
摘要： An improved output driver circuit for a semiconductor integrated circuit device is provided. The output driver circuit receives a type select signal (.phi.1, /.phi.1) determined by bonding selection. When a heavy load circuit is connected to an output terminal (DQ), a signal (.phi.1) of low level and a signal (/.phi.1) of high level are provided, whereby transistors (18, 19) are turned on simultaneously in response to a data signal (Mo). When a light load circuit is connected to the terminal (DQ), a signal (.phi.1) of high level and a signal (/.phi.1) of low level are provided, whereby transistors (18, 19) are turned on at a different timing. More specifically, following charging of a light load by a transistor (18) having low mutual conductance, a transistor (19) is turned on. Therefore, noise generation can be flexibly suppressed by bonding selection.
摘要翻译：提供了一种用于半导体集成电路器件的改进的输出驱动器电路。输出驱动器电路接收通过键合选择确定的类型选择信号（phi 1，/ phi 1）。当重负载电路连接到输出端（DQ）时，提供低电平的信号（phi 1）和高电平的信号（/ phi 1），由此晶体管（18,19）同时导通对数据信号（Mo）的响应。当轻负载电路连接到端子（DQ）时，提供高电平的信号（phi 1）和低电平的信号（/ phi 1），由此晶体管（18,19）以不同的方式导通定时。更具体地，在通过具有低互导性的晶体管（18）对轻负载充电之后，晶体管（19）导通。因此，可以通过接合选择灵活地抑制噪声产生。

115. 发明授权

US5729502A Semiconductor memory device that can read out data at high speed 失效
公开(公告)号：US5729502A
公开(公告)日：1998-03-17
申请号：US775762
申请日：1996-12-31
申请人： Kiyohiro Furutani , Hiroshi Miyamoto
发明人： Kiyohiro Furutani , Hiroshi Miyamoto
IPC分类号： G11C11/401 , G11C7/22 , G11C11/4076 , G11C11/409 , G11C11/4093 , G11C11/4096 , G11C8/00
CPC分类号： G11C11/4093 , G11C11/4076 , G11C11/4096 , G11C7/22
摘要： A .phi..sub.C generation circuit provides a column address buffer control signal to a column address buffer so that the column address buffer maintains a latch operation during the operation period of a differential amplifier. The column address buffer responds to a column address buffer control signal to latch an input address signal for providing a column address signal to a .phi..sub.D and PAE generation circuit. The .phi..sub.D and PAE generation circuit provides a differential amplifier activation signal to the differential amplifier according to a column address signal and a column access activation signal. The differential amplifier responds to a differential amplifier activation signal for amplifying data applied from a data input and output line to provide the same to a selector via a readout data line.

116. 发明授权

US5673231A Semiconductor memory device in which leakage current from defective memory cell can be suppressed during standby 失效
标题翻译：在备用期间能够抑制来自有缺陷的存储单元的漏电流的半导体存储器件
公开(公告)号：US5673231A
公开(公告)日：1997-09-30
申请号：US668169
申请日：1996-06-21
申请人： Kiyohiro Furutani
发明人： Kiyohiro Furutani
IPC分类号： G11C11/401 , G11C11/409 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/50 , G11C7/00
CPC分类号： G11C29/78 , G11C29/02 , G11C29/025 , G11C29/50 , G11C11/401 , G11C2029/5006
摘要： A bit line precharge potential supply interconnection and a bit line pair are connected via N channel MOS transistors in which the gate potentials are controlled by an equalizing signal and a P channel MOS transistor which is in connection with the connection point of N channel MOS transistors. The P channel MOS transistor has its gate connected to a column selecting line. When there is a failure due to short-circuit between a bit line and a word line, the column selecting line is set such that it would be at "H" level during the standby period by disconnecting a fuse element. Accordingly, the connection between the bit line pair and the precharge potential supply interconnection is cut off during the standby period, preventing generation of leakage current and thus suppressing increase in power consumption.
摘要翻译：位线预充电电源互连和位线对通过N沟道MOS晶体管连接，其中栅极电位由均衡信号控制，P沟道MOS晶体管与N沟道MOS晶体管的连接点相连。 P沟道MOS晶体管的栅极连接到列选择线。当由于位线和字线之间的短路而发生故障时，列选择线被设置为在待机期间通过断开熔丝元件将处于“H”电平。因此，在待机期间，位线对与预充电电源互连之间的连接被切断，防止漏电流的产生，从而抑制功耗的增加。

117. 发明授权

US5668774A Dynamic semiconductor memory device having fast operation mode and operating with low current consumption 失效
标题翻译：动态半导体存储器件具有快速运行模式，低电流运行
公开(公告)号：US5668774A
公开(公告)日：1997-09-16
申请号：US651025
申请日：1996-05-21
申请人： Kiyohiro Furutani
发明人： Kiyohiro Furutani
IPC分类号： G11C11/401 , G11C7/10 , G11C7/22 , G11C8/18 , G11C11/409 , G11C8/00
CPC分类号： G11C7/1069 , G11C7/1033 , G11C7/1045 , G11C7/1051 , G11C7/1072 , G11C7/22 , G11C8/18
摘要： A semiconductor memory device includes a delay stage for delaying a row address strobe signal ZRAS by a predetermined time, a first signal generating circuit for generating a signal instructing activation/precharge of an array in accordance with the row address strobe signal ZRAS, and a second signal generating circuit for generating a signal setting the output stage to an output high impedance state in accordance with a delayed row address strobe signal ZRAS from the delay stage and a column address strobe signal ZCAS. Even if both the column address strobe signal and row address strobe signal may be simultaneously set to the high and low levels, respectively, the column address strobe signal and the delayed row address strobe signal are not simultaneously set to the high level, so that the output stage is prevented from attaining the high impedance state, and data output is allowed. Therefore, the semiconductor memory device can operate fast with a low current consumption.
摘要翻译：半导体存储器件包括用于将行地址选通信号ZRAS延迟预定时间的延迟级，用于根据行地址选通信号ZRAS产生指示阵列的激活/预充电的信号的第一信号产生电路，以及第二信号发生电路，用于根据来自延迟级的延迟行地址选通信号ZRAS和列地址选通信号ZCAS产生将输出级设置为输出高阻抗状态的信号。即使列地址选通信号和行地址选通信号都可以分别同时设置为高电平和低电平，列地址选通信号和延迟行地址选通信号也不会同时设置为高电平，防止输出级达到高阻态，允许数据输出。因此，半导体存储器件可以以低电流消耗快速运行。

118. 发明授权

US5640363A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5640363A
公开(公告)日：1997-06-17
申请号：US542958
申请日：1995-10-13
申请人： Kiyohiro Furutani , Tadaaki Yamauchi , Makiko Aoki
发明人： Kiyohiro Furutani , Tadaaki Yamauchi , Makiko Aoki
IPC分类号： G11C11/41 , G11C7/12 , G11C7/22 , G11C11/407 , G11C11/409 , G11C7/00
CPC分类号： G11C7/12 , G11C7/22
摘要： The present invention semiconductor memory device includes common signal lines from which memory cell data is read and an amplifier for detecting a potential difference between these common signal lines, wherein equalization of the common signal lines is started when a potential difference required for an operation of the amplifier is generated on the common signal lines.Also, a semiconductor memory device having a plurality of memory cell arrays includes first common signal lines for reading memory cell data and second common signal lines having the first common signal lines connected thereto. The first common signal lines are operated in an activated state only after a writing operation, whereby access time of the semiconductor device can be shortened.
摘要翻译：本发明的半导体存储器件包括从其读取存储单元数据的公共信号线和用于检测这些公共信号线之间的电位差的放大器，其中当所述公共信号线的操作所需的电位差在公共信号线上产生放大器。此外，具有多个存储单元阵列的半导体存储器件包括用于读取存储单元数据的第一公共信号线和与其连接的第一公共信号线的第二公共信号线。第一公共信号线仅在写入操作之后才被激活，从而可以缩短半导体器件的访问时间。

119. 发明授权

US5621348A Output driver circuit for suppressing noise generation and integrated circuit device for burn-in test 失效
标题翻译：用于抑制噪声产生的输出驱动电路和用于老化测试的集成电路器件
公开(公告)号：US5621348A
公开(公告)日：1997-04-15
申请号：US447587
申请日：1995-05-23
申请人： Kiyohiro Furutani , Hideyuki Ozaki
发明人： Kiyohiro Furutani , Hideyuki Ozaki
IPC分类号： G01R31/28 , G11C7/10 , G11C29/50 , H03G11/04 , H03K5/01 , H03K5/13 , H03K19/003 , H03K19/0185 , G05F1/10
CPC分类号： H03K19/018585 , G01R31/2879 , G11C29/50 , G11C7/1051 , G11C7/1057 , H03G11/04 , H03K19/00361 , H03K5/01 , H03K5/133 , G01R31/2856 , G11C11/401
摘要： An improved output driver circuit for a semiconductor integrated circuit device is provided. The output driver circuit receives a type select signal (.phi.1, /.phi.1) determined by bonding selection. When a heavy load circuit is connected to an output terminal (DQ), a signal (.phi.1) of low level and a signal (/.phi.1) of high level are provided, whereby transistors (18, 19) are turned on simultaneously in response to a data signal (Mo). When a light load circuit is connected to the terminal (DQ), a signal (.phi.1) of high level and a signal (/.phi.1) of low level are provided, whereby transistors (18, 19) are turned on at a different timing. More specifically, following charging of a light load by a transistor (18) having low mutual conductance, a transistor (19) is turned on. Therefore, noise generation can be flexibly suppressed by bonding selection.
摘要翻译：提供了一种用于半导体集成电路器件的改进的输出驱动器电路。输出驱动器电路接收通过键合选择确定的类型选择信号（phi 1，/ phi 1）。当重负载电路连接到输出端（DQ）时，提供低电平的信号（phi 1）和高电平的信号（/ phi 1），由此晶体管（18,19）同时导通对数据信号（Mo）的响应。当轻负载电路连接到端子（DQ）时，提供高电平的信号（phi 1）和低电平的信号（/ phi 1），由此晶体管（18,19）以不同的方式导通定时。更具体地，在通过具有低互导性的晶体管（18）对轻负载充电之后，晶体管（19）导通。因此，可以通过接合选择灵活地抑制噪声产生。

120. 发明授权

US5487043A Semiconductor memory device having equalization signal generating circuit 失效
标题翻译：具有均衡信号发生电路的半导体存储器件
公开(公告)号：US5487043A
公开(公告)日：1996-01-23
申请号：US306098
申请日：1994-09-14
申请人： Kiyohiro Furutani , Tadaaki Yamauchi , Makiko Aoki
发明人： Kiyohiro Furutani , Tadaaki Yamauchi , Makiko Aoki
IPC分类号： G11C11/41 , G11C7/12 , G11C7/22 , G11C11/407 , G11C11/409 , G11C7/00
CPC分类号： G11C7/12 , G11C7/22
摘要： The present invention semiconductor memory device includes common signal lines from which memory cell data is read and an amplifier for detecting a potential difference between these common signal lines, wherein equalization of the common signal lines is started when a potential difference required for an operation of the amplifier is generated on the common signal lines. Also, a semiconductor memory device having a plurality of memory cell arrays includes first common signal lines for reading memory cell data and second common signal lines having the first common signal lines connected thereto. The first common signal lines are operated in an activated state only after a writing operation, whereby access time of the semiconductor device can be shortened.
摘要翻译：本发明的半导体存储器件包括从其读取存储单元数据的公共信号线和用于检测这些公共信号线之间的电位差的放大器，其中当所述公共信号线的操作所需的电位差在公共信号线上产生放大器。此外，具有多个存储单元阵列的半导体存储器件包括用于读取存储单元数据的第一公共信号线和与其连接的第一公共信号线的第二公共信号线。第一公共信号线仅在写入操作之后才被激活，从而可以缩短半导体器件的访问时间。

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