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111. 发明授权

US07434074B2 Logic circuit system and method of changing operating voltage of a programmable logic circuit 失效
公开(公告)号：US07434074B2
公开(公告)日：2008-10-07
申请号：US11778389
申请日：2007-07-16
申请人： Taku Ohneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
发明人： Taku Ohneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3243 , G06F1/3296 , H03K19/0008 , H03K19/0016 , H03K19/1736 , H03K19/17752 , H03K19/17756 , H03K19/17784 , H03K19/17788 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： A logic circuit system with power consumption that is reduced by automatically varying the clock frequency and operating voltage according to processing capability imposed on programmable logic circuits. The programmable logic circuits are capable of achieving plural circuit functions dynamically and can change realized circuit functions during operation. In addition, the system has a voltage supply portion for supplying a voltage to the programmable logic circuits, a clock signal supply portion for supplying a clock signal to the programmable logic circuits, a change control portion for changing the circuit functions realized by the programmable logic circuits to any one of the circuit functions, an operation time measuring portion for measuring the operation times of the programmable logic circuits to perform processing to achieve the circuit functions, respectively, and a clock-and-voltage determination portion for determining the frequency of the clock signal and the voltage, using the operation times.

112. 发明申请

US20070268040A1 LOGIC CIRCUIT SYSTEM AND METHOD OF CHANGING OPERATING VOLTAGE OF A PROGRAMMABLE LOGIC CIRCUIT 失效
标题翻译：逻辑电路系统和可编程逻辑电路的工作电压变化方法
公开(公告)号：US20070268040A1
公开(公告)日：2007-11-22
申请号：US11831722
申请日：2007-07-31
申请人： Taku OHNEDA , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
发明人： Taku OHNEDA , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
IPC分类号： H03K19/173
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3243 , G06F1/3296 , H03K19/0008 , H03K19/0016 , H03K19/1736 , H03K19/17752 , H03K19/17756 , H03K19/17784 , H03K19/17788 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： A logic circuit system, having a programmable logic circuit including a circuit configuration including a first set of plural unit circuits and that is reconfigurable during operation, a circuit configuration information supplier configured to supply circuit configuration information about a second set of plural unit circuits to said programmable logic circuit, a change controller configured to change the circuit configuration of said programmable logic circuit from said first set of said plural unit circuits to said second set of said plural unit circuits based on said circuit configuration information, an operation time measurer configured to measure operation times of said first and second set of plural unit circuits, and a clock-and-voltage supplier configured to use said measured operation times to change from a first frequency and voltage value corresponding to said first set to a second frequency and voltage value corresponding to said second set, and to supply a clock signal having said second frequency and voltage value to said programmable logic circuit, thereby varying a programmable logic circuit frequency and voltage value in accordance with variations in said operation times.
摘要翻译：一种逻辑电路系统，具有可编程逻辑电路，该可编程逻辑电路包括电路配置，该电路配置包括第一组多个单元电路，并且可在运行期间重新配置;电路配置信息提供器，被配置为将电路配置信息提供给所述多个单元电路的第二组可编程逻辑电路，变更控制器，被配置为基于所述电路配置信息将所述可编程逻辑电路的电路配置从所述多个单元电路的所述第一组改变为所述多个单元电路的所述第二组;操作时间测量器，所述第一和第二组多个单位电路的操作时间和被配置为使用所述测量的操作时间从对应于所述第一组的第一频率和电压值变化到对应于第二频率和电压值的时钟和电压供应器到第二组，并提供一个时钟信号将所述第二频率和电压值表示为所述可编程逻辑电路，从而根据所述操作时间的变化来改变可编程逻辑电路的频率和电压值。

113. 发明申请

US20070255976A1 Processor, control device for a processor, clock frequency determining method and source voltage controlling method of a processor 失效
公开(公告)号：US20070255976A1
公开(公告)日：2007-11-01
申请号：US11819449
申请日：2007-06-27
申请人： Masaya Tarui , Shinichi Kanno
发明人： Masaya Tarui , Shinichi Kanno
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A processor comprises a clock signal generator generating clock signals; an operational processing part performing data processing which is divided into a plurality of execution units, in accordance with the clock signals; a storage storing data used when each execution unit is executed by the operational processing part; a data amount detector detecting amounts of the data stored in the storage per each execution unit; a clock frequency determining part determining a new clock frequency of the clock signals by using the amounts of the data, said clock signals being supplied newly to the operational processing part.

114. 发明申请

US20070255975A1 Processor, control device for a processor, clock frequency determining method and source voltage controlling method of a processor 失效
标题翻译：处理器，处理器的控制装置，处理器的时钟频率确定方法和源电压控制方法
公开(公告)号：US20070255975A1
公开(公告)日：2007-11-01
申请号：US11819417
申请日：2007-06-27
申请人： Masaya Tarui , Shinichi Kanno
发明人： Masaya Tarui , Shinichi Kanno
IPC分类号： G06F1/08
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A processor comprises a clock signal generator generating clock signals; an operational processing part performing data processing which is divided into a plurality of execution units, in accordance with the clock signals; a storage storing data used when each execution unit is executed by the operational processing part; a data amount detector detecting amounts of the data stored in the storage per each execution unit; a clock frequency determining part determining a new clock frequency of the clock signals by using the amounts of the data, said clock signals being supplied newly to the operational processing part.
摘要翻译：处理器包括产生时钟信号的时钟信号发生器; 操作处理部分，根据所述时钟信号执行被分成多个执行单元的数据处理; 当由所述操作处理部执行每个执行单元时使用的存储数据的存储器; 数据量检测器，检测每个执行单元存储在存储器中的数据量; 时钟频率确定部分，通过使用所述数据量确定所述时钟信号的新时钟频率，所述时钟信号被新近提供给所述操作处理部分。

115. 发明授权

US07281152B2 Processor, control device for a processor, clock frequency determining method and source voltage controlling method of a processor 失效
标题翻译：处理器，处理器的控制装置，处理器的时钟频率确定方法和源电压控制方法
公开(公告)号：US07281152B2
公开(公告)日：2007-10-09
申请号：US10808571
申请日：2004-03-25
申请人： Masaya Tarui , Shinichi Kanno
发明人： Masaya Tarui , Shinichi Kanno
IPC分类号： G06F5/06 , G06F1/00 , H04L5/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A processor includes a clock signal generator generating clock signals; an operational processing part performing data processing which is divided into a plurality of execution units, in accordance with the clock signals; a storage storing data used when each execution unit is executed by the operational processing part; a data amount detector detecting amounts of the data stored in the storage per each execution unit; a clock frequency determining part determining a new clock frequency of the clock signals by using the amounts of the data, the clock signals being supplied newly to the operational processing part.
摘要翻译：处理器包括产生时钟信号的时钟信号发生器; 操作处理部分，根据所述时钟信号执行被分成多个执行单元的数据处理; 当由所述操作处理部执行每个执行单元时使用的存储数据的存储器; 数据量检测器，检测每个执行单元存储在存储器中的数据量; 时钟频率确定部分，通过使用所述数据量来确定时钟信号的新时钟频率，所述时钟信号被新提供给所述操作处理部分。

116. 发明申请

US20060017459A1 Programmable logic circuit apparatus and programmable logic circuit reconfiguration method 失效
标题翻译：可编程逻辑电路设备和可编程逻辑电路重构方法
公开(公告)号：US20060017459A1
公开(公告)日：2006-01-26
申请号：US11081589
申请日：2005-03-17
申请人： Shinichi Kanno , Masaya Tarui , Taku Ohneda , Riku Ogawa
发明人： Shinichi Kanno , Masaya Tarui , Taku Ohneda , Riku Ogawa
IPC分类号： H03K19/177
CPC分类号： H03K19/17752
摘要： A programmable logic circuit apparatus includes a programmable logic circuit that dynamically switches and operates a plurality of circuit blocks. The circuit blocks include a branch circuit block that performs branch processing and a plurality of child circuit blocks that selectively perform a plurality of kinds of processing on data obtained by the branch circuit block. The apparatus also includes a storage unit that stores data obtained by the branch circuit block and an identifier of a child circuit block into which the data is input. The identifier is associated with the data. The apparatus also includes a controller that causes the programmable logic circuit to process data associated with the same identifier as an identifier of a child circuit block being in operation in the programmable logic circuit, among the data stored in the storage unit, in preference to data associated with identifiers of other child circuit blocks.
摘要翻译：可编程逻辑电路装置包括动态地切换和操作多个电路块的可编程逻辑电路。电路块包括执行分支处理的分支电路块和对由分支电路块获得的数据选择性地执行多种处理的多个子电路块。该装置还包括存储单元，其存储由分支电路块获得的数据和输入数据的子电路块的标识符。标识符与数据相关联。该装置还包括一个控制器，该控制器使可编程逻辑电路处理与存储在存储单元中的数据相当的与可编程逻辑电路中正在操作的子电路块的标识符相同的标识符的数据，优先于数据与其他子电路块的标识符相关联。

117. 发明授权

US06988004B2 Method for inducing angiogenesis by electrical stimulation of muscles 失效
标题翻译：通过电刺激肌肉诱导血管发生的方法
公开(公告)号：US06988004B2
公开(公告)日：2006-01-17
申请号：US09858036
申请日：2001-05-15
申请人： Shinichi Kanno , Yasufumi Sato
发明人： Shinichi Kanno , Yasufumi Sato
IPC分类号： A61N1/18
CPC分类号： A61N1/326
摘要： The present invention comprises a method for stimulating angiogenesis. The method comprises the steps of electrically stimulating muscle below the threshold for muscle contraction.
摘要翻译：本发明包括刺激血管发生的方法。该方法包括以下步骤：电刺激肌肉收缩阈值以下的肌肉。

118. 发明申请

US20050268125A1 Logic circuit apparatus 有权
标题翻译：逻辑电路装置
公开(公告)号：US20050268125A1
公开(公告)日：2005-12-01
申请号：US11128187
申请日：2005-05-13
申请人： Taku Ohneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto , Riku Ogawa
发明人： Taku Ohneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto , Riku Ogawa
IPC分类号： G06F1/32 , G06F1/08 , G06F1/30 , H03K19/00 , H03K19/173
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Programmable logic circuits are changeable circuit components based on circuit data. A circuit data memory stores a plurality of circuit data and performance requirements. A feature data memory stores feature data of each programmable logic circuit. A control unit calculates a minimum voltage of the plurality of programmable logic circuits to execute the plurality of circuit data based on the performance requirements, and selectively assigns the plurality of circuit data to the plurality of programmable logic circuits so that the performance requirement of circuit data assigned to each programmable logic circuit is within the operation range of the programmable logic circuit at the minimum voltage. A supply unit supplies the minimum voltage to the plurality of programmable logic circuits.
摘要翻译：可编程逻辑电路是基于电路数据的可变电路组件。电路数据存储器存储多个电路数据和性能要求。特征数据存储器存储每个可编程逻辑电路的特征数据。控制单元基于性能要求，计算多个可编程逻辑电路的最小电压，以执行多个电路数据，并且选择性地将多个电路数据分配给多个可编程逻辑电路，使得电路数据的性能要求分配给每个可编程逻辑电路的可编程逻辑电路在最小电压范围内。供电单元向多个可编程逻辑电路提供最小电压。

119. 发明申请

US20050138445A1 Logic circuit system and method of changing operating voltage of a programmable logic circuit 失效
标题翻译：逻辑电路系统和可编程逻辑电路的工作电压变化方法
公开(公告)号：US20050138445A1
公开(公告)日：2005-06-23
申请号：US10960707
申请日：2004-10-08
申请人： Taku Ooneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
发明人： Taku Ooneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
IPC分类号： H01L21/822 , G06F1/26 , G06F1/32 , H01L21/82 , H01L27/04 , H03K19/00 , H03K19/173
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3243 , G06F1/3296 , H03K19/0008 , H03K19/0016 , H03K19/1736 , H03K19/17752 , H03K19/17756 , H03K19/17784 , H03K19/17788 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： A logic circuit system with power consumption that is reduced by automatically varying the clock frequency and operating voltage according to processing capability imposed on programmable logic circuits. The programmable logic circuits are capable of achieving plural circuit functions dynamically and can change realized circuit functions during operation. In addition, the system has a voltage supply portion for supplying a voltage to the programmable logic circuits, a clock signal supply portion for supplying a clock signal to the programmable logic circuits, a change control portion for changing the circuit functions realized by the programmable logic circuits to any one of the circuit functions, an operation time measuring portion for measuring the operation times of the programmable logic circuits to perform processing to achieve the circuit functions, respectively, and a clock-and-voltage determination portion for determining the frequency of the clock signal and the voltage, using the operation times.
摘要翻译：通过根据施加在可编程逻辑电路上的处理能力自动改变时钟频率和工作电压，降低功耗的逻辑电路系统。可编程逻辑电路能够动态地实现多个电路功能，并且可以在操作期间改变实现的电路功能。此外，系统具有用于向可编程逻辑电路提供电压的电压供应部分，用于向可编程逻辑电路提供时钟信号的时钟信号提供部分，用于改变可编程逻辑实现的电路功能的改变控制部分电路中的任何一个电路功能，操作时间测量部分，用于分别测量可编程逻辑电路的操作时间以执行分别执行电路功能的处理;以及时钟和电压确定部分，用于确定时钟信号和电压，使用操作时间。

120. 发明申请

US20050110518A1 Logic circuit apparatus and timeshare operating method of a programmable logic circuit 失效
标题翻译：可编程逻辑电路的逻辑电路设备和分时运行方法
公开(公告)号：US20050110518A1
公开(公告)日：2005-05-26
申请号：US10948702
申请日：2004-09-24
申请人： Shinichi Kanno , Yukimasa Miyamoto , Masaya Tarui , Taku Ooneda
发明人： Shinichi Kanno , Yukimasa Miyamoto , Masaya Tarui , Taku Ooneda
IPC分类号： G06F11/00 , G06F9/06 , G06F15/76 , G06F17/50 , H03K19/173 , H03K19/177
CPC分类号： G06F17/5054
摘要： A logic circuit apparatus that allocates process capability to unit circuits operated in a time divisional manner, including a circuit arrangement information memory which stores circuit arrangement information corresponding to each of plurality of unit circuits, and a programmable logic circuit with a circuit arrangement which can be reconfigured by employing the circuit arrangement information while the programmable logic circuit is being operated, a process data memory which stores both input data and output data related to a process operation of each of the circuits, and a controller which monitors a storage amount of the input data and/or a storage amount of the output data corresponding to each unit circuit, and which controls reconfiguration of the circuit arrangement of the programmable logic circuit when the storage amount satisfies a certain condition.
摘要翻译：一种分时处理能力的逻辑电路装置，包括一个电路布置信息存储器，该电路布置信息存储器存储与多个单元电路中的每一个相对应的电路布置信息，以及一个可编程逻辑电路，该电路布置可以是通过在可编程逻辑电路正在运行时采用电路布置信息来重新配置，存储输入数据和与每个电路的处理操作相关的输出数据的处理数据存储器，以及监视输入的存储量的控制器数据和/或对应于每个单元电路的输出数据的存储量，并且当存储量满足一定条件时，控制可编程逻辑电路的电路装置的重新配置。

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