专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

111. 发明授权

US08552504B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US08552504B2
公开(公告)日：2013-10-08
申请号：US13378253
申请日：2011-03-02
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L21/70
CPC分类号： H01L29/66636 , H01L29/1083 , H01L29/6656 , H01L29/78
摘要： The present invention provides a semiconductor device, which is formed on a semiconductor substrate, comprising a gate stack, a channel region, and source/drain regions, wherein the gate stack is on the channel region, the channel region is in the semiconductor substrate, the source/drain regions are embedded in the semiconductor substrate, and each of the source/drain regions comprises a sidewall and a bottom, a second semiconductor layer being sandwiched between the channel region and a portion of the sidewall distant from the bottom, a first semiconductor layer being sandwiched between the semiconductor substrate and at least a portion of the bottom distant from the sidewall, and an insulating layer being sandwiched between the semiconductor substrate and the other portions of the bottom and/or the other portions of the sidewall. The present invention also provides a method for forming the semiconductor device. The present invention helps preventing the dopants in the source/drain regions from diffusing into the substrate.
摘要翻译：本发明提供一种半导体器件，其形成在半导体衬底上，包括栅极堆叠，沟道区和源极/漏极区，其中栅极堆叠在沟道区上，沟道区位于半导体衬底中，源极/漏极区域被嵌入在半导体衬底中，并且每个源极/漏极区域包括侧壁和底部，第二半导体层夹在沟道区域和远离底部的侧壁的一部分之间，第一半导体层被夹在半导体衬底和远离侧壁的底部的至少一部分之间，绝缘层夹在半导体衬底和侧壁的底部和/或其它部分的其它部分之间。本发明还提供了一种用于形成半导体器件的方法。本发明有助于防止源/漏区中的掺杂剂扩散到衬底中。

112. 发明授权

US08524565B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US08524565B2
公开(公告)日：2013-09-03
申请号：US13063882
申请日：2011-02-16
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A method for forming a semiconductor device is provided, wherein a step of forming an S/D region comprises: determining an interface region comprising an active region of a partial width abutting an isolation region, and forming an auxiliary layer covering the interface region; removing a semiconductor substrate of a partial thickness in the active region using the auxiliary layer, a gate stack structure and the isolation region as a mask, so as to form a groove; and growing a semiconductor material in the groove for filling into the groove. A semiconductor device having a material of the semiconductor substrate sandwiched between an S/D region and an isolation region is further provided. The present invention is beneficial to reduce current leakage.
摘要翻译：提供一种形成半导体器件的方法，其中形成S / D区域的步骤包括：确定包括邻近隔离区域的部分宽度的有源区域并形成覆盖该界面区域的辅助层的界面区域; 使用辅助层去除有源区域中的部分厚度的半导体衬底，栅极堆叠结构和隔离区域作为掩模，以形成沟槽; 并且在凹槽中生长半导体材料以填充到凹槽中。还提供了具有夹在S / D区域和隔离区域之间的半导体衬底的材料的半导体器件。本发明有益于减少电流泄漏。

113. 发明授权

US08450813B2 Fin transistor structure and method of fabricating the same 有权
标题翻译：翅片晶体管结构及其制造方法
公开(公告)号：US08450813B2
公开(公告)日：2013-05-28
申请号：US12937493
申请日：2010-06-25
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L27/088 , H01L21/02 , H01L29/78 , H01L21/336 , H01L21/3205 , H01L21/4763 , H01L21/31 , H01L21/469
CPC分类号： H01L29/7851 , H01L29/66795
摘要： There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein a bulk semiconductor material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and an insulation material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages of body-tied structures.
摘要翻译：提供鳍式晶体管结构及其制造方法。翅片晶体管结构包括形成在半导体衬底上的鳍片，其中，在用作晶体管结构的沟道区域的鳍片的一部分和衬底之间形成体半导体材料，并且在其余部分之间形成绝缘材料翅片和底物。因此，可以在保持身体结构的优点的同时减小电流泄漏。

114. 发明授权

US08445973B2 Fin transistor structure and method of fabricating the same 有权
标题翻译：翅片晶体管结构及其制造方法
公开(公告)号：US08445973B2
公开(公告)日：2013-05-21
申请号：US12937486
申请日：2010-06-24
申请人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
发明人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
IPC分类号： H01L27/088 , H01L21/02 , H01L29/78 , H01L21/336 , H01L21/3205 , H01L21/4763 , H01L21/31 , H01L21/469
CPC分类号： H01L29/7851 , H01L29/66795
摘要： There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein an insulation material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and a bulk semiconductor material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages such as low cost and high heat transfer.
摘要翻译：提供鳍式晶体管结构及其制造方法。翅片晶体管结构包括形成在半导体衬底上的鳍片，其中在用作晶体管结构的沟道区域的鳍片的一部分和衬底之间形成绝缘材料，并且在半导体衬底的剩余部分之间形成体半导体材料翅片和底物。由此，可以在保持低成本，高热传递等优点的同时，减小电流泄漏。

115. 发明申请

US20130115743A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20130115743A1
公开(公告)日：2013-05-09
申请号：US13063882
申请日：2011-02-16
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L21/8238
CPC分类号： H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A method for forming a semiconductor device is provided, wherein a step of forming an S/D region comprises: determining an interface region comprising an active region of a partial width abutting an isolation region, and forming an auxiliary layer covering the interface region; removing a semiconductor substrate of a partial thickness in the active region using the auxiliary layer, a gate stack structure and the isolation region as a mask, so as to form a groove; and growing a semiconductor material in the groove for filling into the groove. A semiconductor device having a material of the semiconductor substrate sandwiched between an S/D region and an isolation region is further provided. The present invention is beneficial to reduce current leakage.
摘要翻译：提供一种形成半导体器件的方法，其中形成S / D区域的步骤包括：确定包括邻近隔离区域的部分宽度的有源区域并形成覆盖该界面区域的辅助层的界面区域; 使用辅助层去除有源区域中的部分厚度的半导体衬底，栅极堆叠结构和隔离区域作为掩模，以形成沟槽; 并且在凹槽中生长半导体材料以填充到凹槽中。还提供了具有夹在S / D区域和隔离区域之间的半导体衬底的材料的半导体器件。本发明有益于减少电流泄漏。

116. 发明授权

US08399315B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08399315B2
公开(公告)日：2013-03-19
申请号：US13062911
申请日：2010-09-26
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L21/84
CPC分类号： H01L29/78687 , H01L29/66545 , H01L29/66621 , H01L29/66772
摘要： The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate; an epitaxial semiconductor layer formed on two side portions of the semiconductor substrate; a gate stack formed at a central position on the semiconductor substrate and abutting the epitaxial semiconductor layer, the gate comprising a gate conductor layer and a gate dielectric layer which is sandwiched between the gate conductor layer and the semiconductor substrate and surrounding the lateral surfaces of the gate conductor layer; and a sidewall spacer formed on the epitaxial semiconductor layer and surrounding the gate. The method for manufacturing the above semiconductor structure comprises forming raised source/drain regions in the epitaxial semiconductor layer utilizing the sacrificial gate. The semiconductor structure and the method for manufacturing the same can simplify the fabrication process for an ultra-thin SOI transistor and reduce the ON-state resistance and power consumption of the transistor.
摘要翻译：本申请公开了一种半导体结构及其制造方法。半导体结构包括半导体衬底; 形成在所述半导体衬底的两个侧面上的外延半导体层; 形成在所述半导体衬底上的中心位置并与所述外延半导体层邻接的栅极叠层，所述栅极包括栅极导体层和栅极电介质层，所述栅极介电层夹在所述栅极导体层和所述半导体衬底之间，栅极导体层; 以及形成在外延半导体层上并围绕栅极的侧壁间隔物。制造上述半导体结构的方法包括利用牺牲栅极在外延半导体层中形成凸起的源/漏区。半导体结构及其制造方法可以简化超薄SOI晶体管的制造工艺，并降低晶体管的导通电阻和功耗。

117. 发明申请

US20130062672A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130062672A1
公开(公告)日：2013-03-14
申请号：US13503693
申请日：2011-11-18
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/20 , H01L29/78
CPC分类号： H01L21/845 , H01L27/1211
摘要： The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor layer comprising a plurality of semiconductor sub-layers; and a plurality of fins formed in the semiconductor layer and adjoining the semiconductor layer, wherein at least two of the plurality of fins comprise different numbers of the semiconductor sub-layers and have different heights. According to the present disclosure, a plurality of semiconductor devices with different dimensions and different driving abilities can be integrated on a single wafer.
摘要翻译：本发明提供一种半导体器件及其制造方法。半导体器件包括：包括多个半导体子层的半导体层; 以及形成在所述半导体层中并与所述半导体层相邻的多个鳍，其中所述多个鳍中的至少两个鳍包括不同数量的半导体子层并具有不同的高度。根据本公开，可以在单个晶片上集成具有不同尺寸和不同驱动能力的多个半导体器件。

118. 发明授权

US08367490B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08367490B2
公开(公告)日：2013-02-05
申请号：US13144182
申请日：2011-03-04
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L29/42384 , H01L29/4908 , H01L29/6675 , H01L29/78603 , H01L29/78648 , H01L2924/0002 , H01L2924/00
摘要： The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention adjusts a threshold voltage with a common contact, which has a portion outside the source or drain region extending to the back-gate region and provides an electrical contact of the source or drain region and the back-gate region, which leads to a simple manufacturing process, an increased integration level and a lowered manufacture cost. Moreover, the asymmetric design of the back-gate structure further increases the threshold voltage and improves the performance of the device.
摘要翻译：本申请公开了一种半导体结构及其制造方法。根据本发明的半导体结构利用公共接触来调节阈值电压，该公共触点具有延伸到背栅极区域的源极或漏极区域之外的部分并且提供源极或漏极区域与背栅极的电接触区域，这导致简单的制造过程，增加的集成水平和降低的制造成本。此外，背栅结构的非对称设计进一步增加了阈值电压并提高了器件的性能。

119. 发明授权

US08361851B2 Method for manufacturing an NMOS with improved carrier mobility 有权
标题翻译：具有改善的载流子迁移率的NMOS的制造方法
公开(公告)号：US08361851B2
公开(公告)日：2013-01-29
申请号：US13063896
申请日：2010-06-21
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/338
CPC分类号： H01L29/7845 , H01L21/76897 , H01L29/66545
摘要： Tensile stress is applied to the channel region of an N-type metal oxide semiconductor (NMOS) transistor by directly forming a material having a tensile stress, for example, tungsten, in the contact holes on the source region and drain region of the NMOS. Then, the dummy gate layer in the gate stack of the NMOS transistor is removed, so as to further reduce the counter force of the gate stack on the channel region, thereby increasing the tensile stress in the channel region, enhancing the drift mobility of the carrier, and improving the performance of the transistor. The present invention avoids using a separate stress layer to create tensile stress in the channel region of an NMOS transistor, which advantageously simplifies the transistor manufacturing process and improves sizes and performance of the transistor.
摘要翻译：通过在NMOS的源极区域和漏极区域的接触孔中直接形成具有拉伸应力的材料，例如钨，在N型金属氧化物半导体（NMOS）晶体管的沟道区域上施加拉伸应力。然后，除去NMOS晶体管的栅极堆叠中的虚拟栅极层，以进一步减小栅极堆叠在沟道区域上的反作用力，从而增加沟道区域中的拉伸应力，增强了漏极迁移率载体，并提高晶体管的性能。本发明避免使用单独的应力层在NMOS晶体管的沟道区域中产生拉伸应力，这有利地简化了晶体管制造工艺并改善了晶体管的尺寸和性能。

120. 发明申请

US20130017665A1 METHODS OF FORMING ISOLATION STRUCTURE AND SEMICONDUCTOR STRUCTURE 审中-公开
标题翻译：形成隔离结构和半导体结构的方法
公开(公告)号：US20130017665A1
公开(公告)日：2013-01-17
申请号：US13380807
申请日：2011-08-05
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： The present invention relates to a method of forming an isolation structure and a semiconductor structure. The method of forming the isolation structure comprises the steps of: providing a silicon substrate having a (110) crystal plane or a (112) crystal plane and determining the [111] direction of the silicon substrate; forming first trenches in the silicon substrate by wet etching the silicon substrate, the extension direction of the first trenches being substantially perpendicular to the [111] direction; filling the first trenches with a first insulating material to form a first isolator; forming second trenches in the silicon substrate by dry etching the silicon substrate, the extension direction of the second trenches being perpendicular to the extension direction of the first trenches; filling the second trenches with a second insulating material to form a second isolator.
摘要翻译：本发明涉及形成隔离结构和半导体结构的方法。形成隔离结构的方法包括以下步骤：提供具有（110）晶面或（112）晶面并确定硅衬底的[111]方向的硅衬底; 通过湿蚀刻硅衬底在硅衬底中形成第一沟槽，第一沟槽的延伸方向基本上垂直于[111]方向; 用第一绝缘材料填充第一沟槽以形成第一隔离器; 通过干蚀刻硅衬底在硅衬底中形成第二沟槽，第二沟槽的延伸方向垂直于第一沟槽的延伸方向; 用第二绝缘材料填充第二沟槽以形成第二隔离器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式