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111. 发明授权

US07221921B2 Partitioning of radio-frequency apparatus 有权
公开(公告)号：US07221921B2
公开(公告)日：2007-05-22
申请号：US10730404
申请日：2003-12-08
申请人： James Maligeorgos , Augusto M. Marques , Lysander Lim , G. Tyson Tuttle , Aslamali A. Rafi , Tod Paulus , Gregory T. Uehara , Jeffrey W. Scott , Richard T. Behrens , Donald A. Kerth , G. Diwakar Vishakhadatta , Vishnu S. Srinivasan , Caiyi Wang
发明人： James Maligeorgos , Augusto M. Marques , Lysander Lim , G. Tyson Tuttle , Aslamali A. Rafi , Tod Paulus , Gregory T. Uehara , Jeffrey W. Scott , Richard T. Behrens , Donald A. Kerth , G. Diwakar Vishakhadatta , Vishnu S. Srinivasan , Caiyi Wang
IPC分类号： H04B7/00 , H04B1/40 , H03J7/04
CPC分类号： H04B1/30 , H03J2200/10 , H04L27/0002
摘要： Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry. Automatic frequency control (AFC) circuitry may be integrated with other components of RF circuitry and may generate frequency control signals for the frequency modification circuitry based on, for example, a signal received from a temperature sensor. Digital-to-analog converter (DAC) circuitry may be integrated with other components of RF circuitry to enable all-digital frequency control communications from baseband processor circuitry to RF circuitry.

112. 发明授权

US06859875B1 Processor having selective branch prediction 有权
标题翻译：具有选择性分支预测的处理器
公开(公告)号：US06859875B1
公开(公告)日：2005-02-22
申请号：US09592449
申请日：2000-06-12
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/30058 , G06F9/3844 , G06F9/3846
摘要： A data system capable of selecting whether to utilize address prediction based on the state of an address prediction enable signal. When employing address prediction, the outcome of branch instructions are presumed prior to the resolution of the instruction. When not using address prediction, the system waits until a branch instruction is resolved before fetching the next address to be executed. At least one embodiment of a method and data system disclosed herein makes use of the different setup timing available when employing prediction and non-prediction modes of operation.
摘要翻译：一种能够根据地址预测使能信号的状态来选择是否利用地址预测的数据系统。当采用地址预测时，在指令解析之前假设分支指令的结果。当不使用地址预测时，系统等待直到分支指令被解析，才能取出要执行的下一个地址。本文公开的方法和数据系统的至少一个实施例使用在采用预测和非预测操作模式时可用的不同设置时序。

113. 发明授权

US06591378B1 Debug controller in a data processor and method therefor 有权
标题翻译：数据处理器中的调试控制器及其方法
公开(公告)号：US06591378B1
公开(公告)日：2003-07-08
申请号：US09507740
申请日：2000-02-22
申请人： John H. Arends , Jeffrey W. Scott , William C. Moyer
发明人： John H. Arends , Jeffrey W. Scott , William C. Moyer
IPC分类号： G06F1100
CPC分类号： G06F11/362 , G06F9/321 , G06F9/3863
摘要： A method for debug control in a pipelined data processor where an offset is determined for the program counter (PC) based on the state of the pipeline. The offset is subtracted from the PC value at the end of a debug session. The resultant PC value restarts fetching of a last unsuccessfully completed instruction. If the offset indicates a change to the PC value, the instruction register is adjusted to a nop to allow the pipeline to restart execution after the last successfully completed instruction. In one embodiment, the state of the machine is preserved prior to exception handling.
摘要翻译：一种用于流水线数据处理器中的调试控制的方法，其中基于流水线的状态为程序计数器（PC）确定偏移量。在调试会话结束时从PC值中减去偏移量。所得到的PC值将重新获取最后一个未成功完成的指令。如果偏移量表示PC值的变化，则指令寄存器被调整为nop，以允许管道在上次成功完成指令之后重新启动。在一个实施例中，在异常处理之前保持机器的状态。

114. 发明授权

US06327647B1 Method and apparatus for interfacing a processor to a coprocessor 有权
标题翻译：将处理器与协处理器进行接口的方法和装置
公开(公告)号：US06327647B1
公开(公告)日：2001-12-04
申请号：US09609260
申请日：2000-06-30
申请人： William C. Moyer , John Arends , Jeffrey W. Scott
发明人： William C. Moyer , John Arends , Jeffrey W. Scott
IPC分类号： G06F1500
CPC分类号： G06F9/3012 , G06F9/30116 , G06F9/3861 , G06F9/3879 , G06F9/3881
摘要： A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.
摘要翻译：支持多个协处理器（14,16）的协处理器（14）接口的处理器（12）利用编译器可产生的软件类型函数调用和返回，指令执行以及可变加载和存储接口指令。数据在双向共享总线（28）上的处理器（12）和协处理器（14）之间隐含地通过寄存器窥探和广播来移动，或通过功能调用和返回以及可变负载和存储接口指令明确地移动。加载和存储接口指令允许选择性存储器地址预增量。双向总线（28）可以在每个时钟周期两方面潜在地驱动。接口分离接口指令解码和执行。通过在执行信号被断言之前否定解码信号来指示解码的指令丢弃来提供流水线操作。

115. 发明授权

US06237089B1 Method and apparatus for affecting subsequent instruction processing in a data processor 有权
标题翻译：影响数据处理器中后续指令处理的方法和装置
公开(公告)号：US06237089B1
公开(公告)日：2001-05-22
申请号：US09425469
申请日：1999-10-22
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F900
CPC分类号： G06F9/30094 , G06F9/30079 , G06F9/30087 , G06F9/4812
摘要： A method and apparatus affects subsequent instruction processing in a data processor (10). In one embodiment, a delay interrupt recognition instruction (IDLY4) is executed by data processor (10) to delay or conditionally delay interrupt recognition for a controlled interval, either for a predetermined period of time or for a predetermined number of instructions, so that a read/modify/write sequence of instructions can be performed without dedicated instructions which define the modification operation. The IDLY4 instruction may affect the manner in which subsequent instructions affect a condition bit (38). The condition bit (38) may thus be used to determine if exception processing occurred during the interrupt non-recognition interval after execution of the IDLY4 instruction.
摘要翻译：一种方法和装置影响数据处理器（10）中的后续指令处理。在一个实施例中，延迟中断识别指令（IDLY4）由数据处理器（10）执行以延迟或有条件地延迟中断识别，以控制间隔一段预定的时间段或预定数量的指令，使得可以在没有定义修改操作的专用指令的情况下执行读取/修改/写入指令序列。 IDLY4指令可能会影响后续指令影响条件位（38）的方式。因此，可以使用条件位（38）来确定在执行IDLY4指令之后的中断非识别间隔期间是否发生异常处理。

116. 发明授权

US5220483A Tri-level capacitor structure in switched-capacitor filter 失效
标题翻译：开关电容滤波器中的三电平电容器结构
公开(公告)号：US5220483A
公开(公告)日：1993-06-15
申请号：US821034
申请日：1992-01-16
申请人： Jeffrey W. Scott
发明人： Jeffrey W. Scott
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L27/08 , H01L29/92 , H03H19/00
CPC分类号： H01L27/0805 , H01L28/40
摘要： A tri-level capacitor structure includes a first shielded metal layer (36) that is disposed between an upper metal layer (38) and a lower polysilicon layer (34). The shielded metal layer (36) is separated from the polysilicon layer (34) by an oxide layer (42), and the upper metal layer (38) is separated from the shielded layer (36) by an oxide layer (44). The upper metal layer (38) and the polysilicon layer (34) are connected together to a node (48) to form an Insensitive Node, whereas the shielded layer (36) is connected to a node (46) that is referred to as the Sensitive Node (S). The capacitor structure is operable to be connected in a switched-capacitor configuration in a lossy integrator, such that the Sensitive Node is connected to the virtual ground of a differential amplifier (50). The integrator utilizing this configuration would be comprised of at least one switched-capacitor (56) on the input that has the plates thereof connected between ground and either an input signal V.sub.IN or the inverting input of the differential amplifier (50) through control switches (62) and (64). The Sensitive Node associated with node (46) is connected to the switch (62) such that it is connected between ground and the inverting input of amplifier (50).
摘要翻译：三电平电容器结构包括设置在上金属层（38）和下多晶硅层（34）之间的第一屏蔽金属层（36）。屏蔽金属层（36）通过氧化物层（42）与多晶硅层（34）分离，并且上部金属层（38）通过氧化物层（44）与屏蔽层（36）分离。上金属层（38）和多晶硅层（34）一起连接到节点（48）以形成不敏感节点，而屏蔽层（36）连接到被称为敏感节点（S）。电容器结构可操作地以有损积分器的开关电容器配置连接，使得灵敏节点连接到差分放大器（50）的虚拟接地。利用这种配置的积分器将由输入上的至少一个开关电容器（56）组成，该至少一个开关电容器（56）通过控制开关（其中的至少一个开关电容器56）连接在地之间，其输入信号VIN或差分放大器（50）的反相输入端 62）和（64）。与节点（46）相关联的灵敏节点连接到开关（62），使得它连接在地和放大器（50）的反相输入端之间。

117. 发明授权

US5212659A Low precision finite impulse response filter for digital interpolation 失效
标题翻译：用于数字插值的低精度有限冲击响应滤波器
公开(公告)号：US5212659A
公开(公告)日：1993-05-18
申请号：US773044
申请日：1991-10-08
申请人： Jeffrey W. Scott , Donald A. Kerth , Shaochyi Lin
发明人： Jeffrey W. Scott , Donald A. Kerth , Shaochyi Lin
IPC分类号： H03H17/00 , H03H17/02 , H03H17/06
CPC分类号： H03H17/0614 , H03H17/0671
摘要： A low precision Finite Impulse Response filter (FIR) is provided for filtering in a digital interpolation operation. The interpolation operation includes two steps, a sampling rate conversion operation for interspersing zeroes between samples in an input sequence and a filtering step of filtering out images that result from this operation. The filtering operation utilizes a FIR filter that utilizes low precision filter coefficients that are selected to tune the frequency response such that the low end frequency response including the pass band, the transition band, and the portion of the stop band immediately after the transition band provides a response equivalent to that commensurate with substantially higher precision FIR filter coefficients, with the high frequency end of the stop band gradually increasing. A second, low pass filter section is provided for filtering out the image energy that exists at the output of the FIR filter in the high frequency end of the stop band to provide an overall filter response that is commensurate to that utilizing substantially higher precision FIR coefficients in the filter section. The FIR filter coefficients utilized are restricted to the set of [-1, 0, +1] such that a multiplierless FIR filter can be realized. The FIR filter coefficients are obtained by processing the infinite FIR filter coefficients through a software delta-sigma quantizer which quantizes the output to the desired low precision FIR filter coefficients.
摘要翻译：提供了一种低精度有限脉冲响应滤波器（FIR），用于在数字插值操作中进行滤波。内插操作包括两个步骤：用于在输入序列中的样本之间散布零的采样率转换操作和滤除由该操作产生的图像的滤波步骤。滤波操作利用FIR滤波器，该FIR滤波器利用被选择来调谐频率响应的低精度滤波器系数，使得包括通带，过渡频带以及紧接在转换频带之后的阻带的部分的低端频率响应提供等效于具有与较高精度FIR滤波器系数相当的响应，阻带的高频端逐渐增加。提供了第二个低通滤波器部分，用于滤除存在于阻带的高频端中的FIR滤波器的输出处的图像能量，以提供与利用基本上更高精度的FIR系数的整体滤波器响应相匹配的整体滤波器响应在过滤器部分。所使用的FIR滤波器系数被限制为[-1,0，+1]的集合，使得可以实现无乘法FIR滤波器。 FIR滤波器系数通过软件delta-sigma量化器处理无限FIR滤波器系数来获得，该量化器将输出量化到期望的低精度FIR滤波器系数。

118. 发明申请

US20120204012A1 CONFIGURABLE PIPELINE BASED ON ERROR DETECTION MODE IN A DATA PROCESSING SYSTEM 有权
标题翻译：基于数据处理系统中的错误检测模式的可配置管道
公开(公告)号：US20120204012A1
公开(公告)日：2012-08-09
申请号：US13446930
申请日：2012-04-13
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/30 , G06F9/302 , G06F9/305 , G06F9/312
CPC分类号： G06F9/3875 , G06F9/3004 , G06F9/30181 , G06F9/30189 , G06F9/38 , G06F9/3861 , G06F9/3867 , G06F11/1004 , G06F11/1008 , G06F11/1076
摘要： A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.
摘要翻译：一种方法包括提供具有指令流水线的数据处理器，其中指令流水线具有多个指令流水线级，并且其中多条指令流水线级包括第一指令流水线级和第二指令流水线级。该方法还包括提供数据处理器指令，使数据处理器在数据处理器指令的执行期间执行第一组计算操作，如果数据处理器指令正在执行，则在第一指令流水线阶段执行第一组计算操作执行并且已经选择了第一模式，并且如果正在执行数据处理器指令并且已经选择了第二模式，则在第二指令流水线级中执行第一组计算操作。

119. 发明授权

US08224259B2 Digital architecture for radio-frequency apparatus and associated methods 有权
标题翻译：射频设备数字架构及相关方法
公开(公告)号：US08224259B2
公开(公告)日：2012-07-17
申请号：US12715361
申请日：2010-03-01
申请人： Richard T. Behrens , Tod Paulus , Mark S. Spurbeck , Vishnu S. Srinivasan , Donald A. Kerth , Jeffrey W. Scott , G. Tyson Tuttle , G. Diwakar Vishakhadatta
发明人： Richard T. Behrens , Tod Paulus , Mark S. Spurbeck , Vishnu S. Srinivasan , Donald A. Kerth , Jeffrey W. Scott , G. Tyson Tuttle , G. Diwakar Vishakhadatta
IPC分类号： H04B1/38 , H04W24/00
CPC分类号： H04B1/28 , H04B1/0003 , H04B1/38 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry. The receiver analog circuitry resides within a first integrated circuit and the receiver digital circuitry resides within a second integrated circuit. The second integrated circuit couples to the first integrated circuit via a one-bit digital interface. The receiver analog circuitry receives an RF signal and processes the received RF signal to generate a digital signal. The receiver analog circuitry provides the digital signal to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal with an intermediate frequency (IF) local oscillator (LO) signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal.
摘要翻译：射频（RF）接收机包括接收机模拟电路和接收机数字电路。接收器模拟电路驻留在第一集成电路内，并且接收器数字电路位于第二集成电路内。第二集成电路通过一位数字接口耦合到第一集成电路。接收机模拟电路接收RF信号并处理所接收的RF信号以产生数字信号。接收机模拟电路将数字信号提供给接收机数字电路。接收机数字电路包括数字下变频器电路，其将数字信号与中频（IF）本地振荡器（LO）信号混合以产生数字下变频信号。接收机数字电路还包括数字滤波器电路，其对数字下变频信号进行滤波以产生经滤波的数字信号。

120. 发明申请

US20120001288A1 SUB-PIXEL NBN DETECTOR 有权
标题翻译：子像素NBN检测器
公开(公告)号：US20120001288A1
公开(公告)日：2012-01-05
申请号：US13151085
申请日：2011-06-01
申请人： Jeffrey W. Scott , Colin E. Jones , Ernie J. Caine , Charles A. Cockrum
发明人： Jeffrey W. Scott , Colin E. Jones , Ernie J. Caine , Charles A. Cockrum
IPC分类号： H01L31/0232 , H01L31/0224
CPC分类号： H01L31/035281 , H01L27/146 , H01L27/14601 , H01L27/14603 , H01L27/14638 , H01L27/14643 , H01L27/14694 , H01L31/0304 , H01L31/101 , H01L31/102 , Y02E10/50
摘要： A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.
摘要翻译：制造二维检测器阵列（和这种阵列）的方法包括形成n掺杂的半导体光吸收层的多行和多列单独的检测器中的每一个，形成阻挡层，该阻挡层包括 AlSb，AlAsSb，AlGaAsSb，AlPSb，AlGaPSb和HgZnTe中的一种或多种，并且形成n掺杂的半导体接触区域。

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