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111. 发明授权

US09543192B2 Stitched devices 有权
标题翻译：缝合设备
公开(公告)号：US09543192B2
公开(公告)日：2017-01-10
申请号：US14715538
申请日：2015-05-18
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Wei Shao , Juan Boon Tan , Wei Liu , Wanbing Yi
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/76 , H01L21/768 , H01L23/528
CPC分类号： H01L27/0203 , H01L21/4857 , H01L21/486 , H01L21/76801 , H01L21/76838 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/5226 , H01L23/528 , H01L24/24 , H01L24/82 , H01L25/0655 , H01L25/50 , H01L2224/24137 , H01L2224/82895 , H01L2924/14
摘要： A stitched device is disclosed. The stitched device includes first and second base devices having first and second stitched interconnects electrically coupled in a stitching level. This enables a single substrate of the stitched device to have electrically coupled first and second base devices.
摘要翻译：公开了一种缝合装置。缝合装置包括第一和第二基底装置，其具有以缝合水平电耦合的第一和第二缝合互连。这使得缝合装置的单个基板具有电耦合的第一和第二基本装置。

112. 发明授权

US09520506B2 3D high voltage charge pump 有权
标题翻译： 3D高压电荷泵
公开(公告)号：US09520506B2
公开(公告)日：2016-12-13
申请号：US14338354
申请日：2014-07-23
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Laiqiang Luo , Xinshu Cai , Danny Shum , Fan Zhang , Khee Yong Lim , Juan Boon Tan , Shaoqiang Zhang
IPC分类号： H01L29/94 , H01L29/66 , H01L23/522 , H01L27/08 , H01L49/02
CPC分类号： H01L29/94 , H01L23/5223 , H01L27/0805 , H01L28/86 , H01L28/90 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A capacitor and method of forming a capacitor are presented. The capacitor includes a substrate having a capacitor region in which the capacitor is disposed. The capacitor includes first, second and third sub-capacitors (C1, C2 and C3). The C1 comprises a metal oxide semiconductor (MOS) capacitor which includes a gate on the substrate. The gate includes a gate electrode over a gate dielectric. A first C1 plate is served by the gate electrode, a second C1 plate is served by the substrate of the capacitor region and a C1 capacitor dielectric is served by the gate dielectric. The C2 includes a back-end-of-line (BEOL) vertical capacitor disposed in ILD layers with metal levels and via levels. A plurality of metal lines are disposed in the metal levels. The metal lines of a metal level are grouped in alternating first and second groups, the first group serves as first C2 plates and second group serves as second C2 plates and the dielectric layers between the first and second groups serve as C2 capacitor dielectrics. The C3 includes a first C3 plate served by the gate electrode, a second C3 plate served by second group lines in the first metal level of the ILD layers, and a C3 capacitor dielectric is served by the first via level dielectric below M1 and above the gate electrode. A first capacitor terminal is coupled to first capacitor plates of C1, C2 and C3 and a second capacitor terminal is coupled to second capacitor plates of C1, C2 and C3.
摘要翻译：提出了一种形成电容器的电容器和方法。电容器包括具有其中设置电容器的电容器区域的基板。电容器包括第一，第二和第三子电容器（C1，C2和C3）。 C1包括在衬底上包括栅极的金属氧化物半导体（MOS）电容器。栅极包括位于栅极电介质上的栅电极。第一C1板由栅极电极供电，第二C1板由电容器区域的衬底供电，C1电容器电介质由栅极电介质供电。 C2包括设置在具有金属电平和通孔电平的ILD层中的后端行（BEOL）垂直电容器。多个金属线设置在金属层中。金属层的金属线以交替的第一和第二组分组，第一组用作第一C2板，第二组用作第二C2板，并且第一和第二组之间的介电层用作C2电容器电介质。 C3包括由栅电极服务的第一C3板，由ILD层的第一金属层中的第二组线服务的第二C3板，并且C3电容器电介质由位于M1之下的第一通孔级电介质和栅电极。第一电容器端子耦合到C1，C2和C3的第一电容器板，并且第二电容器端子耦合到C1，C2和C3的第二电容器板。

113. 发明授权

US09397139B1 Integrated inductor and magnetic random access memory device 有权
标题翻译：集成电感和磁性随机存取存储器件
公开(公告)号：US09397139B1
公开(公告)日：2016-07-19
申请号：US14862174
申请日：2015-09-23
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Juan Boon Tan , Yi Jiang , Wanbing Yi , Danny Pak-Chum Shum
IPC分类号： H01L27/22 , H01F27/28 , H01L43/02 , H01L43/12 , H01L49/02
CPC分类号： H01L27/222 , H01F17/0013 , H01L28/10 , H01L43/02 , H01L43/12
摘要： Devices and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first upper dielectric layer is provided over the substrate. The first upper dielectric layer comprises a first upper interconnect level with a plurality of metal lines. A dielectric layer is formed over the first upper dielectric layer. The dielectric layer includes a second upper interconnect level with a plurality of metal lines. A magnetic random access memory (MRAM) cell is formed between the first and second upper interconnect levels in the first region. An inductor is formed in the second region. The inductor includes a lower inductor level formed from metal lines in the first upper interconnect level and an upper inductor level formed from metal lines in the second upper interconnect level. The metal lines in the lower inductor level and upper inductor level are coupled by via contacts to form loops of the inductor.
摘要翻译：公开了形成装置的装置和方法。该方法包括提供限定有至少第一和第二区域的基底。第一上电介质层设置在衬底上。第一上介电层包括具有多条金属线的第一上互连级别。介电层形成在第一上电介质层上。介电层包括具有多条金属线的第二上互连级别。磁性随机存取存储器（MRAM）单元形成在第一区域中的第一和第二上互连级之间。在第二区域形成电感器。电感器包括由第一上部互连电平中的金属线形成的较低电感器电平和由第二上部互连电平中的金属线形成的上部电感器电平。较低电感电平和上电感电平的金属线通过通孔触点耦合，形成电感的环路。

114. 发明授权

US09362171B2 Through via contacts with insulated substrate 有权
标题翻译：通过与绝缘基板的接触
公开(公告)号：US09362171B2
公开(公告)日：2016-06-07
申请号：US14140553
申请日：2013-12-26
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Shunqiang Gong , Juan Boon Tan , Wei Liu
IPC分类号： H01L21/44 , H01L21/768 , H01L21/48 , H01L21/683 , H01L23/522 , H01L23/00 , H01L25/065
CPC分类号： H01L21/76898 , H01L21/486 , H01L21/6835 , H01L21/76831 , H01L21/76871 , H01L21/76877 , H01L21/76892 , H01L23/147 , H01L23/49827 , H01L23/522 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2224/03002 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/11002 , H01L2224/13022 , H01L2224/131 , H01L2224/16145 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2924/10253 , H01L2924/10271 , H01L2924/14 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/014 , H01L2224/11 , H01L2224/03
摘要： Device and a method of forming a device are disclosed. The method includes providing a crystalline-on-insulator (COI) substrate. The COI substrate includes at least a base substrate over a buried insulator layer. Through via (TV) contacts are formed within the substrate. The TV contact extends from a top surface of the base substrate to within the buried insulator layer. Upper interconnect levels are formed over the top surface of the base substrate. A lower redistribution (RDL) is formed over a bottom surface of the base substrate. The buried insulator layer corresponds to a first RDL dielectric layer of the lower RDL and protects the sidewalls of the TV contacts.
摘要翻译：公开了一种装置和一种形成装置的方法。该方法包括提供绝缘体上的结晶（COI）衬底。 COI衬底至少包括在掩埋绝缘体层上的基底衬底。在基片内形成通孔（TV）触点。 TV触点从基底的顶表面延伸到掩埋绝缘体层内。上部互连电平形成在基底衬底的顶表面上。在基底衬底的底表面上形成较低的再分布（RDL）。掩埋绝缘体层对应于下RDL的第一RDL电介质层并保护电视触点的侧壁。

115. 发明授权

US09349772B2 Methods for fabricatingintegrated circuits with spin torque transfer magnetic randomaccess memory (STT-MRAM) including a passivation layer formed along lateral sidewalls of a magnetic tunnel junction of the STT-MRAM 有权
标题翻译：用自旋转矩传递磁性随机存取存储器（STT-MRAM）制造集成电路的方法包括沿着STT-MRAM的磁性隧道结的侧壁形成的钝化层
公开(公告)号：US09349772B2
公开(公告)日：2016-05-24
申请号：US14261543
申请日：2014-04-25
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Wanbing Yi , Yang Hong , Yi Jiang , Francis Poh , Tze Ho Simon Chan , Juan Boon Tan
IPC分类号： H01L27/10 , H01L27/22 , H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12 , G11C11/16
CPC分类号： H01L27/222 , G11C11/16 , G11C11/161 , G11C11/1659 , H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12
摘要： A method of fabricating an integrated circuit includes depositing a bottom electrode layer, an MTJ layer, and a top electrode layer over a passivation layer and within a trench of the passivation layer and removing portions of the MTJ layer and the top electrode layer to form an MTJ/top electrode stack over the bottom electrode layer and at least partially within portions of the trench having being reopened by said removing. The method further includes forming a further passivation layer over the MTJ/top electrode stack, forming a further ILD layer of the further passivation layer, and reforming a top electrode layer over the ILD layer and over the MTJ/top electrode stack. Still further, the method includes removing portions of the bottom electrode layer, the further passivation layer, the further ILD layer, and the re-formed top electrode layer to form a bottom electrode/MTJ/top electrode stack.
摘要翻译：一种制造集成电路的方法包括在钝化层上方和钝化层的沟槽内沉积底部电极层，MTJ层和顶部电极层，并且去除MTJ层和顶部电极层的部分以形成 MTJ /顶部电极堆叠在底部电极层上方，并且至少部分地在沟槽的部分内被所述去除重新打开。该方法还包括在MTJ /顶部电极堆叠上形成另外的钝化层，形成另外的钝化层的另外的ILD层，以及在ILD层上和MTJ /顶部电极堆叠上重整顶部电极层。此外，该方法包括去除底部电极层，另外的钝化层，另外的ILD层和重新形成的顶部电极层的部分，以形成底部电极/ MTJ /顶部电极堆叠。

116. 发明授权

US09263322B2 Reliable contacts 有权
标题翻译：可靠的联系人
公开(公告)号：US09263322B2
公开(公告)日：2016-02-16
申请号：US14029820
申请日：2013-09-18
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Tian-Lin Chang , Jianfang Liang , Aaron Chen , Yew Tuck Clament Chow , Fan Zhang , Juan Boon Tan
IPC分类号： H01L21/311 , H01L21/768 , H01L23/48
CPC分类号： H01L21/76804 , H01L21/31116 , H01L21/31144 , H01L21/76829 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods for forming a semiconductor device are presented. The method includes providing a substrate having a device component with a contact region. A contact dielectric layer is formed on the substrate, covering the substrate and device component. The contact dielectric layer includes a lower contact dielectric layer, an intermediate contact dielectric etch stop layer formed on the lower contact dielectric layer, and an upper contact dielectric layer formed on the intermediate contact dielectric etch stop layer. A contact opening is formed through the contact dielectric layer. The contact opening has an upper contact sidewall profile in the upper contact dielectric layer and a lower tapered contact sidewall profile in the lower contact dielectric layer. The tapered sidewall profile prevents shorting with the device component.
摘要翻译：本发明提供半导体装置及半导体装置的制造方法。该方法包括提供具有具有接触区域的器件部件的衬底。在基板上形成接触电介质层，覆盖基板和元件部件。接触介电层包括下接触电介质层，形成在下接触电介质层上的中间接触电介质蚀刻停止层和形成在中间接触电介质蚀刻停止层上的上接触电介质层。通过接触电介质层形成接触开口。接触开口在上接触电介质层中具有上接触侧壁轮廓，在下接触电介质层中具有下锥形接触侧壁轮廓。锥形侧壁轮廓防止装置部件短路。

117. 发明授权

US09111941B2 Non-volatile memory device with TSI/TSV application 有权
标题翻译：具有TSI / TSV应用的非易失性存储器件
公开(公告)号：US09111941B2
公开(公告)日：2015-08-18
申请号：US13906289
申请日：2013-05-30
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Shunqiang Gong , Juan Boon Tan , Lei Wang , Wei Liu , Wanbing Yi , Jens Oswald
IPC分类号： H01L23/52 , H01L29/40 , H01L21/4763 , H01L23/538 , H01L27/22 , H01L27/24 , H01L23/498
CPC分类号： H01L23/5386 , H01L23/49822 , H01L23/49827 , H01L23/5383 , H01L27/222 , H01L27/2463 , H01L2224/16225 , H01L2924/15311
摘要： Memory devices and methods for forming the device are disclosed. The device includes a substrate having an array surface and a non-array surface and a memory array having a plurality of memory cells interconnected by first conductors in a first direction and second conductors in a second direction. The memory array is disposed on the array surface of the substrate. The device further includes through silicon via (TSV) contacts disposed in the substrate. The TSV contacts extend from the array surface to the non-array surface, enabling electrical connections to the array from the non-array surface.
摘要翻译：公开了用于形成装置的存储装置和方法。该器件包括具有阵列表面和非阵列表面的衬底和存储器阵列，该存储器阵列具有多个存储器单元，该多个存储器单元通过第一方向的第一导体和第二方向上的第二导体互连。存储器阵列设置在衬底的阵列表面上。该器件还包括通过布置在衬底中的硅通孔（TSV）触点。 TSV触点从阵列表面延伸到非阵列表面，使得能够从非阵列表面到阵列的电连接。

118. 发明申请

US20150179543A1 THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURES PROVIDING THERMOELECTRIC COOLING AND METHODS FOR COOLING SUCH INTEGRATED CIRCUIT STRUCTURES 有权
标题翻译：提供热电冷却的三维集成电路结构和用于冷却这种集成电路结构的方法
公开(公告)号：US20150179543A1
公开(公告)日：2015-06-25
申请号：US14138593
申请日：2013-12-23
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Juan Boon Tan , Wei Liu , Kheng Chok Tee , Kam Chew Chew
IPC分类号： H01L23/38 , H01L23/367 , H01L25/065 , H01L23/48
CPC分类号： H01L23/38 , H01L23/3677 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/131 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06589 , H01L2924/0002 , H01L2924/10252 , H01L2924/10253 , H01L2924/10329 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2924/014
摘要： Three-dimensional integrated circuit structures providing thermoelectric cooling and methods for cooling such integrated circuit structures are disclosed. In one exemplary embodiment, a three-dimensional integrated circuit structure includes a plurality of integrated circuit chips stacked one on top of another to form a three-dimensional chip stack, a thermoelectric cooling daisy chain comprising a plurality of vias electrically connected in series with one another formed surrounding the three-dimensional chip stack, a thermoelectric cooling plate electrically connected in series with the thermoelectric cooling daisy chain, and a heat sink physically connected with the thermoelectric cooling plate.
摘要翻译：公开了提供热电冷却的三维集成电路结构和用于冷却这种集成电路结构的方法。在一个示例性实施例中，三维集成电路结构包括堆叠在另一个之上的多个集成电路芯片，以形成三维芯片堆叠;热电冷却菊花链，包括与一个电连接的多个通孔形成在三维芯片堆叠周围的另一个，与热电冷却菊花链串联电连接的热电冷却板，以及与热电冷却板物理连接的散热器。

119. 发明申请

US20150171025A1 INTEGRATED CIRCUITS HAVING CRACK-STOP STRUCTURES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：具有断裂结构的集成电路及其制造方法
公开(公告)号：US20150171025A1
公开(公告)日：2015-06-18
申请号：US14132368
申请日：2013-12-18
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Wei Shao , Fan Zhang , Juan Boon Tan
IPC分类号： H01L23/00 , H01L21/263 , H01L23/532 , H01L23/522 , H01L21/768 , H01L21/311
CPC分类号： H01L23/562 , H01L21/2633 , H01L21/31116 , H01L21/76805 , H01L21/76807 , H01L21/76879 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes fabricating a crack-stop structure that extends through a plurality of metallization layers above a semiconductor substrate. The plurality of metallization layers includes a first metallization layer and a second metallization layer that overlies the first metallization layer. Fabricating the crack-stop structure includes forming a first via-bar overlying and coupled to a first metal line of the first metallization layer that is disposed in a first ILD layer of dielectric material. The first via-bar is disposed in a second ILD layer of dielectric material and has a first width. A second metal line of the second metallization layer that is in the second ILD layer is formed overlying and coupled to the first via-bar. The second metal line has a second width that is from about 1 to about 5 times the first width.
摘要翻译：提供了用于制造集成电路的集成电路和方法。在一个示例中，制造集成电路的方法包括制造延伸穿过半导体衬底上的多个金属化层的裂纹 - 停止结构。多个金属化层包括覆盖在第一金属化层上的第一金属化层和第二金属化层。制造裂纹 - 停止结构包括形成第一通孔条，其覆盖并耦合到第一金属化层的设置在介电材料的第一ILD层中的第一金属线。第一通孔杆设置在介电材料的第二ILD层中并且具有第一宽度。位于第二ILD层中的第二金属化层的第二金属线形成为覆盖并耦合到第一通孔条。第二金属线具有第一宽度的约1至约5倍的第二宽度。

120. 发明公开

US20240268241A1 LAYER STACKS FOR A RESISTIVE MEMORY ELEMENT 审中-公开
公开(公告)号：US20240268241A1
公开(公告)日：2024-08-08
申请号：US18105922
申请日：2023-02-06
申请人： GlobalFoundries Singapore Pte. Ltd.
发明人： Curtis Chun-I Hsieh , Kai Kang , Wanbing Yi , Yongshun Sun , Eng-Huat Toh , Juan Boon Tan
IPC分类号： H10N70/00 , H01L23/528 , H10B63/00
CPC分类号： H10N70/841 , H01L23/5283 , H10B63/34 , H10N70/063 , H10N70/883
摘要： Structures that include a layer stack for a resistive memory element and methods of forming a structure that includes a layer stack for a resistive memory element. The structure comprises a resistive memory element including a first electrode, a second electrode, and a switching layer disposed between the second electrode and the first electrode. The first electrode includes a first layer and a second layer between the first layer and the switching layer. The switching layer has a first thickness, and the second layer of the first electrode has a second thickness that is less than the first thickness of the switching layer.

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