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111. 发明授权

US08194854B2 Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation 有权
标题翻译：用于在并行运行模式下优化先进加密标准（AES）加密和解密的方法和装置
公开(公告)号：US08194854B2
公开(公告)日：2012-06-05
申请号：US12038071
申请日：2008-02-27
申请人： Shay Gueron , Amit Gradstein , Zeev Sperber
发明人： Shay Gueron , Amit Gradstein , Zeev Sperber
IPC分类号： H04L9/06 , H04L9/00 , H04L9/30 , H04L9/28 , H03K19/173 , H04K1/04
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/125
摘要： The throughput of an encryption/decryption operation is increased in a system having a pipelined execution unit. Different independent encryptions (decryptions) of different data blocks may be performed in parallel by dispatching an AES round instruction in every cycle.
摘要翻译：在具有流水线执行单元的系统中，加密/解密操作的吞吐量增加。可以通过在每个周期中调度AES循环指令来并行地执行不同数据块的不同的独立加密（解密）。

112. 发明申请

US20120002804A1 ARCHITECTURE AND INSTRUCTION SET FOR IMPLEMENTING ADVANCED ENCRYPTION STANDARD (AES) 有权
标题翻译：实施高级加密标准（AES）的架构和指导
公开(公告)号：US20120002804A1
公开(公告)日：2012-01-05
申请号：US13088088
申请日：2011-04-15
申请人： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
发明人： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
IPC分类号： H04L9/28
CPC分类号： H04L9/0631 , G06F9/30007 , G06F21/602 , H04L9/14 , H04L2209/24
摘要： A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
摘要翻译：提供了一种用于通用处理器的灵活的aes指令，其使用n次循环执行aes加密或解密，其中n包括标准的一组轮{10,12,14}。提供了一个参数，以允许选择一轮的类型，即是否是“最后一轮”。除了标准aes之外，灵活的aes指令允许指定具有20发的AES类密码或“一轮”通过。

113. 发明授权

US08010587B2 Random number generator 有权
标题翻译：随机数发生器
公开(公告)号：US08010587B2
公开(公告)日：2011-08-30
申请号：US11899574
申请日：2007-09-06
申请人： Mohan J. Kumar , Shay Gueron
发明人： Mohan J. Kumar , Shay Gueron
IPC分类号： G06F1/02
CPC分类号： G06F7/588 , G06F7/58 , H04L9/0662 , H04L2209/20
摘要： Systems, methods, and other embodiments associated with random number generators are described. One system embodiment includes a random number generator logic that may produce an initial random number from a first set of three inputs. The system embodiment may receive the three inputs from sources including an internal counter entropy source (ICES), an internal arbitrary entropy source (IAES), and an external entropy source (EES). The system embodiment may generate a first random number from a first set of three inputs (e.g., value from ICES, value from IAES, value from EES) but may then generate subsequent random numbers from a different set of three inputs (e.g., value from ICES, value from IAES, previous random number).
摘要翻译：描述与随机数生成器相关联的系统，方法和其他实施例。一个系统实施例包括随机数发生器逻辑，其可以从第一组三个输入产生初始随机数。系统实施例可以从包括内部计数器熵源（ICES），内部任意熵源（IAES）和外部熵源（EES）的源接收三个输入。系统实施例可以从第一组三个输入（例如，来自ICES的值，来自IAES的值，来自EES的值）生成第一随机数，然后可以从不同的三个输入集合（例如，来自 ICES，IAES的值，以前的随机数）。

114. 发明授权

US07991152B2 Speeding up Galois Counter Mode (GCM) computations 有权
标题翻译：加速伽罗瓦计数器模式（GCM）计算
公开(公告)号：US07991152B2
公开(公告)日：2011-08-02
申请号：US11772150
申请日：2007-06-30
申请人： Shay Gueron , Michael E. Kounavis
发明人： Shay Gueron , Michael E. Kounavis
IPC分类号： H04K1/00
CPC分类号： G06F7/724 , H04L9/0631 , H04L9/0643 , H04L9/3242 , H04L2209/043
摘要： Methods and apparatus to speed up Galois Counter Mode (GCM) computations are described. In one embodiment, a carry-less multiplication instruction may be used to perform operations corresponding to verification of an encrypted message in accordance with GCM. Other embodiments are also described.
摘要翻译：描述加速伽罗瓦计数器模式（GCM）计算的方法和装置。在一个实施例中，可以使用无进位乘法指令来执行与根据GCM的加密消息的验证相对应的操作。还描述了其它实施例。

115. 发明申请

US20110145683A1 Instruction-set architecture for programmable cyclic redundancy check (CRC) computations 有权
标题翻译：用于可编程循环冗余校验（CRC）计算的指令集架构
公开(公告)号：US20110145683A1
公开(公告)日：2011-06-16
申请号：US12653249
申请日：2009-12-10
申请人： Vinodh Gopal , Shay Gueron , Gilbert M. Wolrich , Wajdi K. Feghali , Kirk S. Yap , Bradley A. Burres
发明人： Vinodh Gopal , Shay Gueron , Gilbert M. Wolrich , Wajdi K. Feghali , Kirk S. Yap , Bradley A. Burres
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G06F9/30145 , G06F9/30018 , G06F11/1004 , H03M13/09 , H03M13/091
摘要： A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.
摘要翻译：提供了使用多个不同的n位多项式对数据块执行循环冗余校验（CRC）操作的方法和装置。灵活的CRC指令使用可编程的n位多项式来执行CRC操作。通过将n位多项式存储在两个操作数之一中，将n位多项式提供给CRC指令。

116. 发明授权

US07958320B2 Protected cache architecture and secure programming paradigm to protect applications 有权
标题翻译：保护缓存架构和安全编程范例来保护应用程序
公开(公告)号：US07958320B2
公开(公告)日：2011-06-07
申请号：US11998902
申请日：2007-12-03
申请人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
发明人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
IPC分类号： G06F12/06
CPC分类号： G06F12/0802 , G06F12/0804 , G06F12/1491 , G06F21/10
摘要： Embodiments of the present invention provide a secure programming paradigm, and a protected cache that enable a processor to handle secret/private information while preventing, at the hardware level, malicious applications from accessing this information by circumventing the other protection mechanisms. A protected cache may be used as a building block to enhance the security of applications trying to create, manage and protect secure data. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供了一种安全编程范例和受保护的高速缓存，其使得处理器能够处理秘密/专用信息，同时防止恶意应用程序通过规避其他保护机制来访问该信息。受保护的缓存可以用作构建块，以增强试图创建，管理和保护安全数据的应用程序的安全性。描述和要求保护其他实施例。

117. 发明申请

US20100082718A1 COMBINED SET BIT COUNT AND DETECTOR LOGIC 有权
标题翻译：组合设置位计数和检测器逻辑
公开(公告)号：US20100082718A1
公开(公告)日：2010-04-01
申请号：US12242727
申请日：2008-09-30
申请人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
发明人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
IPC分类号： G06F7/00
CPC分类号： G06F7/74 , G06F7/607
摘要： A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word).
摘要翻译：描述了PopCount和BitScan的合并数据路径。硬件电路包括用于PopCount功能的压缩器树，其由BitScan功能（例如，位扫描前向（BSF）或位扫描反向（BSR））重用。选择器逻辑使压缩器树能够基于微处理器指令对PopCount或BitScan操作的输入字进行操作。如果选择了BitScan操作，则输入字被编码。压缩器树接收输入字，对位进行操作，好像所有位具有相同的重要程度（例如，对于N位输入字，输入字被视为N个一位输入）。压缩器树电路的结果是表示与执行的操作有关的数字的二进制值（PopCount的设置位数，或通过扫描输入字所遇到的第一组位的位位置）。

118. 发明申请

US20090168998A1 EXECUTING AN ENCRYPTION INSTRUCTION USING STORED ROUND KEYS 有权
标题翻译：使用存放的圆环执行加密指令
公开(公告)号：US20090168998A1
公开(公告)日：2009-07-02
申请号：US11966792
申请日：2007-12-28
申请人： Shay Gueron , Martin G. Dixon , Srinivas Chennupaty
发明人： Shay Gueron , Martin G. Dixon , Srinivas Chennupaty
IPC分类号： H04L9/28
CPC分类号： H04L9/0681 , H04L9/0631 , H04L2209/12 , H04L2209/24
摘要： Embodiments of an invention for executing an encryption instruction using stored round keys are disclosed. In one embodiment, an apparatus includes instruction logic, encryption logic, a storage region, and control logic. The instruction logic is to receive an encryption instruction. The encryption logic is to perform, in response to the instruction logic receiving the encryption instruction, an encryption operation including a plurality of rounds, each round using a corresponding round key from a plurality of round keys. The storage region is to store the plurality of round keys. The control logic is to fetch, for use during each of the plurality of rounds, the corresponding round key from the storage region.
摘要翻译：公开了使用存储的循环密钥执行加密指令的本发明的实施例。在一个实施例中，装置包括指令逻辑，加密逻辑，存储区和控制逻辑。指令逻辑是接收加密指令。加密逻辑是响应于接收到加密指令的指令逻辑执行包括多个回合的加密操作，每个循环使用来自多个循环密钥的对应的循环密钥。存储区域用于存储多个循环密钥。控制逻辑是为了在多个回合中的每个循环期间使用来自存储区域的相应的循环密钥。

119. 发明申请

US20090089564A1 Protecting a Branch Instruction from Side Channel Vulnerabilities 审中-公开
标题翻译：保护分支指令免受副渠道漏洞的影响
公开(公告)号：US20090089564A1
公开(公告)日：2009-04-02
申请号：US11951999
申请日：2007-12-06
申请人： Ernie F. Brickell , Sergiu Ghetie , Shay Gueron , Adil Karrar , Francis X. McKeen
发明人： Ernie F. Brickell , Sergiu Ghetie , Shay Gueron , Adil Karrar , Francis X. McKeen
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/30003 , G06F9/30076 , G06F9/30181 , G06F9/30185 , G06F9/3842 , G06F9/3846 , G06F21/556
摘要： Embodiments of an invention to protection a branch instruction from side channel vulnerabilities are described. In one embodiment, a method includes receiving a request to modify the operation of a processor to protect against side channel attacks, and modifying branch prediction operation in response to the request.
摘要翻译：描述了保护分支指令免受侧面通道漏洞的发明的实施例。在一个实施例中，一种方法包括接收修改处理器的操作以防止侧信道攻击的请求，以及响应于该请求修改分支预测操作。

120. 发明申请

US20090086981A1 Methods and Apparatus for Batch Bound Authentication 有权
标题翻译：批量绑定认证方法与装置
公开(公告)号：US20090086981A1
公开(公告)日：2009-04-02
申请号：US11864887
申请日：2007-09-28
申请人： Mohan J. Kumar , Shay Gueron
发明人： Mohan J. Kumar , Shay Gueron
IPC分类号： G06F21/00 , H04L9/08 , G06F15/177 , H04L9/30
CPC分类号： G06F21/572 , G06F21/575
摘要： A processing system may include a processing unit and nonvolatile storage responsive to the processing unit. The nonvolatile storage may include a candidate boot code module and an authentication code module. The processing unit may be configured to execute code from the authentication code module before executing code from the candidate boot code module. The authentication code module may have instructions which, when executed by the processing unit, cause the processing unit to read a processor identifier from the processing unit and determine whether the processor belongs to a predetermined set of processors associated with a specific vendor, based at least in part on the identifier, before executing any instructions from the candidate boot code module. The processing system may also test authenticity of the candidate boot code module before executing any instructions from the candidate boot code module. Other embodiments are described and claimed.
摘要翻译：处理系统可以包括响应于处理单元的处理单元和非易失性存储器。非易失性存储器可以包括候选引导代码模块和认证代码模块。处理单元可以被配置为在从候选引导代码模块执行代码之前从认证代码模块执行代码。认证码模块可以具有指令，当由处理单元执行时，处理单元至少从处理单元读取处理器标识符并且确定处理器是否属于与特定供应商相关联的预定处理器集合部分地在标识符上，在执行来自候选引导代码模块的任何指令之前。在执行来自候选引导代码模块的任何指令之前，处理系统还可以测试候选引导代码模块的真实性。描述和要求保护其他实施例。

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