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101. 发明授权

US09349728B1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09349728B1
公开(公告)日：2016-05-24
申请号：US14670428
申请日：2015-03-27
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chia-Fu Hsu , Bo-Rong Chen
IPC分类号： H01L23/535 , H01L27/088 , H01L21/8258 , H01L29/786
CPC分类号： H01L27/088 , H01L21/8258 , H01L23/485 , H01L27/1225 , H01L29/7869 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal-oxide semiconductor (MOS) transistor thereon and a first interlayer dielectric (ILD) layer surrounding the MOS transistor; forming a source layer, a drain layer, a first opening between the source layer and the drain layer, and a second ILD layer on the MOS transistor and the first ILD layer, wherein the top surfaces of the source layer, the drain layer, and the second ILD layer are coplanar; forming a channel layer on the second ILD layer, the source layer, and the drain layer and into the first opening; and performing a first planarizing process to remove part of the channel layer so that the top surface of the channel layer is even with the top surfaces of the source layer and the drain layer.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：提供其上具有金属氧化物半导体（MOS）晶体管的衬底和围绕MOS晶体管的第一层间电介质（ILD）层; 在源极层和漏极层之间形成源极层，漏极层，第一开口以及MOS晶体管和第一ILD层上的第二ILD层，其中源极层，漏极层和第二ILD层是共面的; 在第二ILD层，源极层和漏极层上形成沟道层并进入第一开口; 并且执行第一平坦化处理以去除沟道层的一部分，使得沟道层的顶表面与源极层和漏极层的顶表面平齐。

102. 发明授权

US09331153B2 Methods and structures for forming microstrip transmission lines on thin silicon on insulator (SOI) wafers 有权
标题翻译：在薄绝缘体（SOI）晶片上形成微带传输线的方法和结构
公开(公告)号：US09331153B2
公开(公告)日：2016-05-03
申请号：US14105497
申请日：2013-12-13
申请人： Raytheon Company
发明人： Jeffrey R. LaRoche
IPC分类号： H01L29/20 , H01L21/02 , H01L21/762 , H01L21/768 , H01L21/8258 , H01L23/66 , H01L21/683
CPC分类号： H01L29/2003 , H01L21/0254 , H01L21/6835 , H01L21/76251 , H01L21/76898 , H01L21/8258 , H01L23/66 , H01L2221/68327 , H01L2224/32145 , H01L2924/0002 , H01L2924/00
摘要： A structure is provided having: (A) a first silicon layer and a first silicon dioxide layer over the first silicon layer; and (B) a second silicon layer and a second silicon dioxide layer over the second silicon layer; the first silicon dioxide layer bonded to the second silicon dioxide layer. An upper surface of the first silicon layer is polished to reduce its thickness. A III-V layer is grown on the upper surface of the thinned silicon layer. A III-V device is formed in the III-V layer together with a strip conductor connected to the formed. The second silicon layer, the second silicon dioxide layer and the first silicon dioxide layer are successively removed to expose a bottom surface of the first silicon layer. A ground plane conductor is formed on the exposed bottom surface, the strip conductor and the ground plane conductor providing a microstrip transmission line.
摘要翻译：提供一种结构，其具有：（A）第一硅层上的第一硅层和第一二氧化硅层; 和（B）第二硅层上的第二硅层和第二二氧化硅层; 所述第一二氧化硅层与所述第二二氧化硅层结合。抛光第一硅层的上表面以减小其厚度。在薄化硅层的上表面上生长III-V层。 III-V器件与连接到形成的带状导体一起形成在III-V层中。依次去除第二硅层，第二二氧化硅层和第一二氧化硅层以露出第一硅层的底表面。接地平面导体形成在暴露的底表面上，带状导体和接地平面导体提供微带传输线。

103. 发明授权

US09324733B2 Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics 有权
标题翻译：半导体互连中的受控弯曲结构和用于可拉伸电子学的纳米膜
公开(公告)号：US09324733B2
公开(公告)日：2016-04-26
申请号：US14220910
申请日：2014-03-20
申请人： The Board of Trustees of the University of Illinois
发明人： John A. Rogers , Matthew Meitl , Yugang Sun , Heung Cho Ko , Andrew Carlson , Won Mook Choi , Mark Stoykovich , Hanqing Jiang , Yonggang Huang , Ralph G. Nuzzo , Zhengtao Zhu , Etienne Menard , Dahl-Young Khang
IPC分类号： H01L29/12 , H01L27/12 , H01L21/8258 , H05K1/02 , H01L21/02 , H01L29/06 , H05K3/20
CPC分类号： H01L29/72 , H01L21/02422 , H01L21/02628 , H01L21/4846 , H01L21/8258 , H01L23/5387 , H01L27/12 , H01L29/0657 , H01L2924/12041 , H01L2924/13091 , H05K1/0283 , H05K3/20 , H05K3/22 , H05K2201/0133 , H05K2201/09045 , H05K2203/0271 , H01L2924/00
摘要： In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.
摘要翻译：一方面，本发明提供了拉伸，压缩，弯曲或其它变形时能够提供良好性能的可拉伸和可选择的可印刷的部件，例如半导体和电子电路，以及制造或调谐这种可拉伸部件的相关方法。对于一些应用而言，优选的可拉伸半导体和电子电路除了是可拉伸的之外是柔性的，因此能够沿着一个或多个轴显着地伸长，弯曲，弯曲或其它变形。此外，本发明的可拉伸半导体和电子电路适用于宽范围的器件配置，以提供完全灵活的电子和光电器件。

104. 发明申请

US20160086945A1 SEMICONDUCTOR DEVICE STRUCTURE WITH GATE SPACER HAVING PROTRUDING BOTTOM PORTION AND METHOD FOR FORMING THE SAME 有权
标题翻译：具有进气孔部分的带有间隙的半导体器件结构及其形成方法
公开(公告)号：US20160086945A1
公开(公告)日：2016-03-24
申请号：US14490888
申请日：2014-09-19
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
发明人： Yung-Tsun LIU
IPC分类号： H01L27/092 , H01L29/423 , H01L29/161 , H01L21/8258 , H01L29/26 , H01L29/66 , H01L21/441 , H01L21/465 , H01L29/78 , H01L29/08
CPC分类号： H01L21/823864 , H01L21/31111 , H01L21/31116 , H01L21/441 , H01L21/465 , H01L21/823814 , H01L21/8258 , H01L27/092 , H01L29/0649 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/26 , H01L29/4232 , H01L29/6656 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on the sidewall of the gate stack structure, and the gate spacers include a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate. The semiconductor device structure further includes an epitaxial structure formed adjacent to the gate spacers, and the epitaxial structure is formed below the gate spacers.
摘要翻译：提供了一种半导体器件结构及其形成方法。半导体器件结构包括形成在衬底上的衬底和栅叠层结构。半导体器件结构还包括形成在栅极堆叠结构的侧壁上的栅极间隔，并且栅极间隔物包括与顶部相邻的顶部和底部，并且底部部分倾斜到衬底的顶表面。半导体器件结构还包括与栅极间隔物相邻形成的外延结构，并且外部结构形成在栅极间隔物的下方。

105. 发明授权

US09236463B2 Compressive strained III-V complementary metal oxide semiconductor (CMOS) device 有权
公开(公告)号：US09236463B2
公开(公告)日：2016-01-12
申请号：US14027563
申请日：2013-09-16
申请人： GLOBALFOUNDRIES INC.
发明人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L29/778 , H01L29/423 , H01L29/66 , H01L21/8252 , H01L21/8258 , H01L21/84 , H01L27/06 , H01L27/12 , H01L29/10 , H01L29/205 , H01L29/20 , H01L29/51
CPC分类号： H01L29/778 , H01L21/8252 , H01L21/8258 , H01L21/845 , H01L27/0605 , H01L27/1211 , H01L29/1054 , H01L29/20 , H01L29/205 , H01L29/4232 , H01L29/51 , H01L29/518 , H01L29/66462 , H01L29/7787
摘要： A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.

106. 发明授权

US09236376B2 Power semiconductor device with oscillation prevention 有权
标题翻译：功率半导体器件具有防振功能
公开(公告)号：US09236376B2
公开(公告)日：2016-01-12
申请号：US14318458
申请日：2014-06-27
申请人： International Rectifier Corporation
发明人： Tony Bramian , Jason Zhang
IPC分类号： H01L27/088 , H01L27/085 , H01L21/8258 , H01L21/8236 , H01L29/16 , H01L29/20 , H01L29/78 , H01L27/06 , H01L25/18
CPC分类号： H01L27/085 , H01L21/8236 , H01L21/8258 , H01L25/18 , H01L27/0605 , H01L27/0883 , H01L29/16 , H01L29/2003 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： There are disclosed herein various implementations of composite semiconductor devices with active oscillation control. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device. The LV device may be configured to include one or both of a reduced output resistance due to, for example, a modified body implant and a reduced transconductance due to, for example, a modified oxide thickness to cause a gain of the composite semiconductor device to be less than approximately 10,000.
摘要翻译：这里公开了具有主动振荡控制的复合半导体器件的各种实现方式。在一个示例性实施方式中，正常关闭复合半导体器件包括通常为ON III族氮化物功率晶体管和与常规ON III族氮化物功率晶体管共同组成的低电压（LV）器件，以形成正常关闭复合半导体器件。 LV器件可以被配置为包括由于例如修改的体植入物引起的减小的输出电阻中的一个或两个，以及由于例如修改的氧化物厚度导致的复合半导体器件的增益的减小的跨导小于约10,000。

107. 发明授权

US09214461B2 GaN transistors with polysilicon layers for creating additional components 有权
标题翻译：具有多晶硅层的GaN晶体管用于产生额外的部件
公开(公告)号：US09214461B2
公开(公告)日：2015-12-15
申请号：US14445988
申请日：2014-07-29
申请人： Efficient Power Conversion Corporation
发明人： Jianjun Cao , Robert Beach , Alexander Lidow , Alana Nakata , Guangyuan Zhao , Yanping Ma , Robert Strittmatter , Michael A. De Rooji , Chunhua Zhou , Seshadri Kolluri , Fang Chang Liu , Ming-Kun Chiang , Jiali Cao , Agus Jauhar
IPC分类号： H01L29/778 , H01L29/66 , H01L27/085 , H01L29/40 , H01L21/8258 , H01L29/417 , H01L21/763 , H01L29/10 , H01L29/20
CPC分类号： H01L27/1207 , H01L21/763 , H01L21/8221 , H01L21/8258 , H01L27/085 , H01L29/04 , H01L29/1066 , H01L29/16 , H01L29/2003 , H01L29/402 , H01L29/41766 , H01L29/66462 , H01L29/7786 , H01L29/7787
摘要： A GaN transistor with polysilicon layers for creating additional components for an integrated circuit. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.
摘要翻译：具有多晶硅层的GaN晶体管，用于为集成电路产生附加元件。 GaN器件包括EPI结构和设置在EPI结构上的绝缘材料。此外，在多晶硅层具有一个或多个n型区域和p型区域的绝缘材料中设置一个或多个多晶硅层。该装置还包括设置在绝缘材料上的金属互连和设置在绝缘材料层中的通孔，其将源极和漏极金属连接到多晶硅层的n型和p型区域。

108. 发明授权

US09190474B2 Semiconductor device and method of manufacturing the device 有权
公开(公告)号：US09190474B2
公开(公告)日：2015-11-17
申请号：US14103155
申请日：2013-12-11
申请人： Panasonic Corporation
发明人： Noboru Negoro , Hidekazu Umeda , Nanako Hirashita , Tetsuzo Ueda
IPC分类号： H01L31/102 , H01L29/205 , H01L29/66 , H01L29/872 , H01L29/20 , H01L21/8258 , H01L27/06 , H01L29/04 , H01L29/47 , H01L29/778 , H01L21/02
摘要： A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals.

109. 发明申请

US20140342479A1 METHOD AND SYSTEM FOR TEMPLATE ASSISTED WAFER BONDING USING PEDESTALS 有权
标题翻译：使用PEDESTALS模板辅助波形粘结的方法和系统
公开(公告)号：US20140342479A1
公开(公告)日：2014-11-20
申请号：US14261276
申请日：2014-04-24
申请人： Skorpios Technologies, Inc.
发明人： Elton Marchena
IPC分类号： H01L21/8258 , H01S5/02 , H01L31/18 , H01L33/00 , H01L21/762 , H01S5/30
CPC分类号： H01L21/8258 , G02B6/13 , H01L21/76251 , H01L31/18 , H01L33/005 , H01S5/0215 , H01S5/3013
摘要： A method of fabricating a composite semiconductor structure includes providing a first substrate comprising a first material and having a first surface and forming a plurality of pedestals extending to a predetermined height in a direction normal to the first surface. The method also includes attaching a plurality of elements comprising a second material to each of the plurality of pedestals, providing a second substrate having one or more structures disposed thereon, and aligning the first substrate and the second substrate. The method further includes joining the first substrate and the second substrate to form the composite substrate structure and removing at least a portion of the first substrate from the composite substrate structure.
摘要翻译：制造复合半导体结构的方法包括提供包括第一材料并具有第一表面的第一基板，并且形成沿垂直于第一表面的方向延伸到预定高度的多个基座。该方法还包括将包括第二材料的多个元件附接到多个基座中的每一个，从而提供其上设置有一个或多个结构的第二基板，以及对准第一基板和第二基板。该方法还包括接合第一基板和第二基板以形成复合基板结构，并从复合基板结构去除第一基板的至少一部分。

110. 发明授权

US06965128B2 Structure and method for fabricating semiconductor microresonator devices 有权
标题翻译：制造半导体微谐振器器件的结构和方法
公开(公告)号：US06965128B2
公开(公告)日：2005-11-15
申请号：US10356549
申请日：2003-02-03
申请人： Paige M. Holm , Barbara Foley Barenburg , Joyce K. Yamamoto , Fred V. Richard
发明人： Paige M. Holm , Barbara Foley Barenburg , Joyce K. Yamamoto , Fred V. Richard
IPC分类号： H01L21/8258 , H01L27/01 , H01L27/06 , H01L33/00
CPC分类号： H01L27/0605 , H01L21/8258
摘要： High quality epitaxial layers of monocrystalline materials (26) can be grown overlying monocrystalline substrates (22) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer (24) comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy and epitaxial growth of single crystal silicon onto single crystal oxide materials. A microresonator device is formed overlying the monocrystalline substrate. Portions or an entirety of the microresonator device can also overly the accommodating buffer layer, or the monocrystalline material layer.
摘要翻译：通过形成用于生长单晶层的顺应性衬底，可以将单晶材料（26）的高质量外延层生长成覆盖在单晶衬底（22）如大硅晶片上。容纳缓冲层（24）包括通过氧化硅的非晶界面层（28）与硅晶片隔开的单晶氧化物层。非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。此外，顺应性衬底的形成可以包括利用表面活性剂增强的单晶硅在单晶氧化物材料上的外延和外延生长。在单晶衬底上形成微谐振器器件。部分或整个微谐振器装置也可以过度地容纳缓冲层或单晶材料层。

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