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101. 发明申请

US20090204755A1 MULTI-READER, MULTI-WRITER LOCK-FREE RING BUFFER 有权
公开(公告)号：US20090204755A1
公开(公告)日：2009-08-13
申请号：US12028091
申请日：2008-02-08
申请人： THOMAS BRYAN RUSHWORTH , ANGUS RICHARD TELFER
发明人： THOMAS BRYAN RUSHWORTH , ANGUS RICHARD TELFER
IPC分类号： G06F12/00
CPC分类号： G06F9/526 , G06F5/12 , G06F2205/123 , G06F2209/521
摘要： A method for accessing cells of a ring buffer by one or more writers, comprising: storing a current writer cell position value in each of a done writer index and a reserved writer index; storing a current reader cell position value in a done reader index; copying the current writer cell position value to an old writer variable of a writer of the one or more writers; assigning a trial next writer cell position value to a new writer variable of the writer; accepting the trial next writer cell position value if the trial next writer cell position value is not equal to the done reader index value; as a single operation, first, accepting the trial next writer cell position value as a next writer cell position value if the reserved writer index value is equal to the old writer variable value, and second, replacing the reserved writer index value with the new writer variable value; writing data by the writer to a cell of the ring buffer indicated by the next writer cell position value; and, when the done writer index value is equal to the old writer variable value, replacing the done writer index value with the new writer variable value; whereby the one or more writers are prevented from simultaneously accessing the cell of the ring buffer. In addition, a method for accessing cells of a ring buffer by one or more readers, comprising: storing a current reader cell position value in each of a done reader index and a reserved reader index; storing a current writer cell position value in a done writer index; copying the current reader cell position value to an old reader variable of a reader of the one or more readers; assigning a trial next reader cell position value to a new reader variable of the reader; accepting the trial next reader cell position value if the old reader variable value is not equal to the done writer index value; as a single operation, first, accepting the trial next reader cell position value as a next reader cell position value if the reserved reader index value is equal to the old reader variable value, and second, replacing the reserved reader index value with the new reader variable value; reading data by the reader from a cell of the ring buffer indicated by the next reader cell position value; and, when the done reader index value is equal to the old reader variable value, replacing the done reader index value with the new reader variable value; whereby the one or more readers are prevented from simultaneously accessing the cell of the ring buffer.

102. 发明申请

US20090133023A1 High Performance Queue Implementations in Multiprocessor Systems 失效
标题翻译：多处理器系统中的高性能队列实现
公开(公告)号：US20090133023A1
公开(公告)日：2009-05-21
申请号：US12087182
申请日：2005-12-29
申请人： Xiao-Feng Li , Dz-ching Ju
发明人： Xiao-Feng Li , Dz-ching Ju
IPC分类号： G06F9/46
CPC分类号： G06F9/526 , G06F5/12 , G06F9/546 , G06F2209/521
摘要： Systems and methods provide a single reader single writer (SRSW) queue structure having entries that can be concurrently accessed in an atomic manner with a single memory access. The SRSW queues may be combined to create more complicated queues, including multiple reader single writer (MRSW), single reader multiple writer (SRMW), and multiple reader multiple writer (MRMW) queues.
摘要翻译：系统和方法提供单个读写器单写入器（SRSW）队列结构，其具有可以以单一存储器访问以原子方式同时访问的条目。 SRSW队列可以被组合以创建更复杂的队列，包括多个读写器单写入器（MRSW），单个读取器多写入器（SRMW）和多个读取器多写入器（MRMW）队列。

103. 发明申请

US20080141063A1 Real time elastic FIFO latency optimization 审中-公开
标题翻译：实时弹性FIFO延时优化
公开(公告)号：US20080141063A1
公开(公告)日：2008-06-12
申请号：US11637592
申请日：2006-12-12
申请人： Curtis A. Ridgeway , Ravindra Viswanath , Rajinder Cheema
发明人： Curtis A. Ridgeway , Ravindra Viswanath , Rajinder Cheema
IPC分类号： G06F1/06
CPC分类号： G06F5/12 , G06F13/4059 , G06F2205/126
摘要： In some embodiments, a method for optimizing EFIFO latency may include one or more of the following steps: (a) counting each clock cycle from a read clock for a predetermined period of time, (b) counting each clock cycle from a write clock for a predetermined period of time, (c) comparing the counted read clock cycles to the write clock cycles to obtain a difference between the counted clock cycles, (d) adjusting a watermark for a queue based upon the difference between the counted clock cycles, (e) receiving a timeout signal, (f) terminating counting of the clock cycles of the read clock and write clock, and (g) initiating another optimization process after termination.
摘要翻译：在一些实施例中，用于优化EFIFO延迟的方法可以包括以下步骤中的一个或多个：（a）从预定时间段的读时钟计数每个时钟周期，（b）从写时钟计数每个时钟周期，（c）将计数的读取时钟周期与写入时钟周期进行比较以获得计数的时钟周期之间的差异，（d）基于计数的时钟周期之间的差异来调整队列中的水印， e）接收超时信号，（f）终止所述读时钟和写时钟的时钟周期的计数，以及（g）在终止之后启动另一优化处理。

104. 发明申请

US20070223265A1 Fifo Memory Device With Non-Volatile Storage Stage 有权
标题翻译：具有非易失性存储阶段的Fifo存储器件
公开(公告)号：US20070223265A1
公开(公告)日：2007-09-27
申请号：US10589114
申请日：2005-02-08
申请人： Andrei Radulescu
发明人： Andrei Radulescu
IPC分类号： G06F5/06
CPC分类号： G06F5/12
摘要： A FIFO memory device (300) comprises a storage device (321) which is a non-volatile FIFO comprising a plurality of non-volatile storage elements or latches. The FIFO memory device (300) also comprises an input stage (315) which is a volatile FIFO and comprises a plurality of volatile storage elements. The input stage (315) provides a temporary store for data and thus hides the latency of the storage device (321).
摘要翻译： FIFO存储器件（300）包括作为包括多个非易失性存储元件或锁存器的非易失性FIFO的存储设备（321）。 FIFO存储器件（300）还包括作为易失性FIFO并包括多个易失性存储元件的输入级（315）。输入级（315）为数据提供临时存储，从而隐藏存储设备（321）的等待时间。

105. 发明授权

US07234007B2 Adjustable elasticity FIFO buffer have a number of storage cells equal to a frequency offset times a number of data units in a data stream 有权
标题翻译：可调弹性FIFO缓冲器具有等于数据流中多个数据单元的频率偏移的多个存储单元
公开(公告)号：US07234007B2
公开(公告)日：2007-06-19
申请号：US10811126
申请日：2004-03-29
申请人： Andrew Castellano , Pinghua Peter Yang
发明人： Andrew Castellano , Pinghua Peter Yang
IPC分类号： G06F3/00 , G06F3/02 , G06F3/05
CPC分类号： G06F5/12 , G06F2205/063
摘要： A method of processing a data stream through a buffer is performed in accordance with a write clock and a read clock. The buffer has a plurality of sequentially numbered storage cells. The method includes the steps of selecting an initial preload value, with the selecting step including determining a product of the maximum frequency offset between the write and read clocks, and a maximum time between arbitrary symbols in the data stream. The storage cells then receive data units in response to a write pointer. Data units are then provided from the storage cells in response to a read pointer.
摘要翻译：根据写时钟和读时钟来执行通过缓冲器处理数据流的方法。缓冲器具有多个顺序编号的存储单元。该方法包括以下步骤：选择步骤包括确定写入和读取时钟之间的最大频率偏移的乘积以及数据流中的任意符号之间的最大时间。然后，存储单元响应于写指针接收数据单元。然后响应于读指针从存储单元提供数据单元。

106. 发明授权

US07212599B2 Jitter and wander reduction apparatus 有权
标题翻译：抖动和漫游减少装置
公开(公告)号：US07212599B2
公开(公告)日：2007-05-01
申请号：US10346550
申请日：2003-01-17
申请人： Ravi Subrahmanyan , Jeffrey W. Spires
发明人： Ravi Subrahmanyan , Jeffrey W. Spires
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40 , H03D3/24 , H04J3/06
CPC分类号： G06F5/12 , G06F2205/061 , H04J3/076
摘要： The present invention is for an apparatus that receives input data at a non-uniform first data rate carried by a system clock, and provides output data at a substantially uniform second data rate that is nominally equal to the first data rate and is also carried by the system clock. The system clock is faster than the first or second data rates and accordingly, a write enable signal controls the input data that is written into a saturating elastic store and a read enable signal controls the reading and output of data from the saturating elastic store. The saturating elastic store includes a plurality of storage locations and provides a storage fill level indicative of the amount of storage locations currently holding data. A digital filter receives the storage fill level and filters the storage fill level to provide a control word to a digitally controlled read enable signal generator. The digitally controlled read enable signal generator provides a read enable signal that is nominally the second data rate and that can be varied about the nominal second data rate in response to the control word. The digitally controlled read enable signal generator is able to vary the read enable signal rate by providing a plurality of stuff bit opportunities interspersed between the read enable signals. Some of these stuff bit opportunities are filled to set the read enable signal rate at the nominal second data rate value. By filling or not filling the stuff bit opportunities, the read enable signal rate can be adjusted over a narrow band of frequencies.
摘要翻译：本发明是用于以由系统时钟承载的不均匀的第一数据速率接收输入数据的装置，并且以基本均匀的第二数据速率提供输出数据，该数据速率名义上等于第一数据速率，并且还由系统时钟。系统时钟比第一或第二数据速率更快，因此，写入使能信号控制写入饱和弹性存储器的输入数据，并且读使能信号控制从饱和弹性存储器读取和输出数据。饱和弹性存储器包括多个存储位置，并且提供指示当前保存数据的存储位置的量的存储填充水平。数字滤波器接收存储器填充电平并对存储器填充电平进行滤波以向数字控制的读使能信号发生器提供控制字。数字控制的读使能信号发生器提供了名义上为第二数据速率的读使能信号，并且响应于控制字可以改变关于标称第二数据速率的读使能信号。数字控制读使能信号发生器能够通过提供散布在读使能信号之间的多个填充位机会来改变读使能信号速率。填充这些填充位的一些机会，以将读取使能信号速率设置在标称的第二数据速率值。通过填充或不填充填充位机会，可以在窄频带上调整读取使能信号速率。

107. 发明授权

US07130984B2 First-in first-out memory system with shift register fill indication 有权
公开(公告)号：US07130984B2
公开(公告)日：2006-10-31
申请号：US10726913
申请日：2003-12-03
申请人： Gary F. Chard , Osman Koyuncu , T-Pinn R. Koh , Christopher A. Opoczynski
发明人： Gary F. Chard , Osman Koyuncu , T-Pinn R. Koh , Christopher A. Opoczynski
IPC分类号： G06F12/00
CPC分类号： G06F5/12 , G06F5/14 , G06F2205/102 , G06F2205/106 , G06F2205/126
摘要： An electronic device (10). The device comprises a memory structure (12) comprising an integer M of word storage locations. The device further comprises a write shift register (SRWT) for storing a sequence of bits. The sequence in the write shift register comprises a number of bits equal to a ratio of 1/R1 times the integer M. The device further comprises circuitry (16) for providing a write clock cycle to the write shift register for selected write operations with respect to any of the word storage locations. In response to each write clock cycle, received from the circuitry for providing the write clock cycle, the write shift register shifts the sequence in the write shift register. Further, one bit in the sequence in the write shift register corresponds to an indication of one of the memory word storage locations into which a word will be written. The device further comprises a read shift register (SRRD) for storing a sequence of bits. The sequence in the read shift register comprises a number of bits equal to a ratio of 1/R2 times the integer M. The device further comprises circuitry (16) for providing a read clock cycle to the read shift register for selected read operations with respect to any of the word storage locations. In response to each read clock cycle, received from the circuitry for providing the read clock cycle, the read shift register shifts the sequence in the read shift register. Further, one bit in the sequence in the read shift register corresponds to an indication of one of the memory word storage locations from which a word will be read. Lastly, the device comprises circuitry (18x) for evaluating selected bits in the sequence in the write register relative to selected bits in the sequence in the read register for detecting a level of data fullness in the memory structure.

108. 发明授权

US07116599B1 High speed FIFO synchronous programmable full and empty flag generation 有权
标题翻译：高速FIFO同步可编程完整和空标志生成
公开(公告)号：US07116599B1
公开(公告)日：2006-10-03
申请号：US09957587
申请日：2001-09-20
申请人： Johnie Au , Chia Jen Chang , Parinda Mekara
发明人： Johnie Au , Chia Jen Chang , Parinda Mekara
IPC分类号： G11C7/00
CPC分类号： G06F5/12 , G06F2205/126
摘要： An apparatus comprising a flag generation circuit configured to generate a full flag signal in response to (i) a read clock signal, (ii) a write clock signal and (iii) a look ahead bitwise comparison configured to detect when a read count signal and a write count signal are equal.
摘要翻译：一种装置，包括标志产生电路，其被配置为响应于（i）读时钟信号，（ii）写时钟信号和（iii）前瞻比特比较，生成全标志信号，所述比较配置用于检测读计数信号和写计数信号相等。

109. 发明授权

US06978344B2 Shift register control of a circular elasticity buffer 失效
标题翻译：移位寄存器控制圆形弹性缓冲区
公开(公告)号：US06978344B2
公开(公告)日：2005-12-20
申请号：US10323104
申请日：2002-12-18
申请人： Steven Alnor Schauer
发明人： Steven Alnor Schauer
IPC分类号： G06F5/12 , G11C19/00 , G06F12/00
CPC分类号： G06F5/12 , G11C19/00
摘要： A shift register is provided to monitor the difference between the read and write pulses to an elasticity buffer. The shift register essentially eliminates the need for any math functions in the elasticity buffer management logic. The shift register is as wide as the elasticity buffer is deep. In other words, for every word in the elasticity buffer, the shift register has a corresponding bit. Each time a word is written into the elasticity buffer without a simultaneous corresponding read, a value of “1” is shifted from a first end into the shift register, indicating that a space has been taken in the elasticity buffer. For every word read out of the elasticity buffer without a simultaneous corresponding write, a value of “0” (zero) is shifted from a second end of the shift register, indicating that one more space is available. The elasticity buffer management logic need only monitor the shift register value to determine whether the elasticity buffer is nearly empty or nearly full, and if fill words need to be inserted or deleted.
摘要翻译：提供移位寄存器来监视读和写脉冲与弹性缓冲器之间的差异。移位寄存器基本上消除了对弹性缓冲器管理逻辑中的任何数学函数的需要。移位寄存器与弹性缓冲区一样宽。换句话说，对于弹性缓冲器中的每个字，移位寄存器都有一个相应的位。每当一个字被写入弹性缓冲器而没有同时对应的读取时，“1”的值从第一端移位到移位寄存器中，表示在弹性缓冲器中已经取得空间。对于从弹性缓冲器中读出的每个字，没有同时进行相应的写入，值“0”（零）从移位寄存器的第二端移位，表明还有一个空格可用。弹性缓冲器管理逻辑仅需要监视移位寄存器值，以确定弹性缓冲器是否几乎为空或接近满，如果填充字需要插入或删除。

110. 发明授权

US06772243B2 Apparatus and method for generating a partial fullness indicator signal in a FIFO 有权
标题翻译：用于在FIFO中产生部分饱和度指示符信号的装置和方法
公开(公告)号：US06772243B2
公开(公告)日：2004-08-03
申请号：US09742162
申请日：2000-12-19
申请人： Ian W. Jones , Josephus C. Ebergen
发明人： Ian W. Jones , Josephus C. Ebergen
IPC分类号： G06F300
CPC分类号： G06F5/08 , G06F5/12 , G06F2205/126
摘要： Techniques for indicating partial fullness levels of a FIFO comprising a plurality of stages using a partial fullness detector, such as a m-out-of-n detector. According to an embodiment, the m-out-of-n detector is coupled to “n” stages of the FIFO and configured to output a partial fullness indicator signal based on the full/empty states of the stages coupled to the m-out-of-n detector. The m-out-of-n detector may be configured to output the partial fullness indicator signal in a first state when “m” stages coupled to the m-out-of-n detector are full, and to output the partial fullness indicator signal in a second state when “m” stages coupled to the m-out-of-n detector are empty. The number of full stages of the FIFO lies in a first range when the m-out-of-n detector outputs the signal in the first state, and in a second range when the m-out-of-n detector outputs the signal in the second state. The bounds for the ranges may be determined based on factors such as the input and output rate characteristics of the FIFO. The m-out-of-n detector may be used to indicate partial fullness levels for various FIFOs including linear flow-through FIFOs, serial-concurrent-serial (SCS) FIFOs, and the like.
摘要翻译：用于使用诸如m-out-of-n检测器的部分饱和度检测器来指示包括多个级的FIFO的部分丰满度水平的技术。根据实施例，m-out-of-n检测器耦合到FIFO的“n”级，并且被配置为基于耦合到m-out-n的级的满/空状态来输出部分丰满度指示符信号，的n检测器。 m-out-of-n检测器可以被配置为当耦合到m-out-of-n检测器的“m”级满时，将部分丰满度指示符信号输出在第一状态，并且输出部分饱和度指示符信号在与m-out-of-n检测器耦合的“m”级为空时处于第二状态。当m-out-of-n检测器在第一状态下输出信号时，FIFO的全级数位于第一范围内，并且当m-out-of-n检测器输出信号时，在第二范围内第二个状态。范围的范围可以基于诸如FIFO的输入和输出速率特性的因素来确定。 m-out-of-n检测器可以用于指示包括线性流通FIFO，串行并发串行（SCS）FIFO等的各种FIFO的部分饱和度水平。

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