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101. 发明授权

US09981843B2 Chip package and a method of producing the same 有权
公开(公告)号：US09981843B2
公开(公告)日：2018-05-29
申请号：US15138313
申请日：2016-04-26
申请人： Infineon Technologies AG
发明人： Dominic Maier , Alfons Dehe , Thomas Kilger , Markus Menath , Franz Xaver Muehlbauer , Daniel Porwol , Juergen Wagner
IPC分类号： H01L29/84 , B81C1/00
CPC分类号： B81C1/00896 , B81C1/00269 , B81C1/00801 , B81C2201/0194 , B81C2201/053
摘要： A method of producing a chip package is described. A plurality of chips is provided on a first wafer. Each chip has a cavity which opens to a first main face of the chip. The cavities are filled or covered temporarily. The chips are then singulated. The singulated chips are embedded in an encapsulation material, and then the cavities are re-exposed.

102. 发明授权

US09938140B2 MEMS device and method of manufacturing a MEMS device 有权
公开(公告)号：US09938140B2
公开(公告)日：2018-04-10
申请号：US15206836
申请日：2016-07-11
申请人： Infineon Technologies AG
发明人： Alfons Dehe , Stephan Pindl , Bernhard Knott , Carsten Ahrens
IPC分类号： B81C1/00 , H04R19/04 , H04R19/00 , H04R31/00
CPC分类号： B81C1/00825 , B81B2201/0235 , B81B2201/0257 , B81B2201/0264 , B81C1/00873 , B81C2201/017 , B81C2201/053 , H04R19/005 , H04R19/04 , H04R31/00 , H04R2201/003
摘要： A method for manufacturing a MEMS device is disclosed. Moreover a MEMS device and a module including a MEMS device are disclosed. An embodiment includes a method for manufacturing MEMS devices includes forming a MEMS stack on a first main surface of a substrate, forming a polymer layer on a second main surface of the substrate and forming a first opening in the polymer layer and the substrate such that the first opening abuts the MEMS stack.

103. 发明授权

US09919912B2 Microelectronic component arrangement and production method for a microelectronic component arrangement 有权
公开(公告)号：US09919912B2
公开(公告)日：2018-03-20
申请号：US15273772
申请日：2016-09-23
申请人： Robert Bosch GmbH
发明人： Frederik Ante , Maximilian Amberger
IPC分类号： B64C1/22 , B81B3/00 , B81C1/00
CPC分类号： B81B3/0054 , B81B2201/0264 , B81B2207/098 , B81C1/00309 , B81C1/00333 , B81C2201/0167 , B81C2201/053 , H01L2224/27013
摘要： A microelectronic component arrangement includes a sensor and a carrier. The sensor has a detection surface and a region including contact elements situated at a first distance with respect to one another. The carrier includes a mounting surface, and the sensor is fixed on the carrier by the contact elements situated at a first distance with respect to one another at least regionally. The detection surface is opposite the mounting surface in a manner having a second distance with respect to the mounting surface. The contact elements are wetted by a mechanically stabilizing material, the region including the contact elements is enclosed by the mechanically stabilizing material, and the detection surface is free of the mechanically stabilizing material.

104. 发明申请

US20180002165A1 Protective Coating on Trench Features of a Wafer and Method of Fabrication Thereof 有权
公开(公告)号：US20180002165A1
公开(公告)日：2018-01-04
申请号：US15196395
申请日：2016-06-29
申请人： Akustica, Inc. , Robert Bosch GmbH
发明人： Mikko VA Suvanto
IPC分类号： B81B7/00 , B81C1/00 , H01L23/00
CPC分类号： B81B7/0058 , B81B2203/033 , B81C1/00404 , B81C1/00825 , B81C1/00896 , B81C2201/053 , H01L21/78 , H01L23/562
摘要： A coating for protecting a wafer from moisture and debris due to dicing, singulating, or handling the wafer is provided. A semiconductor sensor device comprises a wafer having a surface and at least one trench feature and the protective coating covering the trench feature. The trench feature comprises a plurality of walls and the walls are covered with the protective coating, wherein the walls of the trench feature are formed as a portion of the semiconductor sensor device. The semiconductor sensor device further comprises a patterned mask formed on the wafer before the trench feature is formed, wherein the protective coating is formed directly to the trench feature and the patterned mask. The semiconductor sensor device is selected from a group consisting of a MEMS die, a sensor die, a sensor circuit die, a circuit die, a pressure die, an accelerometer, a gyroscope, a microphone, a speaker, a transducer, an optical sensor, a gas sensor, a bolometer, a giant megnetoresistive sensor (GMR), a tunnel magnetoresistive (TMR) sensor, an environmental sensor, and a temperature sensor.

105. 发明授权

US09790082B1 CMOS and pressure sensor integrated on a chip and fabrication method 有权
公开(公告)号：US09790082B1
公开(公告)日：2017-10-17
申请号：US15271627
申请日：2016-09-21
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Lianjun Liu , Amitava Bose
IPC分类号： B81B3/00 , B81C1/00 , G01L9/00
CPC分类号： B81B3/0027 , B81B2201/0264 , B81B2207/015 , B81B2207/07 , B81C1/00246 , B81C2201/0132 , B81C2201/053 , B81C2203/0714 , B81C2203/075 , G01L9/0042 , G01L9/0045 , G01L9/0052 , G01L9/0054
摘要： A device comprises a silicon-on-insulator (SOI) substrate having first and second silicon layers with an insulator layer interposed between them. A structural layer, having a first conductivity type, is formed on the first silicon layer. A well region, having a second conductivity type opposite from the first conductivity type, is formed in the structural layer, and resistors are diffused in the well region. A metallization structure is formed over the well region and the resistors. A first cavity extends through the metallization structure overlying the well region and a second cavity extends through the second silicon layer, with the second cavity stopping at one of the first silicon layer and the insulator layer. The well region interposed between the first and second cavities defines a diaphragm of a pressure sensor. An integrated circuit and the pressure sensor can be fabricated concurrently on the SOI substrate using a CMOS fabrication process.

106. 发明授权

US09676609B2 Integrated MEMS device 有权
公开(公告)号：US09676609B2
公开(公告)日：2017-06-13
申请号：US15144896
申请日：2016-05-03
申请人： Asia Pacific Microsystems, Inc.
发明人： Jerwei Hsieh
IPC分类号： H01L21/4763 , B81B7/00 , B81C1/00
CPC分类号： B81B7/0038 , B81B7/0058 , B81B2201/032 , B81C1/00238 , B81C1/00817 , B81C1/00825 , B81C2201/053 , B81C2201/056 , B81C2203/0785
摘要： An integrated MEMS device is provided. The integrated MEMS device comprises a circuit chip and a device chip. The circuit chip has a patterned first bonding layer disposed thereon, the bonding layer being composed of a conductive material/materials. The device chip has a first structural layer and a second structural layer, the first structural layer being connected to the second structural layer and the first bonding layer of the circuit chip, and being sandwiched between the second structural layer and the circuit chip. A plurality of hermetic spaces are enclosed by the first structural layer, the second structural layer, the first bonding layer and the circuit chip.

107. 发明申请

US20170121172A1 INTEGRATED MEMS-CMOS DEVICES AND INTEGRATED CIRCUITS WITH MEMS DEVICES AND CMOS DEVICES 审中-公开
公开(公告)号：US20170121172A1
公开(公告)日：2017-05-04
申请号：US15405911
申请日：2017-01-13
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Jia Jie Xia , Nagarajan Ranganathan , Rakesh Kumar , Aveek Nath Chatterjee
IPC分类号： B81B7/00 , B81C1/00
CPC分类号： B81B7/007 , B81B2201/016 , B81B2201/0271 , B81B2207/015 , B81B2207/07 , B81C1/00246 , B81C1/00253 , B81C2201/013 , B81C2201/019 , B81C2201/053 , B81C2203/0735 , B81C2203/0771 , B81C2203/0792
摘要： Integrated MEMS-CMOS devices and integrated circuits with MEMS devices and CMOS devices are provided. An exemplary integrated MEMS-CMOS device is vertically integrated and includes a substrate having a first side and a second side opposite the first side. Further, the exemplary vertically integrated MEMS-CMOS device includes a CMOS device located in and/or over the first side of the substrate. Also, the exemplary vertically integrated MEMS-CMOS device includes a MEMS device located in and/or under the second side of the substrate.

108. 发明申请

US20170088412A1 Microelectronic Component Arrangement and Production Method for a Microelectronic Component Arrangement 有权
公开(公告)号：US20170088412A1
公开(公告)日：2017-03-30
申请号：US15273772
申请日：2016-09-23
申请人： Robert Bosch GmbH
发明人： Frederik Ante , Maximilian Amberger
IPC分类号： B81B3/00 , B81C1/00
CPC分类号： B81B3/0054 , B81B2201/0264 , B81B2207/098 , B81C1/00309 , B81C1/00333 , B81C2201/0167 , B81C2201/053 , H01L2224/27013
摘要： A microelectronic component arrangement includes a sensor and a carrier. The sensor has a detection surface and a region including contact elements situated at a first distance with respect to one another. The carrier includes a mounting surface, and the sensor is fixed on the carrier by the contact elements situated at a first distance with respect to one another at least regionally. The detection surface is opposite the mounting surface in a manner having a second distance with respect to the mounting surface. The contact elements are wetted by a mechanically stabilizing material, the region including the contact elements is enclosed by the mechanically stabilizing material, and the detection surface is free of the mechanically stabilizing material.

109. 发明申请

US20170044006A1 COMPOSITE CAVITY AND FORMING METHOD THEREOF 审中-公开
标题翻译：复合孔及其形成方法
公开(公告)号：US20170044006A1
公开(公告)日：2017-02-16
申请号：US15305799
申请日：2014-11-05
申请人： ADVANCED SEMICONDUCTOR MANUFACTURING CO. LTD
发明人： Yuanjun Xu , Yilin Yan , Weijia Xue
IPC分类号： B81B7/02 , B81C1/00
CPC分类号： B81B7/02 , B81B2201/0257 , B81B2203/0127 , B81B2203/0315 , B81C1/00158 , B81C1/00396 , B81C2201/0132 , B81C2201/0133 , B81C2201/019 , B81C2201/0198 , B81C2201/053
摘要： There is provided a method for forming a composite cavity and a composite cavity formed using the method. The method comprises the following steps: providing a silicon substrate (101); forming an oxide layer on the front side thereof; patterning the oxide layer to form one or more grooves (103), the position of the groove (103) corresponding to the position of small cavity (109) to be formed; providing a bonding wafer (104), which is bonded to the patterned oxide layer to form one or more closed micro-cavity structures (105) between the silicon substrate (101) and the bonding wafer (104); forming a protective film (106) over the bonding wafer (104) and forming a masking layer (107) on the back side of the silicon substrate (101); patterning the masking layer (107), the pattern of the masking layer (107) corresponding to the position of a large cavity (108) to be formed; using the masking layer (107) as a mask, etching the silicon substrate (101) from the back side until the oxide layer at the front side thereof to form the large cavity (108) in the silicon substrate (101); and using the masking layer (107) and the oxide layer as a mask, etching the bonding wafer (104) from the back side through the silicon substrate (101) until the protective film (106) thereover to form one or more small cavities (109) in the bonding wafer (104). The uniformity of thickness of the semiconductor medium layer where the small cavity (109) in the composite cavity is located is well controlled by the present invention.
摘要翻译：提供了使用该方法形成复合腔和复合腔的方法。该方法包括以下步骤：提供硅衬底（101）; 在其前侧形成氧化物层; 图案化氧化物层以形成一个或多个凹槽（103），凹槽（103）的位置对应于待形成的小空腔（109）的位置; 提供接合晶片（104），其接合到所述图案化氧化物层以在所述硅衬底（101）和所述接合晶片（104）之间形成一个或多个闭合微腔结构（105）; 在所述接合晶片（104）上形成保护膜（106），并在所述硅衬底（101）的背侧上形成掩模层（107）; 图案化掩模层（107），对应于待形成的大空腔（108）的位置的掩模层（107）的图案; 使用掩模层（107）作为掩模，从背面蚀刻硅衬底（101）直到其前侧的氧化物层在硅衬底（101）中形成大空腔（108）; 并且使用所述掩模层（107）和所述氧化物层作为掩模，通过所述硅衬底（101）从所述背面蚀刻所述接合晶片（104）直到所述保护膜（106）在其上形成一个或多个小空腔 109）。复合空腔中的小空腔（109）所在的半导体介质层的厚度均匀性由本发明很好地控制。

110. 发明授权

US09505609B2 CMOS-MEMS integrated device with selective bond pad protection 有权
标题翻译： CMOS-MEMS集成器件，具有选择性接合焊盘保护
公开(公告)号：US09505609B2
公开(公告)日：2016-11-29
申请号：US14699938
申请日：2015-04-29
申请人： InvenSense, Inc.
发明人： Daesung Lee
IPC分类号： B81C1/00
CPC分类号： B81C1/00801 , B81B7/0025 , B81B2207/07 , B81C2201/053 , B81C2203/0785
摘要： A method and system for preparing a semiconductor wafer are disclosed. In a first aspect, the method comprises providing a passivation layer over a patterned top metal on the semiconductor wafer, etching the passivation layer to open a bond pad in the semiconductor wafer using a first mask, depositing a protection layer on the semiconductor wafer, patterning the protective layer using a second mask, and etching the passivation layer to open other electrodes in the semiconductor wafer using a third mask. The system comprises a MEMS device that further comprises a first substrate and a second substrate bonded to the first substrate, wherein the second substrate is prepared by the aforementioned steps of the method.
摘要翻译：公开了一种用于制备半导体晶片的方法和系统。在第一方面，该方法包括在半导体晶片上的图案化的顶部金属上提供钝化层，蚀刻钝化层以使用第一掩模打开半导体晶片中的接合焊盘，在半导体晶片上沉积保护层，图案化使用第二掩模的保护层，并且使用第三掩模蚀刻钝化层以打开半导体晶片中的其它电极。该系统包括MEMS器件，其还包括第一基底和与第一基底结合的第二基底，其中第二基底是通过上述方法的步骤制备的。

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