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101. 发明申请

US20110147830A1 METHOD OF FORMING A SELF-ALIGNED CHARGE BALANCED POWER DMOS 有权
标题翻译：形成自对准电荷平衡功率DMOS的方法
公开(公告)号：US20110147830A1
公开(公告)日：2011-06-23
申请号：US12643837
申请日：2009-12-21
申请人： John Chen , Yeeheng Lee , Lingpeng Guan , Moses Ho , Wilson Ma , Anup Bhalla , Hamza Yilmaz
发明人： John Chen , Yeeheng Lee , Lingpeng Guan , Moses Ho , Wilson Ma , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/26586 , H01L29/0615 , H01L29/0634 , H01L29/0878 , H01L29/165 , H01L29/456 , H01L29/66719 , H01L29/78 , H01L29/7811
摘要： Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.
摘要翻译：公开了自对准电荷平衡半导体器件及其形成方法。在第一导电类型的半导体衬底上形成一个或多个平面栅极。在与平面栅极自对准的半导体中蚀刻一个或多个深沟槽。沟槽填充有第二导电类型的半导体材料，使得深沟槽与半导体衬底的相邻区域电荷平衡。该工艺可以形成具有小于12微米的电池间距的自对准电荷平衡装置。

102. 发明申请

US20110127602A1 Dual Channel Trench LDMOS Transistors and BCD Process with Deep Trench Isolation 有权
标题翻译：双通道沟槽LDMOS晶体管和具有深沟槽隔离的BCD工艺
公开(公告)号：US20110127602A1
公开(公告)日：2011-06-02
申请号：US12629844
申请日：2009-12-02
申请人： Shekar Mallikarjunaswamy
发明人： Shekar Mallikarjunaswamy
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/407 , H01L21/823412 , H01L21/823807 , H01L21/8249 , H01L27/0617 , H01L27/0623 , H01L27/092 , H01L29/0634 , H01L29/0649 , H01L29/0696 , H01L29/0821 , H01L29/0878 , H01L29/1095 , H01L29/408 , H01L29/4175 , H01L29/42356 , H01L29/4236 , H01L29/42368 , H01L29/732 , H01L29/7393 , H01L29/7813 , H01L29/7816 , H01L29/7817 , H01L29/7823 , H01L29/7825 , H01L29/7831
摘要： A dual channel trench LDMOS transistor includes a substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the first conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the second conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body region; a drain region of the second conductivity type spaced apart from the body region by a drain drift region. The planar gate forms a lateral channel in the body region, and the trench gate in the first trench forms a vertical channel in the body region of the LDMOS transistor.
摘要翻译：双通道沟槽LDMOS晶体管包括第一导电类型的衬底; 形成在所述基板上的第二导电类型的半导体层; 形成在所述半导体层中的沟槽栅极形成在所述第一沟槽的上部的第一沟槽; 形成在与所述第一沟槽相邻的所述半导体层中的所述第一导电类型的体区; 所述第二导电类型的源极区域形成在所述体区域中并且邻近所述第一沟槽; 覆盖身体区域的平面门; 所述第二导电类型的漏极区域通过漏极漂移区域与所述体区域间隔开。平面栅极在体区域中形成横向沟道，并且第一沟槽中的沟槽栅极在LDMOS晶体管的体区中形成垂直沟道。

103. 发明授权

US07951651B2 Dual flat non-leaded semiconductor package 有权
标题翻译：双平面无铅半导体封装
公开(公告)号：US07951651B2
公开(公告)日：2011-05-31
申请号：US12474089
申请日：2009-05-28
申请人： Kai Liu , Xiaotian Zhang , Ming Sun , Leeshawn Luo
发明人： Kai Liu , Xiaotian Zhang , Ming Sun , Leeshawn Luo
IPC分类号： H01L21/00
CPC分类号： H01L24/48 , H01L23/3107 , H01L23/4952 , H01L23/49562 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/45 , H01L24/49 , H01L24/83 , H01L2224/04042 , H01L2224/05555 , H01L2224/05556 , H01L2224/05599 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/48799 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/73265 , H01L2224/83801 , H01L2224/83851 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/0665 , H01L2924/00012
摘要： A DFN semiconductor package includes a leadframe having a die bonding pad formed integrally with a drain lead, a gate lead and a source lead, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead and a die gate bonding area coupled to the gate lead, and an encapsulant at least partially covering the die, drain lead, gate lead and source lead.
摘要翻译： DFN半导体封装包括引线框架，其具有与漏极引线，栅极引线和源极引线一体形成的管芯焊接焊盘，耦合到管芯焊接焊盘的管芯，耦合到源极引线的管芯源极接合区域和管芯栅极键合区域，以及密封剂，其至少部分地覆盖晶片，漏极引线，栅极引线和源极引线。

104. 发明申请

US20110014766A1 BOTTOM-DRAIN LDMOS POWER MOSFET STRUCTURE HAVING A TOP DRAIN STRAP 有权
标题翻译：底部排水LDMOS功率MOSFET结构具有顶部排水带
公开(公告)号：US20110014766A1
公开(公告)日：2011-01-20
申请号：US12891485
申请日：2010-09-27
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/0649 , H01L29/0653 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/41775 , H01L29/66659 , H01L29/7835
摘要： Lateral DMOS devices having improved drain contact structures and methods for making the devices are disclosed. A semiconductor device comprises a semiconductor substrate; an epitaxial layer on top of the substrate; a drift region at a top surface of the epitaxial layer; a source region at a top surface of the epitaxial layer; a channel region between the source and drift regions; a gate positioned over a gate dielectric on top of the channel region; and a drain contact trench that electrically connects the drift layer and substrate. The contact trench includes a trench formed vertically from the drift region, through the epitaxial layer to the substrate and filled with an electrically conductive drain plug; electrically insulating spacers along sidewalls of the trench; and an electrically conductive drain strap on top of the drain contact trench that electrically connects the drain contact trench to the drift region.
摘要翻译：公开了具有改进的漏极接触结构的侧面DMOS器件和用于制造器件的方法。半导体器件包括半导体衬底; 在衬底的顶部上的外延层; 位于外延层顶表面的漂移区; 在所述外延层的顶表面处的源极区; 源极和漂移区域之间的沟道区域; 栅极位于沟道区域顶部的栅极电介质上; 以及电连接漂移层和衬底的漏极接触沟槽。接触沟槽包括从漂移区垂直形成的沟槽，穿过外延层到衬底并填充有导电排放塞; 沿沟槽侧壁的电绝缘垫片; 以及在漏极接触沟槽的顶部上的导电漏极带，其将漏极接触沟槽电连接到漂移区域。

105. 发明授权

US07867852B2 Super-self-aligned trench-dmos structure and method 有权
标题翻译：超自对准沟槽dmos结构和方法
公开(公告)号：US07867852B2
公开(公告)日：2011-01-11
申请号：US12189062
申请日：2008-08-08
申请人： François Hébert
发明人： François Hébert
IPC分类号： H01L21/336
CPC分类号： H01L29/66734 , H01L21/2257 , H01L29/04 , H01L29/0865 , H01L29/0869 , H01L29/41766 , H01L29/456 , H01L29/66727 , H01L29/7813
摘要： A semiconductor device includes a P-body layer formed in an N-epitaxial layer; a gate electrode formed in a trench in the P-body and N-epitaxial layer; a top source region formed from the P-body layer next to the gate electrode; a gate insulator disposed along a sidewall of the gate electrode between the gate electrode and the source, between the gate electrode and the P-body and between the gate electrode and the N-epitaxial layer; a cap insulator disposed on top of the gate electrode; and an N+ doped spacer disposed along a sidewall of the source and a sidewall of the gate insulator. The source includes N+ dopants diffused from the spacer. A body contact region containing P-type dopants is formed from the N-epitaxial layer. The contact region touches one or more P-doped regions of the P-body layer and the source. Methods for manufacturing such a device are also disclosed. Embodiments of this invention may also be applied to P-channel devices.
摘要翻译：半导体器件包括形成在N外延层中的P体层; 形成在P体和N外延层中的沟槽中的栅电极; 由栅极电极旁边的P体层形成的顶部源极区域; 沿着栅电极的侧壁设置在栅电极和源极之间，栅电极和P体之间以及栅电极和N外延层之间的栅极绝缘体; 设置在所述栅电极的顶部的盖绝缘体; 以及沿着源极的侧壁和栅极绝缘体的侧壁设置的N +掺杂的间隔物。源包括从间隔物扩散的N +掺杂剂。由N型外延层形成含有P型掺杂剂的体接触区域。接触区域接触P体层和源的一个或多个P掺杂区域。还公开了制造这种装置的方法。本发明的实施例也可以应用于P沟道器件。

106. 发明申请

US20110001187A1 Configurations and methods for manufacturing charge balanced devices 有权
标题翻译：制造电荷平衡装置的配置和方法
公开(公告)号：US20110001187A1
公开(公告)日：2011-01-06
申请号：US12807116
申请日：2010-08-26
申请人： François Hébert
发明人： François Hébert
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0623 , H01L29/0634 , H01L29/0873 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/66734
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件，半导体衬底具有多个深沟槽。深沟槽填充有外延层，从而形成覆盖半导体衬底上的深沟槽顶表面上方的区域的顶部外延层。半导体功率器件还包括设置在顶部外延层中的多个晶体管单元，由此半导体功率器件的器件性能取决于深沟槽的深度，而不依赖于顶部外延层的厚度。多个晶体管单元中的每一个包括沟槽DMOS晶体管单元，其沟槽栅极通过顶部外延层开口并且填充有栅极电介质材料。

107. 发明申请

US20100320461A1 INTEGRATION OF SENSE FET INTO DISCRETE POWER MOSFET 有权
标题翻译：将感应FET集成到分立功率MOSFET中
公开(公告)号：US20100320461A1
公开(公告)日：2010-12-23
申请号：US12870489
申请日：2010-08-27
申请人： Yi Su , Anup Bhalla
发明人： Yi Su , Anup Bhalla
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/7815 , H01L21/8234 , H01L27/088 , H01L29/0646 , H01L29/0653 , H01L29/0696 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs. A transistor portion of the sense FET is surrounded by transistors of the main FET. An electrical isolation structure that surrounds the main FET is configured to electrically isolate source and body regions of the main FET from source and body regions of the sense FET. A sense FET source pad is located at an edge of the main FET and spaced apart from the transistor portion of the sense FET. The sense FET source pad is connected to the transistor portion of the sense FET by a sense FET probe metal. The isolation structure is configured such that the transistor portion of the sense FET and the sense FET source pad are located outside an active area of the main FET.
摘要翻译：半导体器件包括主场效应晶体管（FET）和一个或多个感测FET。感测FET的晶体管部分被主FET的晶体管包围。围绕主FET的电隔离结构被配置为将主FET的源极和主体区域与感测FET的源极和体区电气隔离。感测FET源极焊盘位于主FET的边缘并与感测FET的晶体管部分间隔开。感测FET源极焊盘通过感测FET探针金属连接到感测FET的晶体管部分。隔离结构被配置为使得感测FET和感测FET源极焊盘的晶体管部分位于主FET的有效区域之外。

108. 发明授权

US07851314B2 Short channel lateral MOSFET and method 有权
标题翻译：短沟横向MOSFET及方法
公开(公告)号：US07851314B2
公开(公告)日：2010-12-14
申请号：US12112120
申请日：2008-04-30
申请人： Shekar Mallikarjunaswamy , Amit Paul
发明人： Shekar Mallikarjunaswamy , Amit Paul
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/26513 , H01L21/26586 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66681 , H01L29/7816 , H01L2924/0002 , H01L2924/00
摘要： A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.
摘要翻译：公开了一种短沟道横向MOSFET（LMOS）和方法，其具有用于降低通道导通电阻同时保持高穿透电压的互穿漏极体突起（IDBP）。 LMOS包括较低的器件体积层; 上部源极和上部漏极区域位于下部器件体层的顶部; 上部源极和上部漏极区都与下部器件本体层之间的中间上部区域接触; 上排水区和上体区均形成排水体界面; 排水体接口具有IDBP结构，其中表面排出突起位于掩埋体突起的顶部，同时露出上身体区域的顶部体表面积; 栅极氧化物栅极电极双层，其设置在形成LMOS的上部主体区域的顶部，其具有由在上部源区域和上部漏极区域之间描绘的顶部体表面积的水平长度限定的短沟道长度。

109. 发明授权

US07786837B2 Semiconductor power device having a stacked discrete inductor structure 有权
标题翻译：具有层叠离散电感器结构的半导体功率器件
公开(公告)号：US07786837B2
公开(公告)日：2010-08-31
申请号：US11818219
申请日：2007-06-12
申请人： François Hébert
发明人： François Hébert
IPC分类号： H01F5/00 , H01F27/06 , H01F27/02 , H01F27/29 , H01L23/48 , G05F1/00
CPC分类号： H01F27/292 , H01F17/0013 , H01F17/045 , H01F27/40 , H01F2007/1822 , H01L23/645 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/81 , H01L24/85 , H01L25/072 , H01L2224/0401 , H01L2224/05553 , H01L2224/16225 , H01L2224/16235 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48472 , H01L2224/48799 , H01L2224/49111 , H01L2224/49171 , H01L2224/81801 , H01L2224/85 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10162 , H01L2924/12032 , H01L2924/1306 , H01L2924/14 , H01L2924/1461 , H01L2924/15173 , H01L2924/15174 , H01L2924/1532 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19107 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A power device includes a discrete inductor having contacts formed on a first surface of the discrete inductor and at least one semiconductor component mounted on the first surface of the discrete inductor and coupled to the contacts. The discrete inductor further includes contacts formed on a second surface opposite the first surface and routing connections connecting the first surface contacts to corresponding second surface contacts. The semiconductor components may be flip chip mounted onto the discrete inductor contacts or wire bonded thereto.
摘要翻译：功率器件包括具有形成在分立电感器的第一表面上的触点和安装在离散电感器的第一表面上并耦合到触点的至少一个半导体部件的分立电感器。离散电感器还包括形成在与第一表面相对的第二表面上的触点和将第一表面触点连接到对应的第二表面触点的路由连接。半导体部件可以倒装芯片安装到分立的电感器触头上或与之结合的引线上。

110. 发明申请

US20100133644A1 Bottom anode Schottky diode structure and method 有权
标题翻译：底部阳极肖特基二极管的结构和方法
公开(公告)号：US20100133644A1
公开(公告)日：2010-06-03
申请号：US12653345
申请日：2009-12-11
申请人： Francois Hébert
发明人： Francois Hébert
IPC分类号： H01L29/872 , H01L21/30
CPC分类号： H01L29/872 , H01L29/402 , H01L29/66143 , H01L29/861 , H01L2924/0002 , H01L2924/00
摘要： This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as a Schottky anode. The BAS diode further includes a lateral cathode region extended laterally from a cathode electrode near a top surface of the semiconductor substrate opposite the Schottky barrier metal wherein the lateral cathode region doped with an opposite dopant from the sinker dopant region and interfacing the sinker dopant region whereby a current path is formed from the cathode electrode to the anode electrode through the lateral cathode region and the sinker dopant region in applying a forward bias voltage and the sinker dopant region depleting the cathode region in applying a reverse bias voltage for blocking a leakage current.
摘要翻译：本发明公开了一种底阳极肖特基（BAS）二极管，其包括设置在半导体衬底的底表面上的阳极电极。底部阳极肖特基二极管还包括设置在半导体衬底中的深度处的沉降片掺杂剂区域，其基本上延伸到设置在半导体底表面上的阳极电极和由用作肖特基的埋地肖特基势垒金属覆盖的沉降弧掺杂区域阳极。 BAS二极管进一步包括从阴极延伸到靠近半导体衬底的与肖特基势垒金属相对的顶表面的横向阴极区域，其中侧向阴极区域掺杂有与沉降弧掺杂区域相反的掺杂剂，并且与沉淀弧掺杂区域接合，由此在施加正偏压时，通过横向阴极区和沉降弧掺杂区形成电流路径，并且在施加用于阻断泄漏电流的反向偏置电压时消耗阴极区的沉降掺杂区。

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