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101. 发明授权

US06864568B2 Packaging device for holding a plurality of semiconductor devices to be inspected 失效
标题翻译：用于保持待检查的多个半导体器件的封装装置
公开(公告)号：US06864568B2
公开(公告)日：2005-03-08
申请号：US10252546
申请日：2002-09-24
申请人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
发明人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
IPC分类号： G01R31/26 , G01R1/04 , G01R1/073 , H01L21/66 , H01L23/02
CPC分类号： G01R1/0483 , H01L2924/0002 , H01L2924/00
摘要： A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.
摘要翻译：一种用于在其上保持要检查的多个待检查的半导体器件的封装装置，包括：电连接到每个半导体器件的电极的探针，包括：用于分别接收半导体器件中的可分离地接收的孔，以保持位置半导体器件之间的关系以及在与半导体器件的厚度方向垂直的方向上半导体器件之间的间隔恒定的封装器件和每个半导体器件之间的位置关系以及适于分别连接的导电部件并且延伸到包装装置的外部，使得探针连接到每个导电构件。

102. 发明申请

US20050029674A1 Multi-chip module 失效
标题翻译：多芯片模块
公开(公告)号：US20050029674A1
公开(公告)日：2005-02-10
申请号：US10919331
申请日：2004-08-17
申请人： Atsushi Kazama , Akihiro Yaguchi , Hideo Miura , Asao Nishimura
发明人： Atsushi Kazama , Akihiro Yaguchi , Hideo Miura , Asao Nishimura
IPC分类号： H01L23/31 , H01L23/48 , H01L25/065 , H01L25/10
CPC分类号： H01L23/3157 , H01L23/3114 , H01L23/3171 , H01L24/10 , H01L24/13 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L25/105 , H01L2224/05599 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2225/1005 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10329 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.
摘要翻译：多芯片模块具有至少两个半导体芯片。每个半导体芯片具有半导体芯片的芯片电极，用于与芯片电极电连接的导电互连，用于与互连电连接的导电焊盘，设置在焊盘上的外部端子以及介于两者之间的应力松弛层土地和半导体芯片。半导体芯片通过外部端子放置在安装板上。第一半导体芯片的应力松弛层厚于第二半导体芯片的应力松弛层，该第二半导体芯片的距离其中心至位于其最外端部分的外部端子的距离小于第一半导体芯片的应力松弛层。

103. 发明申请

US20050006751A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20050006751A1
公开(公告)日：2005-01-13
申请号：US10909402
申请日：2004-08-03
申请人： Hiroya Shimizu , Asao Nishimura , Toshiho Miyamoto , Hideki Tanaka , Hideo Miura
发明人： Hiroya Shimizu , Asao Nishimura , Toshiho Miyamoto , Hideki Tanaka , Hideo Miura
IPC分类号： H01L21/3205 , H01L21/60 , H01L21/822 , H01L23/50 , H01L23/52 , H01L23/552 , H01L23/64 , H01L23/66 , H01L27/04 , H01L27/14
CPC分类号： H01L24/10 , H01L23/50 , H01L23/5286 , H01L23/552 , H01L23/645 , H01L23/66 , H01L24/13 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05569 , H01L2224/05571 , H01L2224/05572 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device including a semiconductor element having external terminals at a first level and external electrodes at a second level, higher than the first level. The external terminals include power terminals, ground terminals and signal terminals formed on a main surface of the semiconductor element. The external electrodes include power electrodes connected to the power terminals via power connecting sections, ground electrodes connected to the ground terminals via ground connecting sections and signal electrodes connected to the signal terminals via signal connecting sections. One of the signal terminals, signal electrodes and corresponding signal connecting sections are surrounded by either the power connecting sections connecting the power terminals and power electrodes or by the ground connection sections connecting the ground terminals and ground electrodes.
摘要翻译：一种半导体器件，包括具有第一电平的外部端子和高于第一电平的第二电平的外部电极的半导体元件。外部端子包括形成在半导体元件的主表面上的电源端子，接地端子和信号端子。外部电极包括通过电源连接部分连接到电源端子的电力电极，经由接地连接部分连接到接地端子的接地电极和经由信号连接部分连接到信号端子的信号电极。信号端子，信号电极和相应的信号连接部分之一被连接电源端子和电源电极的电源连接部分或连接接地端子和接地电极的接地连接部分包围。

104. 发明授权

US06620704B2 Method of fabricating low stress semiconductor devices with thermal oxide isolation 失效
标题翻译：制造具有热氧化隔离的低应力半导体器件的方法
公开(公告)号：US06620704B2
公开(公告)日：2003-09-16
申请号：US09893980
申请日：2001-06-29
申请人： Hideo Miura , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
发明人： Hideo Miura , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
IPC分类号： H01L2176
CPC分类号： H01L21/76205 , H01L21/76202 , H01L27/0802
摘要： A method is provided of fabricating a semiconductor device that includes forming a silicon oxide film on a semiconductor substrate. A silicon nitrite film may be formed on the silicon oxide film. A portion of the silicon nitrite film and the silicon oxide film may be removed at a desired portion. Additionally, a groove may be formed in the semiconductor substrate in the portion in which the silicon oxide film is removed. A part of the silicon oxide film may be etched back around the groove with hydrofluoric acid type at the portion in which the silicon nitrite film is located above. Additionally, an oxidized film may be formed in the groove of the semiconductor substrate and the groove may be oxidized.
摘要翻译：提供一种制造半导体器件的方法，该半导体器件包括在半导体衬底上形成氧化硅膜。可以在氧化硅膜上形成亚硝酸硅膜。可以在期望的部分去除一部分亚硝酸硅膜和氧化硅膜。此外，可以在除去氧化硅膜的部分中的半导体衬底中形成沟槽。氧化硅膜的一部分可以在硅亚硝酸盐膜位于上方的部分用氢氟酸型蚀刻回到槽周围。此外，可以在半导体衬底的沟槽中形成氧化膜，并且可以使沟槽被氧化。

105. 发明授权

US06614246B1 Probe structure 失效
标题翻译：探头结构
公开(公告)号：US06614246B1
公开(公告)日：2003-09-02
申请号：US09648452
申请日：2000-08-28
申请人： Ryuji Kohno , Tatsuya Nagata , Hiroya Shimizu , Toshio Miyatake , Hideo Miura
发明人： Ryuji Kohno , Tatsuya Nagata , Hiroya Shimizu , Toshio Miyatake , Hideo Miura
IPC分类号： G01R1073
CPC分类号： G01R1/07378
摘要： The invention provides a probe structure in which secondary electrodes of a main base material in which probes are formed can be electrically connected to electrodes in a substrate side even when a lot of probes are formed in a large area, so that a lot of LSIs within a wafer can be tested in one lot in a wafer test process, whereby an efficiency of the test process can be improved. In the probe structure, an interposer constituted by a high rigid material is arranged between the main base material having the probes formed therein and the substrate side, and the secondary electrodes of the main base material having the probes formed therein are electrically connected to the electrodes in the substrate side via the interposer.
摘要翻译：本发明提供了一种探针结构，其中形成探针的主要基底材料的二次电极即使在大面积形成大量探针的情况下也可以与衬底侧的电极电连接，从而使大量的LSIs 可以在晶片测试过程中一次性地测试晶片，从而可以提高测试过程的效率。在探针结构中，由具有高刚性材料的插入体配置在其中形成有探针的主基材和基板侧之间，并且其中形成有探针的主基材的二次电极电连接到电极在基板侧经由插入件。

106. 发明授权

US06476492B2 Semiconductor device having a capacitor and an interconnect layer with molybdenum-containing tungsten 失效
标题翻译：具有电容器的半导体器件和具有含钼钨的互连层
公开(公告)号：US06476492B2
公开(公告)日：2002-11-05
申请号：US09758288
申请日：2001-01-12
申请人： Tomio Iwasaki , Hideo Miura , Takashi Nakajima , Hiroyuki Ohta , Shinji Nishihara , Masashi Sahara
发明人： Tomio Iwasaki , Hideo Miura , Takashi Nakajima , Hiroyuki Ohta , Shinji Nishihara , Masashi Sahara
IPC分类号： H01L2348
CPC分类号： H01L23/53257 , H01L27/10814 , H01L27/10894 , H01L28/55 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device, which comprises a capacitor component comprising a first electrode, an oxide film with a high dielectric constant or ferroelectricity in contact with the first electrode and a second electrode in contact with the oxide film, as formed in this order, on one principal side of a silicon substrate with a metal wiring layer formed thereon, such problems as breaking of tungsten interconnect, lowering of reliability, lowering of yield, etc. of semi-conductor devices can be solved by using molybdenum-containing tungsten as the material of metal interconnect layer.
摘要翻译：在包括第一电极的电容器组件，具有高介电常数或与第一电极接触的铁电性的氧化膜和与该氧化物膜接触的第二电极的电容器组件中，在其上形成有金属布线层的硅衬底的主面上，通过使用含钼钨作为材料，可以解决半导体器件的钨互连断裂，可靠性降低，成品率降低等问题金属互连层。

107. 发明授权

US06465264B1 Method for producing semiconductor device and apparatus usable therein 失效
标题翻译：用于制造半导体器件的方法和可用于其中的装置
公开(公告)号：US06465264B1
公开(公告)日：2002-10-15
申请号：US09654612
申请日：2000-09-01
申请人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
发明人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
IPC分类号： G01R3126
CPC分类号： G01R1/0483 , H01L2924/0002 , H01L2924/00
摘要： A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.
摘要翻译：一种用于在其上保持要检查的多个待检查的半导体器件的封装装置，包括：电连接到每个半导体器件的电极的探针，包括：用于分别接收半导体器件中的可分离地接收的孔，以保持位置半导体器件之间的关系以及在与半导体器件的厚度方向垂直的方向上半导体器件之间的间隔恒定的封装器件和每个半导体器件之间的位置关系以及适于分别连接的导电部件并且延伸到包装装置的外部，使得探针连接到每个导电构件。

108. 发明授权

US06265784B1 Resin sealed semiconductor device having improved arrangement for reducing thermal stress within the device 有权
标题翻译：树脂密封的半导体器件具有改进的装置，用于降低装置内的热应力
公开(公告)号：US06265784B1
公开(公告)日：2001-07-24
申请号：US09437266
申请日：1999-11-10
申请人： Kenya Kawano , Hiroaki Doi , Akio Yasukawa , Hideo Miura
发明人： Kenya Kawano , Hiroaki Doi , Akio Yasukawa , Hideo Miura
IPC分类号： H01L2300
CPC分类号： H01L21/563 , H01L24/32 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/73257 , H01L2224/83859 , H01L2224/83951 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01039 , H01L2924/0105 , H01L2924/01082 , H01L2924/01087 , H01L2924/14 , H01L2924/15787 , H01L2924/351 , H01L2924/00 , H01L2924/3512 , H01L2224/05599
摘要： A resin sealed semiconductor device is provided with an organic resin wiring substrate, an LSI chip having a semiconductor integrated circuit and mounted in a bare chip package form to the organic resin wiring substrate through a plurality of electrical bonding members, and a resin charged into a gap portion between the organic resin wiring substrate and the LSI chip. In this resin sealed semiconductor device, a modulus of longitudinal elasticity of the resin to be charged, its coefficient of linear thermal expansion and its fillet shape are optimized. The resin charged is also preferably colored in black to minimize adverse effects of visible rags on the LSI chip.
摘要翻译：树脂密封半导体器件具有有机树脂布线基板，具有半导体集成电路的LSI芯片，并且通过多个电接合部件以裸芯片封装形式安装到有机树脂布线基板，并且将树脂装入有机树脂布线基板和LSI芯片之间的间隙部分。在这种树脂密封半导体器件中，优化被充电树脂的纵向弹性模量，线性热膨胀系数和圆角形状。充电的树脂还优选用黑色着色，以尽可能减少LSI芯片上的可见抹布的不良影响。

109. 外观设计

USD400903S LCD projector 失效
公开(公告)号：USD400903S
公开(公告)日：1998-11-10
申请号：US80673
申请日：1997-12-03
申请人： Toshihiko Miyagawa , Hideo Miura , Yukihiko Oota , Mikiya Shimizu , Koichi Harada , Naoto Fukasawa
设计人： Toshihiko Miyagawa , Hideo Miura , Yukihiko Oota , Mikiya Shimizu , Koichi Harada , Naoto Fukasawa

110. 外观设计

USD392302S Liquid crystal projector 失效
公开(公告)号：USD392302S
公开(公告)日：1998-03-17
申请号：US62904
申请日：1996-12-02
申请人： Yukihiko Oota , Yoshinari Horimoto , Hideo Miura
设计人： Yukihiko Oota , Yoshinari Horimoto , Hideo Miura

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