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101. 发明申请

US20100038697A1 NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT 失效
标题翻译：非易失性双向晶体管可编程逻辑单元和阵列布局
公开(公告)号：US20100038697A1
公开(公告)日：2010-02-18
申请号：US12370828
申请日：2009-02-13
申请人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , William C. Plants , Zhigang Wang
发明人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , William C. Plants , Zhigang Wang
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L27/11524 , H01L27/0203 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11526 , H01L27/11529 , H01L29/7881
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
摘要翻译：在半导体本体中形成双晶体管非易失性存储单元。记忆晶体管阱设置在半导体本体内。开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

102. 发明申请

US20090159954A1 NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT 有权
公开(公告)号：US20090159954A1
公开(公告)日：2009-06-25
申请号：US12359481
申请日：2009-01-26
申请人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
发明人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/0203 , H01L21/823493 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

103. 发明申请

US20090052015A1 METHOD FOR ACQUIRING SPECTRUM SHAPE OF A GAIN FLATTENING FILTER IN AN OPTICAL AMPLIFIER 失效
标题翻译：在光放大器中获取增益滤光片的光谱形状的方法
公开(公告)号：US20090052015A1
公开(公告)日：2009-02-26
申请号：US12195864
申请日：2008-08-21
申请人： Zhigang Wang , Aihua Yu
发明人： Zhigang Wang , Aihua Yu
IPC分类号： H01S3/00
CPC分类号： H01S3/06754 , H01S3/0014 , H01S3/1616 , H01S2301/04
摘要： A method for acquiring spectrum shape of a gain flattening filter of a doped optical fiber amplifier comprises the steps of: measuring spectrum shapes at two gain point (H, L) of the doped optical fiber with invariable fiber length respectively; and acquiring various gain spectrums of the doped optical fiber with various fiber length and various population inversion level according to an expression: ErGain(λ,x,L′)=[ErLGain(λ)+[ErHGain(λ)−ErLGain(λ)]*x]*L′, Wherein Gain(λ) refers to the spectral function of gain, x is Δ′inv/Δinv which refers to change of population inversion level, and L′ is set as proportion of doped fiber length. Gain spectrums of the doped optical fiber with various fiber length can be acquired by measuring spectrum shapes at two gain point (H, L) of the doped optical fiber in invariable fiber length and applying change rule of gain spectrum of the doped optical fiber in different population inversion level, which improves the flexibility for design of amplifier.
摘要翻译：一种用于获取掺杂光纤放大器的增益平坦滤波器的光谱形状的方法，包括以下步骤：分别测量具有不变光纤长度的掺杂光纤的两个增益点（H，L）处的光谱形状; 并且根据以下表达式获取具有各种光纤长度和各种总体反转电平的掺杂光纤的各种增益光谱：<？in-line-formula description =“In-line Formulas”end =“lead”？> ErGain（λ， x，L'）= [ErLGain（lambda）+ [ErHGain（lambda）-ErLGain（lambda）] * x] * L'，<？in-line-formula description =“In-line Formulas”end =“tail” ？>其中增益（lambda）是指增益的光谱函数，x是Delta'inv / Deltainv，其指的是群体反转级别的变化，L'被设置为掺杂光纤长度的比例。通过以不变的光纤长度测量掺杂光纤的两个增益点（H，L）处的光谱形状，并将掺杂光纤的增益光谱的变化规则应用于不同的光纤中，可以获得具有各种光纤长度的掺杂光纤的增益谱人口反演水平提高了放大器设计的灵活性。

104. 发明授权

US07418683B1 Constraint assistant for circuit design 有权
标题翻译：电路设计约束助手
公开(公告)号：US07418683B1
公开(公告)日：2008-08-26
申请号：US11233809
申请日：2005-09-21
申请人： Jean-Daniel Sonnard , Zhigang Wang , Hemanth Sampath
发明人： Jean-Daniel Sonnard , Zhigang Wang , Hemanth Sampath
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/74
摘要： A computer aided design tool and method for designing IC layouts by recommending subcircuit layout constraints based upon an automated identification from a circuit schematic of subcircuit types requiring special IC layout constraints. Subcircuit types are identified on the basis of netlist examination, as well as cues from the layout of the circuit schematic.
摘要翻译：一种用于设计IC布局的计算机辅助设计工具和方法，其通过基于需要特殊IC布局约束的子电路类型的电路原理图的自动识别来推荐子电路布局约束。基于网表检查的子电路类型，以及电路原理图布局的线索。

105. 发明申请

US20070215935A1 NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT 失效
标题翻译：非易失性双向晶体管可编程逻辑单元和阵列布局
公开(公告)号：US20070215935A1
公开(公告)日：2007-09-20
申请号：US11750650
申请日：2007-05-18
申请人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
发明人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/0203 , H01L21/823493 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
摘要翻译：在半导体本体中形成双晶体管非易失性存储单元。记忆晶体管阱设置在半导体本体内。开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

106. 发明申请

US20050230272A1 Porous biosensing device 审中-公开
标题翻译：多孔生物传感器
公开(公告)号：US20050230272A1
公开(公告)日：2005-10-20
申请号：US11035431
申请日：2005-01-14
申请人： Gil Lee , Jin-Won Park , Zhigang Wang
发明人： Gil Lee , Jin-Won Park , Zhigang Wang
IPC分类号： G01N27/26 , G01N33/00 , G01N33/543 , G01N33/68
CPC分类号： B01L3/5027 , B01L3/50853 , B01L3/50857 , B01L2300/0636 , B01L2300/0819 , B01L2300/0864 , B01L2400/0406 , G01N33/54366 , G01N33/5438 , G01N33/6872
摘要： This invention relates to the biosensor devices, their fabrication and use. The biosensor devices comprise a substrate supporting an array of microwells where each microwell can contain a biocompatible fluid and a membrane having a membrane protein of interest. In use the microwells can be addressable to detect and analyze a variety of analytes.
摘要翻译：本发明涉及生物传感器装置及其制造和使用。生物传感器装置包括支撑微孔阵列的基底，其中每个微孔可包含生物相容性流体和具有感兴趣的膜蛋白的膜。在使用中，微孔可以寻址以检测和分析各种分析物。

107. 发明授权

US06894925B1 Flash memory cell programming method and system 有权
标题翻译：闪存单元编程方法和系统
公开(公告)号：US06894925B1
公开(公告)日：2005-05-17
申请号：US10342585
申请日：2003-01-14
申请人： Sheunghee Park , Sameer S. Haddad , Chi Chang , Richard M. Fastow , Ming Sang Kwan , Zhigang Wang
发明人： Sheunghee Park , Sameer S. Haddad , Chi Chang , Richard M. Fastow , Ming Sang Kwan , Zhigang Wang
IPC分类号： G11C11/56 , G11C16/04 , H01L29/423 , H01L29/788
CPC分类号： G11C11/5621 , G11C16/0416 , H01L29/42324 , H01L29/7883
摘要： A flash memory cell programming system and method that facilitate efficient and quick operation of a flash memory cell by providing a biasable well (e.g., substrate) is presented. The biasable well flash memory cell enables increases in electrical field strengths in a manner that eases resistance to charge penetration of a dielectric barrier (e.g., oxide) around a charge trapping region (e.g., a floating gate). The present biasable well system and method also create a self convergence point that increase control during programming operations and reduces the chances of excessive correction for over erased memory cells. The biasing can assist hard programming to store information and/or soft programming to correct the effects of over-erasing. The biasing can also reduce stress on a drain voltage pump, reduce leakage current and reduce programming durations. Some implementations also include a biasable control gate component, biasable source component and biasable drain component.
摘要翻译：提出了一种闪存单元编程系统和方法，其通过提供可偏置的阱（例如，衬底）来促进闪存单元的有效和快速的操作。可偏置阱快闪存储器单元能够以减轻电荷俘获区域（例如浮栅）周围的电介质势垒（例如氧化物）的电荷穿透的方式增加电场强度。本发明的偏压井系统和方法还创建了一个自会聚点，从而在编程操作期间增加了控制，并降低了对擦除过的存储器单元过度校正的可能性。偏置可以帮助硬编程来存储信息和/或软编程以校正过度擦除的影响。偏置还可以减少漏极电压泵上的应力，减少泄漏电流并减少编程持续时间。一些实施方案还包括可偏置控制栅极分量，可偏置源分量和可偏置漏极分量。

108. 发明授权

US06617639B1 Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling 有权
标题翻译：对于ONO和隧道氧化物使用高K介电材料来改善浮栅闪存耦合
公开(公告)号：US06617639B1
公开(公告)日：2003-09-09
申请号：US10176594
申请日：2002-06-21
申请人： Zhigang Wang , Xin Guo , Yue-Song He
发明人： Zhigang Wang , Xin Guo , Yue-Song He
IPC分类号： H01L29788
CPC分类号： H01L21/28194 , H01L21/28273 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/7883
摘要： A floating gate flash memory device including a substrate comprising a source region, a drain region, and a channel region positioned therebetween; a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer; and a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising a nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, in which the tunnel dielectric material layer, and at least one of the bottom dielectric material layer and the top dielectric material layer, comprise a high-K dielectric material.
摘要翻译：一种浮栅闪存器件，包括：衬底，包括源极区，漏极区和位于其间的沟道区; 位于通道区域上方并通过隧道介电材料层与沟道区分离的浮栅电极; 以及控制栅电极，其位于所述浮置栅电极的上方，并且通过间隔电介质层与所述浮栅电极分离，所述互聚电介质层包括具有与所述浮栅电极相邻的底电介质材料层的修饰的ONO结构，顶介电材料层，以及包括氮化物并位于底部电介质材料层和顶部电介质材料层之间的中心层，其中隧道电介质材料层和底部电介质材料层和底部电介质材料层中的至少一个顶部介电材料层，包括高K电介质材料。

109. 发明授权

US06510085B1 Method of channel hot electron programming for short channel NOR flash arrays 有权
标题翻译：用于短通道NOR闪存阵列的通道热电子编程方法
公开(公告)号：US06510085B1
公开(公告)日：2003-01-21
申请号：US09861031
申请日：2001-05-18
申请人： Richard Fastow , Sheunghee Park , Zhigang Wang , Sameer Haddad , Chi Chang
发明人： Richard Fastow , Sheunghee Park , Zhigang Wang , Sameer Haddad , Chi Chang
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/10 , G11C16/12 , G11C16/3404
摘要： Methods of programming and soft programming short channel NOR flash memory cells that reduce the programming currents and column leakages during both programming and soft programming while maintaining fast programming speeds. During programming, a voltage of between 7 and 10 volts is applied to the control gate, a voltage of between 4 and 6 volts; is applied to the drain, a voltage of between 0.5 and 2.0 volts is applied to the source and a voltage of between minus 2 and minus 0.5 volts is applied to the substrate of the selected cell to be programmed. During soft programming, a voltage of between 0.5 and 4.5 volts is applied to the control gates, between 4 and 5.5 volts is applied to the drains, between 0.5 and 2 volts is applied to the sources and between minus 2.0 and minus 0.5 volts is applied to the substrates of the memory cells.
摘要翻译：编程和软编程短节目NOR闪存单元的方法，可在编程和软编程期间减少编程电流和列泄漏，同时保持快速的编程速度。在编程期间，7至10伏之间的电压施加到控制栅极，电压在4和6伏之间; 施加到漏极，将0.5至2.0伏之间的电压施加到源极，并且在所述要编程的所选择的单元的衬底之间施加负2和负0.5伏之间的电压。在软编程期间，向控制栅极施加0.5至4.5伏之间的电压，在漏极之间施加4至5.5伏之间的电压，施加0.5至2伏之间的电压，并施加负2.0至负0.5伏之间到存储单元的基板。

110. 发明授权

US06469939B1 Flash memory device with increase of efficiency during an APDE (automatic program disturb after erase) process 有权
标题翻译：闪存器件在APDE期间提高效率（擦除后的自动程序干扰）过程
公开(公告)号：US06469939B1
公开(公告)日：2002-10-22
申请号：US09969572
申请日：2001-10-01
申请人： Zhigang Wang , Richard Fastow , Sheung-Hee Park , Sameer S. Haddad , Chi Chang
发明人： Zhigang Wang , Richard Fastow , Sheung-Hee Park , Sameer S. Haddad , Chi Chang
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/10 , G11C16/12 , G11C16/3404
摘要： A source resistor or a positive voltage is coupled to the source and a negative bias voltage is applied at the substrate or p-well of flash memory cells for enhanced efficiency during programming and/or during an APDE (Automatic Program Disturb after Erase) process for a flash memory device. Furthermore, in a system and method for programming the flash memory device, a flash memory cell of the array of multiple flash memory cells is selected to be programmed. A control gate programming voltage is applied to the control gate of the selected flash memory cell, and a bit line programming voltage is applied to the drain of the selected flash memory cell via the common bit line terminal to which the drain of the selected flash memory cell is connected.
摘要翻译：源极电阻或正电压耦合到源极，并且在闪存单元的衬底或p阱处施加负偏置电压，以在编程期间和/或在APDE（擦除后自动程序干扰）处理期间提高效率闪存设备。此外，在用于对闪速存储器件进行编程的系统和方法中，选择多个闪速存储器单元的阵列中的闪存单元进行编程。控制栅极编程电压被施加到所选择的闪速存储器单元的控制栅极，并且位线编程电压通过公共位线端子被施加到所选择的闪存单元的漏极，所述公共位线端子选择闪存的漏极单元格已连接。

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