专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

101. 发明申请

US20080256550A1 Parallel processing system by OS for single processor 审中-公开
标题翻译：用于单处理器的OS的并行处理系统
公开(公告)号：US20080256550A1
公开(公告)日：2008-10-16
申请号：US12213190
申请日：2008-06-16
申请人： Masato Edahiro , Yoshiyuki Ito , Junji Sakai , Tetsuya Minakami , Hiroaki Inoue
发明人： Masato Edahiro , Yoshiyuki Ito , Junji Sakai , Tetsuya Minakami , Hiroaki Inoue
IPC分类号： G06F9/46
CPC分类号： G06F9/5066
摘要： The present invention relates to a parallel processing system by an OS for single processor capable of operating an OS for single processor and an existing application on a multiprocessor and achieving parallel processing by a multiprocessor with respect to the application, wherein the multiprocessor are logically divided into two groups, i.e., a first processor side and a second processor side, and units of work that are parallelizable within the application operating on the processors on the first processor side are controlled as new units of work on the processors on the second processor side.
摘要翻译：本发明涉及一种用于单处理器的OS的并行处理系统，其能够操作用于单处理器的OS和多处理器上的现有应用，并且实现相对于应用的多处理器的并行处理，其中多处理器被逻辑地分为两个组，即第一处理器侧和第二处理器侧，以及在第一处理器侧的处理器上操作的应用内可并行化的工作单元被控制为第二处理器侧的处理器上的新的工作单元。

102. 发明申请

US20080172667A1 Parallel processing system by OS for single processors and parallel processing program 有权
标题翻译：用于单处理器和并行处理程序的OS的并行处理系统
公开(公告)号：US20080172667A1
公开(公告)日：2008-07-17
申请号：US10807168
申请日：2004-03-24
申请人： Hiroaki Inoue , Yoshiyuki Ito , Junji Sakai , Masato Edahiro
发明人： Hiroaki Inoue , Yoshiyuki Ito , Junji Sakai , Masato Edahiro
IPC分类号： G06F9/46
CPC分类号： G06F9/54
摘要： In a parallel processing system by an OS for single processors which operates an OS for single processors and an existing application for single processors on a multiprocessor to realize parallel processing by the multiprocessor with respect to the application, with the multiprocessor being logically divided into two groups of a first processor side and a second processor side, a unit of work that can be parallelized within the application operating on a processor on the first processor side is controlled as a new unit of work on a processor on the second processor side.
摘要翻译：在用于单个处理器的操作系统的OS的并行处理系统中，用于单个处理器的OS和用于多处理器上的单个处理器的现有应用以实现多处理器相对于应用的并行处理，其中多处理器被逻辑地分成两组第一处理器侧和第二处理器侧的可在第一处理器侧的处理器上操作的应用中并行化的工作单元被控制为在第二处理器侧的处理器上的新的工作单元。

103. 发明授权

US07387717B2 Method of performing electrolytic treatment on a conductive layer of a substrate 失效
标题翻译：在基板的导电层上进行电解处理的方法
公开(公告)号：US07387717B2
公开(公告)日：2008-06-17
申请号：US10631726
申请日：2003-08-01
申请人： Junji Kunisawa , Mitsuko Odagaki , Natsuki Makino , Koji Mishima , Kenji Nakamura , Hiroaki Inoue , Norio Kimura , Tetsuo Matsuda , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura , Manabu Tsujimura , Toshiyuki Morita
发明人： Junji Kunisawa , Mitsuko Odagaki , Natsuki Makino , Koji Mishima , Kenji Nakamura , Hiroaki Inoue , Norio Kimura , Tetsuo Matsuda , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura , Manabu Tsujimura , Toshiyuki Morita
IPC分类号： C25D7/12
CPC分类号： H01L21/6719 , C25D7/123 , C25D17/001 , C25D17/12 , C25D17/14 , H01L21/2885 , H01L21/67046 , H01L21/67051 , H01L21/6708 , H01L21/6715 , H01L21/6723 , H01L21/76877 , H01L21/76879 , H01L2924/0002 , H05K3/423 , H01L2924/00
摘要： A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.
摘要翻译：用于衬底的电镀方法和装置将诸如铜的金属填充到形成在半导体衬底中的精细互连图案中。该装置具有基板保持部分36，其水平地保持并旋转基板，其表面被面向上。密封材料90接触表面的周缘部分，以水密的方式密封该部分。阴极电极88在与基板接触时通过电流。阴极部38与基板保持部36一体地旋转。电极臂部30在阴极部38的上方，水平且垂直地移动，阳极98面朝下。将电镀液注入被镀表面与接近待镀表面的阳极98之间的空间中。因此，电镀处理和附带的处理可以通过单个单元进行。

104. 发明授权

US07344986B2 Plating solution, semiconductor device and method for manufacturing the same 有权
标题翻译：电镀液，半导体装置及其制造方法
公开(公告)号：US07344986B2
公开(公告)日：2008-03-18
申请号：US10482104
申请日：2002-11-06
申请人： Hiroaki Inoue , Xinming Wang , Moriji Matsumoto , Makoto Kanayama
发明人： Hiroaki Inoue , Xinming Wang , Moriji Matsumoto , Makoto Kanayama
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , C23C18/48 , C25D3/58 , H01L21/288 , H01L21/2885 , H01L21/7684 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a plating solution useful for forming embedded interconnects by embedding a conductive material in fine recesses for interconnects provided in the surface of a substrate, such as a semiconductor substrate, or for forming a protective layer for protecting the surface of embedded interconnects, a semiconductor device manufactured by using the plating solution and a method for manufacturing the semiconductor device. The plating solution contains copper ions, metal ions of a metal, and the metal is capable of forming with copper a copper alloy in which the metal does not form a solid solution with copper, a complexing agent, and a reducing agent free from alkali metal.
摘要翻译：本发明涉及一种用于通过将导电材料嵌入到设置在诸如半导体衬底的衬底的表面中的互连的精细凹槽中的用于形成嵌入式互连的电镀液，或用于形成用于保护嵌入式互连的表面的保护层，使用电镀液制造的半导体装置及其制造方法。电镀溶液含有铜离子，金属的金属离子，金属能够与铜形成铜合金，其中金属不与铜形成固溶体，络合剂和不含碱金属的还原剂。

105. 发明申请

US20080005794A1 Information Communication Device and Program Execution Environment Control Method 有权
标题翻译：信息通信设备和程序执行环境控制方法
公开(公告)号：US20080005794A1
公开(公告)日：2008-01-03
申请号：US11660967
申请日：2005-08-15
申请人： Hiroaki Inoue , Junji Sakai , Tsuyoshi Abe , Masato Edahiro
发明人： Hiroaki Inoue , Junji Sakai , Tsuyoshi Abe , Masato Edahiro
IPC分类号： G06F12/14 , G06F9/50 , G06F9/54
CPC分类号： G06F21/56 , G06F21/52
摘要： A device and a method are provided for increasing processing speed and for ensuring system security when an application or a driver is added. The device includes a first CPU group 10A that executes software 20A composed of basic processing 22 and an OS 21A; a second CPU group 10B that executes software 20B composed of additional processing 23 and OS 21B corresponding to the additional processing, inter-processor communication means 40, and 402 used for communication between the first CPU 10A and the second CPU 10B, and access control means 30 that controls access made by the second CPU 10B to a memory 50 and/or an input/output device 60.
摘要翻译：提供了一种用于提高处理速度并在添加应用程序或驱动程序时确保系统安全性的设备和方法。该装置包括执行由基本处理22和OS 21A构成的软件20A的第一CPU组10A; 第二CPU组10B，其执行由与用于第一CPU10A和第二CPU10B之间的通信的附加处理，处理器间通信装置40和402对应的附加处理23和OS 21B组成的软件20B 以及将第二CPU10B进行的访问控制到存储器50和/或输入/输出装置60的访问控制装置30。

106. 发明授权

US07279408B2 Semiconductor device, method for manufacturing the same, and plating solution 有权
标题翻译：半导体装置及其制造方法以及电镀液
公开(公告)号：US07279408B2
公开(公告)日：2007-10-09
申请号：US11254790
申请日：2005-10-21
申请人： Hiroaki Inoue , Norio Kimura , Xinming Wang , Moriji Matsumoto , Makoto Kanayama
发明人： Hiroaki Inoue , Norio Kimura , Xinming Wang , Moriji Matsumoto , Makoto Kanayama
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , C23C18/1608 , C23C18/1632 , C23C18/1653 , C23C18/32 , C23C18/48 , C23C18/50 , H01L21/288 , H01L21/2885 , H01L21/3212 , H01L21/7684 , H01L21/76849 , H01L21/76864 , H01L21/76874 , H01L21/76877 , H01L21/76883 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a semiconductor device and a method for manufacturing the same. The semiconductor device has an embedded interconnect structure in which an electric conductor, such as copper or silver, is embedded in fine recesses formed in a surface of a semiconductor substrate, and also has a protective film formed on surfaces of exposed interconnects that define the interconnect structure, to protect the interconnects. The protective film has a flattened surface.
摘要翻译：半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。半导体器件具有嵌入式互连结构，其中诸如铜或银的电导体嵌入形成在半导体衬底的表面中的细小凹槽中，并且还具有形成在暴露的互连件的表面上的保护膜，所述互连限定了互连结构，保护互连。保护膜具有平坦的表面。

107. 发明申请

US20070097055A1 Drive apparatus of liquid crystal display device 失效
标题翻译：液晶显示装置驱动装置
公开(公告)号：US20070097055A1
公开(公告)日：2007-05-03
申请号：US11507497
申请日：2006-08-22
申请人： Satoshi Takamura , Hidetoshi Okazaki , Hiroaki Inoue
发明人： Satoshi Takamura , Hidetoshi Okazaki , Hiroaki Inoue
IPC分类号： G09G3/36
CPC分类号： G09G3/3622 , G09G3/3614 , G09G2330/02 , G09G2330/025
摘要： An apparatus includes a polarity reversing section which generates a polarity reversing signal for the liquid crystal drive voltage; a liquid crystal driver which reverses the polarity of the liquid crystal drive voltage based on the polarity reversing signal to drive the liquid crystal display panel; a warning signal generation section which generates a warning signal indicating the polarity reverse before the polarity of the liquid crystal drive voltage is reversed; and a regulator section which controls a supply of the liquid crystal drive voltage in accordance with the warning signal.
摘要翻译：一种装置包括：极性反转部，其生成用于液晶驱动电压的极性反转信号; 液晶驱动器，其根据极性反转信号反转液晶驱动电压的极性，驱动液晶显示面板; 警告信号生成部，其在液晶驱动电压的极性反转之前生成表示极性反转的警告信号; 以及调节器部，其根据所述警告信号控制所述液晶驱动电压的供给。

108. 发明授权

US07208074B2 Substrate processing apparatus and substrate plating apparatus 失效
标题翻译：基板处理装置和基板电镀装置
公开(公告)号：US07208074B2
公开(公告)日：2007-04-24
申请号：US10742390
申请日：2003-12-22
申请人： Koji Mishima , Junji Kunisawa , Natsuki Makino , Norio Kimura , Hiroaki Inoue , Kenji Nakamura , Moriji Matsumoto , Takahiro Nanjo , Mitsuko Odagaki
发明人： Koji Mishima , Junji Kunisawa , Natsuki Makino , Norio Kimura , Hiroaki Inoue , Kenji Nakamura , Moriji Matsumoto , Takahiro Nanjo , Mitsuko Odagaki
IPC分类号： C25C28/00 , C25D5/10
CPC分类号： H01L21/67109 , C25D7/123 , C25D17/001 , H01L21/2885 , H01L21/67778 , H01L21/681
摘要： A substrate processing apparatus fills a metal such as copper or the like in fine interconnection patterns or trenches defined in a semiconductor substrate. The substrate processing apparatus has a loading/unloading unit for placing a substrate cassette to allow a substrate to be loaded and unloaded, a substrate treating unit for treating a substrate, and a transfer robot for transferring a substrate between the loading/unloading unit and the substrate treating unit. The loading/unloading unit, the substrate treating unit, and the transfer robot are installed in a single facility. The loading/unloading unit has a rotary table which is horizontally rotatable for positioning the substrate cassette in a position to detect the substrate cassette placed in the loading/unloading unit and to remove the substrate from the substrate cassette with the transfer robot.
摘要翻译：基板处理装置以限定在半导体基板中的精细互连图案或沟槽中填充诸如铜等的金属。基板处理装置具有用于放置基板盒以装载和卸载基板的装载/卸载单元，用于处理基板的基板处理单元，以及用于在装载/卸载单元和卸载单元之间传送基板的传送机器人底物处理单元。装载/卸载单元，基板处理单元和传送机器人安装在单个设施中。装载/卸载单元具有可水平旋转的旋转台，用于将基板盒定位在检测装载/卸载单元中的基板盒的位置，并用传送机器人从基板盒移除基板。

109. 发明授权

US06861704B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06861704B2
公开(公告)日：2005-03-01
申请号：US10663705
申请日：2003-09-17
申请人： Hitoshi Asada , Hiroaki Inoue
发明人： Hitoshi Asada , Hiroaki Inoue
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/08 , H01L29/417 , H01L29/49 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/0847 , H01L21/823418 , H01L21/823468 , H01L29/41775 , H01L29/4933 , H01L29/6656 , H01L29/66659 , H01L29/7833 , H01L29/7835
摘要： The semiconductor device comprises a gate electrode 26 formed on a semiconductor substrate 10, a source region 45a having a lightly doped source region 42a and a heavily doped source region 44a, a drain region 45b having a lightly doped drain region 42b and a heavily doped drain region 44b, a first silicide layer 40c formed on the source region, a second silicide layer 40d formed on the drain region, a first conductor plug 54 connected to the first silcide layer and a second conductor plug 54 connected to the second silicide layer. The heavily doped drain region is formed in the region of the lightly doped region except the peripheral region, and the second silicide layer is formed in the region of the heavily doped drain region except the peripheral region. Thus, the concentration of the electric fields on the drain region can be mitigated when voltages are applied to the drain region. Thus, even with the silicide layer formed on the source/drain region, sufficiently high withstand voltages of the high withstand voltage transistor can be ensured. Furthermore, the drain region alone has the above-described structure, whereby the increase of the source-drain electric resistance can be prevented while high withstand voltages can be ensured.
摘要翻译：半导体器件包括形成在半导体衬底10上的栅电极26，具有轻掺杂源极区域42a和重掺杂源极区域44a的源极区域45a，具有轻掺杂漏极区域42b的漏极区域45b和重掺杂漏极区域44b，形成在源极区上的第一硅化物层40c，形成在漏极区上的第二硅化物层40d，连接到第一硅化物层的第一导体插塞54和连接到第二硅化物层的第二导体插塞54。重掺杂漏极区域形成在除了外围区域之外的轻掺杂区域的区域中，并且第二硅化物层形成在除了周边区域之外的重掺杂漏极区域的区域中。因此，当向漏极区域施加电压时，可以减轻漏极区域上的电场的浓度。因此，即使在源极/漏极区域上形成硅化物层，也可以确保高耐压晶体管的足够高的耐受电压。此外，单独的漏极区域具有上述结构，由此可以防止源极 - 漏极电阻的增加，同时可以确保高耐受电压。

110. 发明申请

US20050029669A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050029669A1
公开(公告)日：2005-02-10
申请号：US10893244
申请日：2004-07-19
申请人： Hiroaki Inoue , Akira Susaki
发明人： Hiroaki Inoue , Akira Susaki
IPC分类号： C23C18/16 , C25D7/12 , H01L21/288 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L23/52
CPC分类号： H01L21/76885 , H01L21/76852 , H01L23/5226 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including a highly reliable multi-level interconnect structure having a low effective dielectric constant and which can be easily manufactured with a relatively inexpensive process, and a method for manufacturing the semiconductor device. The semiconductor device includes a lower-level interconnect and an upper-level interconnect, each surrounded by a barrier layer, and a via plug surrounded by a barrier layer and electrically connecting the lower-level interconnect and the upper-level interconnect.
摘要翻译：一种半导体器件，包括具有低有效介电常数的高可靠性多电平互连结构，并且可以以相对便宜的工艺容易地制造，以及半导体器件的制造方法。该半导体器件包括一个下层互连和一个上层互连，每一个都被一个阻挡层包围，一个由阻挡层包围并通过电气连接下层互连和上层互连的通孔。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式