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101. 发明授权

US06831479B2 Circuit for reducing pin count of a semiconductor chip and method for configuring the chip 有权
标题翻译：用于减少半导体芯片的引脚数的电路和用于配置芯片的方法
公开(公告)号：US06831479B2
公开(公告)日：2004-12-14
申请号：US10287527
申请日：2002-11-05
申请人： William Lo
发明人： William Lo
IPC分类号： H03K19173
CPC分类号： H03K19/1732
摘要： A circuit that reduces external terminal count of a semiconductor chip, such as a communications chip or other type of chip that requires the generation of configuration codes, by reducing the number of external input terminals required for generating the configuration data. The circuit includes multiplexers, each of which selects output data or configuration data, and includes an output in communication with a respective external output terminal of the chip. A selector is connectable between a selected one of the external output terminals and an external input terminal in communication with a memory to serially input configuration data on that output terminal to the memory to configure the chip. Thus, configuration codes are generated for the chip using a reduced number of external input terminals, thereby reducing the overall external terminal count of the chip. The circuit and chip may be embodied on a network or Ethernet card.
摘要翻译：通过减少生成配置数据所需的外部输入端子的数量，减少需要生成配置代码的诸如通信芯片或其他类型的芯片的半导体芯片的外部端子计数的电路。电路包括多路复用器，每个复用器选择输出数据或配置数据，并且包括与芯片的相应外部输出端通信的输出。选择器可连接在所选择的一个外部输出端子和与存储器通信的外部输入端子，以将输出端子上的配置数据串行输入到存储器以配置芯片。因此，使用减少数量的外部输入端子为芯片生成配置码，从而减少芯片的整体外部终端计数。电路和芯片可以体现在网络或以太网卡上。

102. 发明授权

US06741097B2 Circuit for reducing pin count of a semiconductor chip and method for configuring the chip 有权
公开(公告)号：US06741097B2
公开(公告)日：2004-05-25
申请号：US10287528
申请日：2002-11-05
申请人： William Lo
发明人： William Lo
IPC分类号： H03K19173
CPC分类号： H03K19/1732
摘要： A circuit that reduces external terminal count of a semiconductor chip, such as a communications chip or other type of chip that requires the generation of configuration codes, by reducing the number of external input terminals required for generating the configuration data. The circuit includes multiplexers, each of which selects output data or configuration data, and includes an output in communication with a respective external output terminal of the chip. A selector is connectable between a selected one of the external output terminals and an external input terminal in communication with a memory to serially input configuration data on that output terminal to the memory to configure the chip. Thus, configuration codes are generated for the chip using a reduced number of external input terminals, thereby reducing the overall external terminal count of the chip. The circuit and chip may be embodied on a network or Ethernet card.

103. 发明授权

US6118809A Repeater delay balancing 失效
标题翻译：中继器延时平衡
公开(公告)号：US6118809A
公开(公告)日：2000-09-12
申请号：US791587
申请日：1997-01-31
申请人： William Lo
发明人： William Lo
IPC分类号： H04L25/24 , H04B3/36
CPC分类号： H04L25/242
摘要： A repeater set provides for delaying a character of data that passes through the repeater set from one receive channel to a set of transmit channels. In providing for the delay of a character, the repeater set includes a delay calculator for calculating a character delay value. The repeater set then receives a character that is to be provided on a transmit channel and delays the character in a delay module for a period of time equal to the character delay value. The character delay value is determined by the delay calculator by first calculating a bit delay value and then converting the bit delay value into the character delay value.
摘要翻译：中继器组提供用于将通过中继器组的数据的字符从一个接收信道延迟到一组发送信道。在提供字符的延迟时，中继器组包括用于计算字符延迟值的延迟计算器。然后，中继器组接收将在发送信道上提供的字符，并将延迟模块中的字符延迟等于字符延迟值的时间段。字符延迟值由延迟计算器确定，首先计算位延迟值，然后将位延迟值转换为字符延迟值。

104. 发明授权

US5754525A Programmable delay of disrupt for secure networks 失效
标题翻译：可编程的安全网络中断延迟
公开(公告)号：US5754525A
公开(公告)日：1998-05-19
申请号：US366808
申请日：1994-12-30
申请人： William Lo , Ian Crayford
发明人： William Lo , Ian Crayford
IPC分类号： H04L12/22 , H04L12/44 , H04L29/06 , H04J3/26
CPC分类号： H04L12/44 , B60G17/0182 , H04L12/22 , H04L63/0236 , B60G2400/102 , B60G2400/202 , B60G2600/182 , B60G2600/1872 , B60G2600/1873 , B60G2800/162
摘要： A secure repeater implementing data packet masking includes a programmable and selective, on a per port basis, delay disrupt response. A delay disrupt controller receives signals indicating retransmissions of fields from a data packet. These signals include a destination address field and a source address field. A plurality of memories, one associated with each port, determines the associated port's delay response to the data packet. Each memory stores a delay disrupt control code. When the delay disrupt control code for a particular port has a value indicating that the associated port is enabled to delay disruption of a data packet, security marking is disabled until the source address field is retransmitted from the particular port.
摘要翻译：实现数据包掩蔽的安全中继器包括在每个端口基础上的可编程和选择性的延迟中断响应。延迟中断控制器接收指示来自数据分组的字段重传的信号。这些信号包括目的地址字段和源地址字段。与每个端口相关联的多个存储器确定相关端口对数据分组的延迟响应。每个存储器存储一个延迟中断控制码。当延迟中断特定端口的控制代码具有指示相关端口被使能以延迟数据分组中断的值时，安全标记被禁用，直到源地址字段从特定端口重传为止。

105. 发明授权

US5640393A Multiple address security architecture 失效
标题翻译：多地址安全架构
公开(公告)号：US5640393A
公开(公告)日：1997-06-17
申请号：US460319
申请日：1995-06-02
申请人： William Lo , Ian Crayford
发明人： William Lo , Ian Crayford
IPC分类号： H04L9/36 , H04L12/22 , H04L12/44 , H04L12/46 , H04L29/06 , H04L9/00
CPC分类号： H04L63/02 , H04L12/22 , H04L12/44 , H04L12/4625
摘要： A secure repeater implementing data packet masking includes a programmable and selective, on a per port basis, disrupt response responsive to any of several selectable qualifying conditions. A disrupt controller receives signals indicating various characteristics of fields of a data packet, and other conditions. A register bank includes a plurality of memories, one associated with each port and some of the conditions, assists the disrupt controller to determine the associated port's disrupt response to the data packet. Each memory stores a disrupt control code. When the disrupt control code for a particular port has a value indicating that the associated port is enabled, deassertion of a condition signal associated with that control code results in disruption of a data packet. A cell array permits simple, efficient scaling and formation of integrated semiconductor structures to implement complex disrupt logic equations.
摘要翻译：实现数据分组掩蔽的安全中继器包括在每个端口的基础上的可编程和选择性，响应于几种可选择的限定条件中的任一种而中断响应。中断控制器接收指示数据包的字段的各种特性的信号和其他条件。寄存器组包括多个存储器，一个与每个端口相关联的存储器和一些条件，帮助中断控制器确定相关端口对数据包的中断响应。每个存储器存储中断控制代码。当特定端口的中断控制代码具有指示相关端口被使能的值时，与该控制代码相关联的条件信号的取消取消导致数据分组的中断。单元阵列允许简单，有效的缩放和形成集成半导体结构以实现复杂的中断逻辑方程。

106. 发明授权

US5559801A Programmable packet sampling for network management 失效
标题翻译：用于网络管理的可编程数据包采样
公开(公告)号：US5559801A
公开(公告)日：1996-09-24
申请号：US438982
申请日：1995-05-11
申请人： William Lo
发明人： William Lo
IPC分类号： H04L12/24 , H04L12/44 , H04J3/06
CPC分类号： H04L41/26 , H04L12/44
摘要： A sampling repeater implementing a data packet sampling schedule includes a repeater front-end, a transmitter and a sampler. The transmitter, responsive to disrupt control signals, retransmits a data packet in a disrupted form, or an undisrupted form, to a management unit coupled to a management port. When one of the disrupt control signals are asserted, the data packet is retransmitted undisrupted as a sample packet. The management unit processes the sample packet and extracts any desired statistics. When none of the disrupt control signals are asserted, the disrupted data packet is retransmitted to the management unit. The disrupted data packet fails error checking and is ignored. The sampler periodically, according to the sampling schedule, asserts one of the disrupt control signals, to pass sample packets to the management unit. Thus, the management unit only processes a subset of the input data packets, rather than every data packet.
摘要翻译：实现数据分组采样计划的采样中继器包括中继器前端，发射机和采样器。响应于中断控制信号的发射机以破坏的形式或不间断的形式将数据分组重传到耦合到管理端口的管理单元。当其中一个中断控制信号被断言时，数据包被重传为中断，作为一个采样包。管理单元处理样本数据包并提取任何所需的统计信息。当没有断开控制信号被断言时，中断的数据包被重新发送到管理单元。中断的数据包失败错误检查，并被忽略。采样器根据采样计划周期性地定出其中一个中断控制信号，以将采样数据包传送到管理单元。因此，管理单元仅处理输入数据分组的子集，而不是每个数据分组。

107. 发明授权

US5493562A Apparatus and method for selectively storing error statistics 失效
标题翻译：用于选择性地存储错误统计的装置和方法
公开(公告)号：US5493562A
公开(公告)日：1996-02-20
申请号：US337635
申请日：1994-11-10
申请人： William Lo
发明人： William Lo
IPC分类号： H04L12/56 , H04L12/26 , H04B17/02 , H04J3/14
CPC分类号： H04L43/0847
摘要： A circuit including a data formatter for receiving desired information associated with a data packet and arranging the bits into a format for transfer to a memory, a memory for storing the desired information for later access by a microprocessor, and a controller for selectively transferring and writing the desired information from the data formatter to the memory. The circuit provides improved performance by storing only the desired information for a data packet having an error. That is, information internal to the data packet itself, such as the source address, and information external to the data packet, such as the repeater port number, in addition to data packet error information, such as error conditions, may be stored as an error statistic in a memory for a microprocessor to read at its leisure.
摘要翻译：一种电路，包括用于接收与数据分组相关联的期望信息并将这些比特排列成用于传送到存储器的格式的数据格式器，用于存储所需信息以供稍后由微处理器访问的存储器，以及用于选择性地传送和写入的控制器从数据格式化器到存储器的所需信息。该电路通过仅存储具有错误的数据分组的期望信息来提供改进的性能。也就是说，除数据分组错误信息（诸如错误条件）之外，数据分组本身内部的信息，诸如源地址和数据分组外部的信息，诸如中继器端口号，可以被存储为微处理器在其休闲时读取的存储器中的错误统计信息。

108. 发明授权

US5388133A Counter for attribute storage for use in a repeater 失效
标题翻译：用于中继器的属性存储的计数器
公开(公告)号：US5388133A
公开(公告)日：1995-02-07
申请号：US20490
申请日：1993-02-22
申请人： Nader Vijeh , William Lo
发明人： Nader Vijeh , William Lo
IPC分类号： H04L12/28 , G06F11/34 , H04L12/26 , G06M3/06
CPC分类号： H04L12/2602 , G06F11/348 , H04L43/00 , G06F2201/88
摘要： A counter for attribute stored in an Ethernet system is partitioned such that the storage section is separated from the incrementors section. In so doing, counters are implemented in a significantly less space than if the counters were implemented as individual counters. The counter utilizes random access memory as the storage section and a 32 bit incrementor. As the incrementor section along with a pair of latches to implement the counter.
摘要翻译：存储在以太网系统中的属性的计数器被分区，使得存储部分与增量部分分离。在这样做时，计数器的实现方式远远小于将计数器作为单独计数器实现的空间。该计数器利用随机存取存储器作为存储部分和32位增量器。作为递增器部分以及用于实现计数器的一对闩锁。

109. 发明授权

US5375089A Plural port memory system utilizing a memory having a read port and a write port 失效
标题翻译：利用具有读取端口和写入端口的存储器的多端口存储器系统
公开(公告)号：US5375089A
公开(公告)日：1994-12-20
申请号：US132027
申请日：1993-10-05
申请人： William Lo
发明人： William Lo
IPC分类号： G11C11/401 , G06F12/00 , G11C8/16 , G11C11/41 , G11C7/00 , G11C8/00
CPC分类号： G11C8/16
摘要： A plural port memory system utilizing a memory having a write port and a separate read port wherein the write port includes a write data line, a write address, and a write enable line and wherein the read port includes a read data line, a read address, and a read enable line. The plural port memory system includes: a plurality of interfaces for reading from and writing to the memory, each interface having a read request line and a write request line; and a controller coupled to each of the read and write request lines, and the read and write enable lines for arbitrating access to the memory by the plurality of interfaces.
摘要翻译：一种利用具有写入端口和单独读取端口的存储器的多端口存储器系统，其中写入端口包括写入数据线，写入地址和写入使能线，并且其中读取端口包括读取数据线，读取地址，以及读使能线。多个端口存储器系统包括：多个用于从存储器读取和写入存储器的接口，每个接口具有读取请求行和写入请求行; 以及耦合到读取和写入请求行中的每一个的控制器以及用于通过多个接口仲裁对存储器的访问的读取和写入使能线。

110. 发明授权

US08856391B1 Method and apparatus for controlling data transfer between EEPROM and a physical layer device 有权
标题翻译：用于控制EEPROM和物理层设备之间的数据传输的方法和装置
公开(公告)号：US08856391B1
公开(公告)日：2014-10-07
申请号：US12616111
申请日：2009-11-10
申请人： Trinh T. Phung , William Lo
发明人： Trinh T. Phung , William Lo
IPC分类号： G06F13/00 , G06F13/14 , G06F13/36 , H04L12/66
CPC分类号： G06F13/1684
摘要： An IEEE 802.3 compliant physical layer device provides efficient loading of configuration information of the physical layer device. The configuration information is written into a volatile memory in the physical layer device, and then uploaded to at least one EEPROM. The configuration information is downloaded to the volatile memory during startup of the physical layer device. The system controller can also directly access the EEPROMs, bypassing the volatile memory. By providing a bridge between the system controller and the EEPROMs and providing additional bits in the volatile memory of the physical layer device, the system controller can read and write the EEPROMs one byte at a time. During reset time, the content of the EEPROMs is written to registers in the physical layer device to configure the physical layer device.
摘要翻译：符合IEEE 802.3标准的物理层设备提供物理层设备的配置信息的高效加载。配置信息被写入物理层设备中的易失性存储器中，然后上传到至少一个EEPROM。配置信息在物理层设备启动期间被下载到易失性存储器。系统控制器也可以直接访问EEPROM，绕过易失性存储器。通过在系统控制器和EEPROM之间提供桥接器，并在物理层器件的易失性存储器中提供额外的位，系统控制器可以一次读取一个字节的EEPROM。在复位期间，将EEPROM的内容写入物理层设备中的寄存器，以配置物理层设备。

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