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101. 发明授权

US07291519B2 Methods of forming transistor constructions 有权
标题翻译：形成晶体管结构的方法
公开(公告)号：US07291519B2
公开(公告)日：2007-11-06
申请号：US11350061
申请日：2006-02-08
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L21/00
CPC分类号： H01L27/11568 , G11C16/0416 , G11C16/10 , G11C16/26 , G11C16/28 , G11C2211/4016 , H01L21/76838 , H01L21/84 , H01L27/10802 , H01L27/10814 , H01L27/10852 , H01L27/10873 , H01L27/115 , H01L27/11521 , H01L27/12 , H01L27/1203 , H01L28/40 , H01L29/66742 , H01L29/66825 , H01L29/66833 , H01L29/7841 , H01L29/7842 , H01L29/78687 , H01L29/7881
摘要： The invention includes a non-volatile memory cell comprising a field effect transistor construction having a body region within a crystalline material. The body region includes a charge trapping region. The memory cell can be TFT-SOI based, and can be supported by a substrate selected from a diverse assortment of materials. The top portion of the substrate can be a conductive layer separated from the memory device by the SOI-oxide insulator film. The charge trapping region can be, for example, silicon enriched silicon nitride or silicon enriched silicon oxide. The crystalline material can include silicon and germanium. The transistor comprises first and second diffusion regions within the body region, and also comprises a channel region between the first and second diffusion regions. The entirety of the body region within the crystalline material can be within a single crystal of the material.
摘要翻译：本发明包括一种非易失性存储单元，其包括在结晶材料内具有体区的场效应晶体管结构。身体区域包括电荷俘获区域。存储单元可以是基于TFT-SOI的，并且可以由选自不同种类的材料的衬底支撑。衬底的顶部可以是通过SOI氧化物绝缘膜与存储器件分离的导电层。电荷捕获区可以是例如富硅氮化硅或富含硅的氧化硅。结晶材料可以包括硅和锗。晶体管包括体区内的第一和第二扩散区，并且还包括在第一和第二扩散区之间的沟道区。结晶材料内的体区的整体可以在材料的单晶内。

102. 发明授权

US07285798B2 CMOS inverter constructions 有权
标题翻译： CMOS逆变器结构
公开(公告)号：US07285798B2
公开(公告)日：2007-10-23
申请号：US11336463
申请日：2006-01-20
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L31/036
CPC分类号： H01L27/12 , H01L21/8221 , H01L21/823828 , H01L21/84 , H01L27/0688 , H01L27/092 , H01L27/1203 , H01L29/78687
摘要： Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and PFET devices can have an active region extending into both a strained crystalline lattice and a relaxed crystalline lattice. The relaxed crystalline lattice can comprise appropriately-doped silicon/germanium. The strained crystalline lattice can comprise, for example, appropriately doped silicon, or appropriately-doped silicon/germanium. The CMOS inverter can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic).
摘要翻译：利用在PFET器件和NFET器件之间桥接的公共栅极的基于薄膜晶体管的三维CMOS反相器。 NFET和PFET器件中的一个或两个可以具有延伸到应变晶格和松弛晶格两者中的有源区。松弛的晶格可以包括适当掺杂的硅/锗。应变晶格可以包括例如适当掺杂的硅或适当掺杂的硅/锗。 CMOS反相器可以是在常规基板（例如单晶硅晶片）或非常规基板（诸如玻璃，氧化铝，二氧化硅，金属和塑料中的一种或多种）之上形成的SOI结构的一部分。

103. 发明授权

US07250338B2 Scalable Flash/NV structures and devices with extended endurance 有权
标题翻译：可扩展的Flash / NV结构和具有延长耐久性的设备
公开(公告)号：US07250338B2
公开(公告)日：2007-07-31
申请号：US11209416
申请日：2005-08-23
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L21/336
CPC分类号： H01L21/28194 , B82Y10/00 , G11C16/0416 , G11C16/0466 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel medium, a high K charge blocking and charge storing medium, and an injector medium. The high K charge blocking and charge storing medium is disposed on the tunnel medium. The injector medium is operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling. According to one embodiment, the injector medium is disposed on the high K charge blocking and charge storing medium. According to one embodiment, the tunnel medium is disposed on the injector medium. Other aspects and embodiments are provided herein.
摘要翻译：关于非易失性结构的栅极堆叠提供了器件和方法。根据一个方面，提供了一个栅极堆叠。栅极堆叠的一个实施例包括隧道介质，高K电荷阻挡和电荷存储介质以及注入介质。高K电荷阻挡和电荷存储介质设置在隧道介质上。喷射器介质相对于隧道介质和高K电荷阻挡和电荷存储介质可操作地设置，以通过增强的隧穿提供电荷传输。根据一个实施例，喷射器介质设置在高K电荷阻挡和电荷存储介质上。根据一个实施例，隧道介质设置在注射器介质上。本文提供了其它方面和实施例。

104. 发明申请

US20070145454A1 SCALABLE INTEGRATED LOGIC AND NON-VOLATILE MEMORY 有权
标题翻译：可扩展的集成逻辑和非易失性存储器
公开(公告)号：US20070145454A1
公开(公告)日：2007-06-28
申请号：US11684138
申请日：2007-03-09
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L27/108
CPC分类号： H01L29/42332 , B82Y10/00 , H01L29/4966 , H01L29/66825
摘要： A scalable, logic transistor has a pair of doped regions for the drain and source. A gate insulator layer is formed over the substrate and between the drain and source regions. A gate stack is formed of a gate layer, such as polysilicon or metal, between two metal nitride layers. A compatible non-volatile memory transistor can be formed from this basic structure by adding a high-K dielectric constant film with an embedded metal nano-dot layer between the tunnel insulator and the gate stack.
摘要翻译：可扩展的逻辑晶体管具有用于漏极和源极的一对掺杂区域。栅极绝缘体层形成在衬底上并且在漏极和源极区域之间。栅层叠在两个金属氮化物层之间由诸如多晶硅或金属之类的栅极层形成。通过在隧道绝缘体和栅极堆叠之间添加具有嵌入金属纳米点层的高K介电常数膜，可以从该基本结构形成兼容的非易失性存储晶体管。

105. 发明申请

US20070138555A1 One transistor SOI non-volatile random access memory cell 有权
标题翻译：一个晶体管SOI非易失性随机存取存储单元
公开(公告)号：US20070138555A1
公开(公告)日：2007-06-21
申请号：US11656602
申请日：2007-01-23
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L27/12
CPC分类号： G11C16/0466 , G11C7/062 , G11C2207/063 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/66833 , H01L29/7841 , H01L29/78612 , H01L29/7881 , H01L29/792
摘要： Various semiconductor structure embodiments include a substrate, a buried insulator over at least a portion of the substrate, a body region over the buried insulator, first and second source/drain regions to provide a channel region in the body region, a gate insulator over the channel region, and a gate over the gate insulator. The body region includes a silicon nitride region. Various system embodiments includes means for writing a memory cell into a first memory state by trapping charges in the charge trapping region to provide a silicon-on-insulator field effect transistor (SOI-FET) with a first threshold voltage, means for writing the memory cell into a second memory state by neutralizing charges in the charge trapping region to provide the SOI-FET with a second threshold voltage, and means for reading the memory cell using a channel conductance of the SOI-FET to determine a threshold voltage for the SOI-FET.
摘要翻译：各种半导体结构实施例包括衬底，衬底的至少一部分上的掩埋绝缘体，掩埋绝缘体上方的主体区域，用于在主体区域中提供沟道区域的第一和第二源极/漏极区域，沟道区域和栅极绝缘体上的栅极。身体区域包括氮化硅区域。各种系统实施例包括用于通过俘获电荷俘获区域中的电荷将存储器单元写入第一存储器状态以提供具有第一阈值电压的绝缘体上硅场效应晶体管（SOI-FET）的装置，用于写入存储器的装置通过中和电荷俘获区域中的电荷来提供SOI-FET以提供第二阈值电压，以及用于使用SOI-FET的沟道电导读取存储器单元以确定SOI的阈值电压的装置， -FET。

106. 发明授权

US07190043B2 Techniques to create low K ILD for beol 有权
标题翻译：创造低K ILD的技术为beol
公开(公告)号：US07190043B2
公开(公告)日：2007-03-13
申请号：US10931140
申请日：2004-08-31
申请人： Arup Bhattacharyya , Paul A. Farrar
发明人： Arup Bhattacharyya , Paul A. Farrar
IPC分类号： H01L29/00 , H01L23/48
CPC分类号： H01L23/53295 , H01L21/02126 , H01L21/02203 , H01L21/02321 , H01L21/02337 , H01L21/02351 , H01L21/31695 , H01L21/7682 , H01L21/76825 , H01L23/5222 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at least one trench. After the metal layer is formed, voids are formed in the insulator layer. One aspect of the present subject matter relates to an integrated circuit. In various embodiments, the integrated circuit includes an insulator structure having a plurality of voids that have a maximum size, and a metal layer formed in the insulator structure. The maximum size of the voids is larger than the minimum photo dimension of the metal layer such that a maximum-sized void is capable of extending between a first and second metal line in the metal layer. Other aspects are provided herein.
摘要翻译：本主题的一个方面涉及形成层间电介质（ILD）的方法。在该方法的各种实施例中，形成绝缘体层，在绝缘体层中形成至少一个沟槽，并且在该至少一个沟槽中形成金属层。在形成金属层之后，在绝缘体层中形成空隙。本主题的一个方面涉及集成电路。在各种实施例中，集成电路包括具有多个具有最大尺寸的空隙的绝缘体结构和形成在绝缘体结构中的金属层。空隙的最大尺寸大于金属层的最小照片尺寸，使得最大尺寸的空隙能够在金属层中的第一和第二金属线之间延伸。本文提供了其他方面。

107. 发明申请

US20070052011A1 Scalable multi-functional and multi-level nano-crystal non-volatile memory device 有权
标题翻译：可扩展的多功能和多级纳米晶体非易失性存储器件
公开(公告)号：US20070052011A1
公开(公告)日：2007-03-08
申请号：US11210363
申请日：2005-08-24
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , B82Y10/00 , G11C16/10 , H01L27/115 , H01L29/42332 , H01L29/513
摘要： A multi-functional and multi-level memory cell is comprised of a tunnel layer formed over a substrate. In one embodiment, the tunnel layer is comprised of two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from HfSiON. A control gate is formed over the charge blocking layer. A discrete trapping layer is embedded in either the tunnel layer or the charge blocking layer, depending on the desired level of non-volatility. The closer the discrete trapping layer is formed to the substrate/insulator interface, the lower the non-volatility of the device. The discrete trapping layer is formed from nano-crystals having a uniform size and distribution.
摘要翻译：多功能和多层存储单元由在衬底上形成的隧道层组成。在一个实施例中，隧道层由两层构成，例如HfO 2和LaAlO 3。在隧道层上形成电荷阻挡层。在一个实施方案中，该层由HfSiON形成。控制栅极形成在电荷阻挡层上。离散的捕获层嵌入在隧道层或电荷阻挡层中，这取决于期望的非挥发性水平。离散捕获层越靠近衬底/绝缘体界面，器件的非易失性越低。离散捕获层由具有均匀尺寸和分布的纳米晶体形成。

108. 发明授权

US07176073B2 Methods of forming memory cells having diodes and electrode plates connected to source/drain regions 有权
标题翻译：形成具有连接到源极/漏极区域的二极管和电极板的存储器单元的方法
公开(公告)号：US07176073B2
公开(公告)日：2007-02-13
申请号：US10892340
申请日：2004-07-14
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , G11C16/0466 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/1054 , H01L29/42324 , H01L29/66742 , H01L29/66825 , H01L29/66833 , H01L29/78621 , H01L29/78687 , H01L29/7881
摘要： The invention pertains to thin film constructions comprising NVRAM devices built over a versatile substrate base. In particular aspects, a device includes a body region, and further include first and second diffusion regions formed in the body region. A channel region is in the body region between the first and second diffusion regions. A gate insulator stack is above the channel region, and a gate is over the gate insulator stack. The gate insulator stack includes a floating plate charge center which is electrically connected to the second diffusion region. The memory device includes a diode which connects the body region to the second diffusion region such that the floating plate is charged when the diode is reversed biased. The invention also includes electronic systems comprising novel TFT-based NVRAM devices.
摘要翻译：本发明涉及包括在通用基板基底上构建的NVRAM器件的薄膜结构。在具体方面，一种装置包括身体区域，并且还包括形成在身体区域中的第一和第二扩散区域。沟道区位于第一和第二扩散区之间的体区。栅极绝缘体堆叠在沟道区域的上方，栅极位于栅极绝缘体堆叠之上。栅极绝缘体堆叠包括电连接到第二扩散区的浮置板电荷中心。存储器件包括将体区连接到第二扩散区的二极管，使得当二极管被反向偏置时浮置板被充电。本发明还包括包括新颖的基于TFT的NVRAM器件的电子系统。

109. 发明授权

US07166888B2 Scalable high density non-volatile memory cells in a contactless memory array 有权
公开(公告)号：US07166888B2
公开(公告)日：2007-01-23
申请号：US11044703
申请日：2005-01-27
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , G11C11/5621 , G11C16/0483 , H01L27/115 , H01L27/11556 , H01L29/7881
摘要： A plurality of split gate non-volatile memory cells are formed vertically in a trench along the sidewalls. Each cell is comprised of a bistable element and an adjacent fixed gate threshold element that share a common respective control gate/access gate. The bistable element has a gate insulator stack that is comprised of either a floating gate or a charge trapping layer over a tunnel insulator. A plurality of silicon rich nitride layers are formed over the floating gate or charge trapping layer and separated by a high dielectric constant layer.

110. 发明授权

US07130216B2 One-device non-volatile random access memory cell 有权
公开(公告)号：US07130216B2
公开(公告)日：2006-10-31
申请号：US10788230
申请日：2004-02-26
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： G11C16/04
CPC分类号： H01L21/28273 , G11C16/0416 , H01L27/108 , H01L27/115 , H01L29/42324 , H01L29/66825 , H01L29/7886 , H01L29/8611 , H01L29/872
摘要： One aspect of the present subject matter relates to a one-device non-volatile memory cell. The memory cell includes a body region, a first diffusion region and a second diffusion region formed in the body region. A channel region is formed in the body region between the first diffusion region and the second diffusion region. The memory cell includes a gate insulator stack formed above the channel region, and a gate to connect to a word line. The gate insulator stack includes a floating plate to selectively hold a charge. The floating plate is connected to the second diffusion region. The memory cell includes a diode that connects the body region to the second diffusion region such that the floating plate is charged when the diode is reversed biased. Other aspects are provided herein.

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