专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

101. 发明授权

US07916547B2 Method for controlling a non-volatile semiconductor memory device 有权
标题翻译：用于控制非易失性半导体存储器件的方法
公开(公告)号：US07916547B2
公开(公告)日：2011-03-29
申请号：US12209486
申请日：2008-09-12
申请人： Koji Hosono
发明人： Koji Hosono
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/26 , G11C16/3418 , G11C16/3454 , G11C2211/565
摘要： A non-volatile semiconductor memory device has a NAND string, in which multiple memory cells are connected in series. A read procedure is performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof. In the read procedure, a first read pass voltage is applied to unselected memory cells except an adjacent and unselected memory cell disposed adjacent to the selected memory cell, the adjacent and unselected memory cell being completed in data write later than the selected memory cell, and a second read pass voltage higher than the first read pass voltage is applied to the adjacent and unselected memory cell.
摘要翻译：非易失性半导体存储器件具有串联多个存储单元的NAND串。在所选择的存储单元被施加选定电压的同时驱动未选择的存储单元而不考虑其单元数据的情况下，对NAND串中的所选存储单元执行读取过程。在读取过程中，第一读取通过电压被施加到非选择存储单元，除了邻近所选存储单元设置的相邻和非选择存储单元之外，相邻和未选择的存储单元在比所选择的存储器单元晚的数据写入中完成;以及将高于第一读通过电压的第二读通过电压施加到相邻和未选择的存储单元。

102. 发明授权

US07911844B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07911844B2
公开(公告)日：2011-03-22
申请号：US12337808
申请日：2008-12-18
申请人： Dai Nakamura , Hiroyuki Kutsukake , Kenji Gomikawa , Takeshi Shimane , Mitsuhiro Noguchi , Koji Hosono , Masaru Koyanagi , Takashi Aoi
发明人： Dai Nakamura , Hiroyuki Kutsukake , Kenji Gomikawa , Takeshi Shimane , Mitsuhiro Noguchi , Koji Hosono , Masaru Koyanagi , Takashi Aoi
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/24
摘要： A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.
摘要翻译：非挥发性半导体存储装置包括：具有布置在其中的存储单元的存储单元阵列，所述存储单元以非易失性方式存储数据; 以及向存储单元传送电压的多个转移晶体管，用于相对于存储单元进行数据读取，写入和擦除操作的电压。每个转移晶体管包括：通过栅极绝缘膜形成在半导体衬底上的栅电极; 以及形成为将栅极电极夹在其间并用作漏极/源极层的扩散层。上层布线设置在扩散层上方，并具有预定电压，以至少在传输晶体管导通时防止扩散层的耗尽。

103. 发明授权

US07894268B2 Semiconductor memory device and method of erasing data therein 有权
标题翻译：半导体存储器件及其中擦除数据的方法
公开(公告)号：US07894268B2
公开(公告)日：2011-02-22
申请号：US12773280
申请日：2010-05-04
申请人： Koji Hosono
发明人： Koji Hosono
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/3404 , G11C16/344
摘要： A semiconductor memory device includes a memory cell array of NAND cell units. The NAND cell unit includes a plurality of electrically erasable programmable nonvolatile memory cells connected serially, and a first and a second selection transistor provided to connect both ends of the memory cells to a bit line and a source line, respectively. The semiconductor memory device also includes dummy cells inserted in the NAND cell unit adjacent to the first and second selection transistors, respectively. The dummy cells in the NAND cell unit are erased simultaneously with the memory cells under a weaker erase potential condition than that for the memory cells and set in a higher threshold distribution than an erased state of the memory cells.
摘要翻译：半导体存储器件包括NAND单元单元的存储单元阵列。 NAND单元单元包括串联连接的多个电可擦除可编程非易失性存储单元，以及分别将存储单元的两端连接到位线和源极线的第一和第二选择晶体管。半导体存储器件还包括分别插入与NAND单元单元相邻的第一和第二选择晶体管的虚拟单元。与存储单元相比，NAND单元单元中的虚设单元与存储单元同时擦除，而且存储单元的擦除电位低于存储单元，并且设置在比存储单元的擦除状态更高的阈值分布。

104. 发明授权

US07859907B2 Non-volatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07859907B2
公开(公告)日：2010-12-28
申请号：US12621134
申请日：2009-11-18
申请人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
发明人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/0483 , G11C5/145 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.
摘要翻译：非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中在预定的阈值电平范围内。在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于要存储在其中一个存储单元中的一位二电平数据。

105. 发明授权

US07839679B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07839679B2
公开(公告)日：2010-11-23
申请号：US12043510
申请日：2008-03-06
申请人： Koji Hosono , Masahiro Yoshihara , Dai Nakamura , Youichi Kai
发明人： Koji Hosono , Masahiro Yoshihara , Dai Nakamura , Youichi Kai
IPC分类号： G11C16/06 , G11C5/14
CPC分类号： G11C16/30 , G11C5/14 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory according to an aspect of the invention includes memory cell arrays including plural cell units, a power supply pad disposed on one end in a first direction of the memory cell arrays, and page buffers disposed in the first direction of the memory cell arrays. The nonvolatile semiconductor memory also includes plural bit lines which are disposed on the memory cell arrays while extending in the first direction and a first power supply line which is disposed on the plural bit lines on the memory cell arrays to connect the power supply pad and the page buffers.
摘要翻译：根据本发明的一个方面的非易失性半导体存储器包括存储单元阵列，其包括多个单元单元，设置在存储单元阵列的第一方向上的一端的电源垫，以及设置在存储单元的第一方向上的页缓冲器阵列非易失性半导体存储器还包括多个位线，它们沿着第一方向延伸设置在存储单元阵列上，第一电源线设置在存储单元阵列上的多个位线上，以将电源焊盘和页面缓冲区。

106. 发明申请

US20100232208A1 METHOD OF EXECUTING A FORMING OPERATION TO VARIABLE RESISTANCE ELEMENT 有权
标题翻译：将成形操作的方法用于可变电阻元件
公开(公告)号：US20100232208A1
公开(公告)日：2010-09-16
申请号：US12721092
申请日：2010-03-10
申请人： Hiroshi MAEJIMA , Koji Hosono
发明人： Hiroshi MAEJIMA , Koji Hosono
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C29/50 , G11C13/0004 , G11C13/0064 , G11C29/028 , G11C2013/0083 , G11C2013/0088 , G11C2029/0403
摘要： A method of executing a forming operation to a variable resistance element to render a resistance value of the variable resistance element capable of transition, the variable resistance element being included in a memory cell connected between a first wiring and a second wiring and changing the resistance value by electrical control, comprises applying a voltage required to execute the forming operation to the variable resistance element between the first and second wirings and changing the first wiring to a floating state.
摘要翻译：一种向可变电阻元件执行形成操作以使可变电阻元件能够转变的电阻值的方法，所述可变电阻元件包括在连接在第一布线和第二布线之间并改变电阻值的存储单元中通过电气控制，包括向第一和第二布线之间的可变电阻元件施加执行成形操作所需的电压并将第一布线改变为浮动状态。

107. 发明申请

US20100214820A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100214820A1
公开(公告)日：2010-08-26
申请号：US12710661
申请日：2010-02-23
申请人： Koji Hosono , Hiroshi Maejima
发明人： Koji Hosono , Hiroshi Maejima
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C8/14 , G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C2013/0076 , G11C2013/0088 , G11C2013/009 , G11C2213/72
摘要： A semiconductor memory device comprises: a memory cell array having memory cells disposed at a crossing-point of a plurality of first lines and a plurality of second lines and a control circuit configured to apply a first voltage to selected one or more of the first lines, and to apply a second voltage having a value smaller than the first voltage to selected one of the second lines, such that a certain potential difference is applied to selected one or more of the memory cells. The control circuit adjusts the second voltage based on a position of the selected one or more of the memory cells within the memory cell array and a number of the selected one or more of the memory cells on which an operation is simultaneously executed, during application of the potential difference to the selected one or more of the memory cells.
摘要翻译：半导体存储器件包括：存储单元阵列，其具有设置在多个第一线的交叉点处的存储单元和多条第二线;以及控制电路，被配置为向所选择的一条或多条第一条线施加第一电压并且将具有小于第一电压的值的第二电压施加到所选择的第二行中的一个，使得对所选择的一个或多个存储器单元施加一定的电位差。控制电路根据存储单元阵列内所选择的一个或多个存储器单元的位置以及在其中同时执行操作的所选择的一个或多个存储器单元的数量来调整第二电压，与所选择的一个或多个存储器单元的电位差。

108. 发明申请

US20100091551A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20100091551A1
公开(公告)日：2010-04-15
申请号：US12556272
申请日：2009-09-09
申请人： Koji Hosono , Satoru Takase
发明人： Koji Hosono , Satoru Takase
IPC分类号： G11C11/00 , G11C7/06
CPC分类号： G11C13/0064 , G11C13/0004 , G11C13/0011 , G11C13/0069 , G11C2013/0078 , G11C2213/71 , G11C2213/72
摘要： A semiconductor storage device includes: a memory cell array having memory cells; and a control circuit configured to apply a first voltage to a selected one of first wirings as well as a second voltage to a selected one of second wirings. The control circuit includes: a signal output circuit configured to output a first signal based on a first current flowing through a selected memory cell and a reference current; and a current retaining circuit configured to retain a second current flowing through the first wirings or a wiring electrically connected to the first wirings during a certain period of time. The signal output circuit is configured to determine the first current based on the second current retained by the current retaining circuit. The control circuit is configured to stop application of the first voltage to the first wirings based on the first signal.
摘要翻译：半导体存储装置包括：具有存储单元的存储单元阵列; 以及控制电路，被配置为将第一电压施加到所选择的第一布线中的一个，以及将第二电压施加到所选择的第二布线中的一个。控制电路包括：信号输出电路，被配置为基于流过所选择的存储单元的第一电流和参考电流来输出第一信号; 以及电流保持电路，其被配置为在一定时间段期间保持流过所述第一布线的第二电流或电连接到所述第一布线的布线。信号输出电路被配置为基于由电流保持电路保持的第二电流来确定第一电流。控制电路被配置为基于第一信号停止将第一电压施加到第一布线。

109. 发明授权

US07639544B2 Non-volatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07639544B2
公开(公告)日：2009-12-29
申请号：US12257828
申请日：2008-10-24
申请人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
发明人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/0483 , G11C5/145 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.
摘要翻译：非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中在预定的阈值电平范围内。在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于要存储在其中一个存储单元中的一位二电平数据。

110. 发明授权

US07619921B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07619921B2
公开(公告)日：2009-11-17
申请号：US11530551
申请日：2006-09-11
申请人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G11C16/06
CPC分类号： G11C29/789 , G11C7/20 , G11C16/20 , G11C2029/4402
摘要： A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.
摘要翻译：非易失性半导体存储器包括具有多个电可重写非易失性存储单元的存储单元阵列。存储单元阵列设置有初始设置的数据区，其中编程有初始设置数据，用于决定存储器操作要求。非易失性半导体存储器还包括初始设置数据锁存器。在初始设置操作中，存储单元阵列的初始设置数据被读出并传送到数据锁存器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式