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101. 发明授权

US08335967B2 Memory system 有权
标题翻译：内存系统
公开(公告)号：US08335967B2
公开(公告)日：2012-12-18
申请号：US12673904
申请日：2008-08-07
申请人： Daisaburo Takashima
发明人： Daisaburo Takashima
IPC分类号： G11C29/00
CPC分类号： G11C11/5621 , G06F11/1068 , G11C11/5657 , G11C16/0483 , G11C2211/5647
摘要： A memory system that can efficiently relieve a large number of defective bits with a small number of redundant bits is provided in a Flash-EEPROM nonvolatile memory. A memory system according to an embodiment of the present invention comprises a Flash-EEPROM memory in which a plurality of memory cells having a floating gate or a charge trapping layer and capable of electrically erasing and writing data are arranged; a control circuit that controls a cache memory and the Flash-EEPROM memory; and an interface circuit that communicates with outside, wherein a plurality of group data and a plurality of flag data for storing presence of inversion of all bits of respective group data are stored in a memory area of the Flash-EEPROM memory.
摘要翻译：在闪存EEPROM非易失性存储器中提供了一种能够以少量冗余位有效地解除大量缺陷位的存储器系统。根据本发明的实施例的存储器系统包括闪存EEPROM存储器，其中布置具有浮置栅极或电荷捕获层并且能够电擦除和写入数据的多个存储单元; 控制电路，控制高速缓冲存储器和闪存EEPROM存储器; 以及与外部通信的接口电路，其中存储有多个组数据和用于存储各个组数据的所有比特的反转存在的多个标志数据存储在闪存EEPROM存储器的存储区域中。

102. 发明授权

US08218372B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08218372B2
公开(公告)日：2012-07-10
申请号：US12877862
申请日：2010-09-08
申请人： Daisaburo Takashima
发明人： Daisaburo Takashima
IPC分类号： G11C11/34
CPC分类号： G11C11/412 , H01L27/0207 , H01L27/11 , H01L27/1104
摘要： According to one embodiment, a first node is connected to a gate of a second PMOS and a gate of a second NMOS, a second node is connected to a gate of a first PMOS and a gate of a first NMOS, a gate of the first transistor is connected to a first signal line, a source of a first transistor is connected to the first node, and a drain of the first transistor is connected to the second node, a gate of a second transistor is connected to the second node, a source of the second transistor is connected to a third node, and a drain of the second transistor is connected to a second signal line, and a gate of a third transistor is connected to a third signal line, a source of the third transistor is connected to a fourth signal line, and a drain of the third transistor is connected to the third node.
摘要翻译：根据一个实施例，第一节点连接到第二PMOS的栅极和第二NMOS的栅极，第二节点连接到第一PMOS的栅极和第一NMOS的栅极，第一NMOS的栅极晶体管连接到第一信号线，第一晶体管的源极连接到第一节点，第一晶体管的漏极连接到第二节点，第二晶体管的栅极连接到第二节点，第二晶体管的源极连接到第三节点，第二晶体管的漏极连接到第二信号线，第三晶体管的栅极连接到第三信号线，第三晶体管的源极连接到第四信号线，并且第三晶体管的漏极连接到第三节点。

103. 发明授权

US08045357B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08045357B2
公开(公告)日：2011-10-25
申请号：US12553819
申请日：2009-09-03
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C11/22 , G11C7/00 , G11C7/22 , G11C7/24
CPC分类号： G11C11/22
摘要： A memory includes a memory cell array including destructive read-out type memory cells; a decoder selecting a cell; a sense amplifier configured to detect the data; and a read and write controller controlling a read operation and a write operation, wherein the read and write controller outputs a logical value of a write enable signal at the start of the read operation in a first period and makes the write enable signal invalid after the read operation starts during the first period, on the basis of the write enable signal and a restore signal keeping an activated state during the first period, the write enable signal being a signal allowing the write operation, the first period being a period from when the read operation starts to when a restore operation for writing the data back to the memory cell is completed.
摘要翻译：存储器包括包括破坏性读出型存储单元的存储单元阵列; 选择单元的解码器; 感测放大器，被配置为检测所述数据; 以及控制读取操作和写入操作的读取和写入控制器，其中所述读取和写入控制器在第一周期中在所述读取操作开始时输出写入使能信号的逻辑值，并使所述写入使能信号在所述写入使能信号之后无效在第一时段期间，基于写使能信号和恢复信号在第一时段期间保持激活状态的读操作开始，写使能信号是允许写操作的信号，第一周期是从当将数据写入存储单元的恢复操作完成时，读操作开始。

104. 发明授权

US07990791B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07990791B2
公开(公告)日：2011-08-02
申请号：US12506815
申请日：2009-07-21
申请人： Tadashi Miyakawa , Daisaburo Takashima
发明人： Tadashi Miyakawa , Daisaburo Takashima
IPC分类号： G11C7/02 , G11C7/00
CPC分类号： G11C7/14 , G11C7/18 , G11C2207/002
摘要： A memory includes a cell array; bit lines; word lines; sense amplifiers; first determination transistors receiving information data and making a connection between a first voltage source and a first determination node be in a conductive or a non-conductive state based on a logic value of the information data; second determination transistors receiving the information data detected by the sense amplifiers and making a connection between the first voltage source and a second determination node be in a conductive or a non-conductive state based on the logic value of the information data; a second voltage source charging the first and the second determination nodes; and a determination unit detecting potentials of the first determination node and the second determination node when a logic of the information data is inverted logically to determine maximum and minimum values of potential of the information data.
摘要翻译：存储器包括单元阵列; 位线字线感测放大器; 基于信息数据的逻辑值，接收信息数据的第一确定晶体管和第一电压源与第一确定节点之间的连接处于导通状态或非导通状态; 基于所述信息数据的逻辑值，接收由所述读出放大器检测并且使所述第一电压源与所述第二判定节点之间的连接的信息数据的第二判定晶体管处于导通状态或非导通状态; 对所述第一和第二确定节点充电的第二电压源; 以及确定单元，当所述信息数据的逻辑逻辑地反转时，检测所述第一确定节点和所述第二确定节点的电位，以确定所述信息数据的最大和最小值。

105. 发明授权

US07746164B2 Voltage generating circuit 有权
标题翻译：电压发生电路
公开(公告)号：US07746164B2
公开(公告)日：2010-06-29
申请号：US12027699
申请日：2008-02-07
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/465
摘要： Disclosed is a voltage generating circuit which steps down a voltage to output a stepped down voltage. The voltage generating circuit includes first and second transistors. The drains of the first and second transistors are connected to a higher voltage power supply. The gate of the first transistor is connected to the gate of the second transistor. The voltage of the gate of the first transistor is controlled by a control circuit such that a voltage of the source of the first transistor can reach a predetermined voltage. A stepped down voltage is outputted from the source of the second transistor.
摘要翻译：公开了一种降压电压以输出降压的电压产生电路。电压产生电路包括第一和第二晶体管。第一和第二晶体管的漏极连接到较高电压的电源。第一晶体管的栅极连接到第二晶体管的栅极。第一晶体管的栅极的电压由控制电路控制，使得第一晶体管的源极的电压可以达到预定电压。从第二晶体管的源极输出降压电压。

106. 发明授权

US07733683B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07733683B2
公开(公告)日：2010-06-08
申请号：US11968829
申请日：2008-01-03
申请人： Daisaburo Takashima , Ryu Ogiwara
发明人： Daisaburo Takashima , Ryu Ogiwara
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： Disclosed is a semiconductor memory including ferroelectric capacitors. Memory cells each including a ferroelectric capacitor and an insulted-gate-type cell transistor are connected to a corresponding one of bit lines. Insulated-gate-type separating transistors are connected between multiple bit-line selecting transistors and multiple sense amplifiers, respectively. When the separating transistors are turned on, data retained in the sense amplifiers are capable of being written to the memory cells during the same time period substantially.
摘要翻译：公开了一种包括铁电电容器的半导体存储器。每个包括铁电电容器和绝缘栅型单元晶体管的存储单元连接到相应的位线。绝缘栅型分离晶体管分别连接在多个位线选择晶体管和多个读出放大器之间。当分离晶体管导通时，保持在读出放大器中的数据能够在相同的时间段内基本上被写入存储器单元。

107. 发明授权

US07724581B2 Discharge order control circuit and memory device 有权
标题翻译：放电顺序控制电路和存储器件
公开(公告)号：US07724581B2
公开(公告)日：2010-05-25
申请号：US11671107
申请日：2007-02-05
申请人： Ryu Ogiwara , Shinichiro Shiratake , Daisaburo Takashima
发明人： Ryu Ogiwara , Shinichiro Shiratake , Daisaburo Takashima
IPC分类号： G11C16/06 , G05F3/02
CPC分类号： G11C5/14
摘要： A discharge order control circuit includes a pool circuit a delay circuit and a discharge unit to control a discharge order of internal power supplies. The pool circuit stores electric charges provided from a potential of an external power supply. The delay circuit operates on the electric charges stored in the pool circuit and delays a discharge signal generated when potential of the external power supply is lowered to a predetermined potential level. The delay circuit includes an inverter array having a plurality of stages each containing an inverter. The plurality of stages include a final stage that outputs the delayed discharge signal. Only the inverter of the final stage generates an RC delay.
摘要翻译：放电顺序控制电路包括：缓冲电路，延迟电路和用于控制内部电源的放电顺序的放电单元。池电路存储从外部电源的电位提供的电荷。延迟电路对存储在池电路中的电荷进行操作，并且当外部电源的电位降低到预定电位电平时，延迟产生的放电信号。延迟电路包括具有多个级的逆变器阵列，每个级包含反相器。多个级包括输出延迟放电信号的最后级。只有最终级的逆变器产生RC延迟。

108. 发明申请

US20100107021A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100107021A1
公开(公告)日：2010-04-29
申请号：US12523607
申请日：2008-09-30
申请人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda
发明人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda
IPC分类号： G11C29/52 , G06F11/10
CPC分类号： G11C16/349 , G06F11/1068 , G11C11/005 , G11C16/3431
摘要： This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.
摘要翻译：本公开涉及存储器，包括：包括存储器组的第一存储器区域，包括多个存储器单元，分别分配给存储器组的地址，存储器组分别是数据擦除操作的单位; 第二存储器区域暂时存储从第一存储器区域读取的数据或者暂时存储要写入到第一存储器区域的数据; 读取计数器，存储每个存储器组的数据读取计数; 错误校正电路，计算读取数据的错误位数; 以及执行刷新操作的控制器，其中存储在一个存储器组中的读取数据被临时存储在第二存储器区域中，并且当读取数据写入同一存储器组时，当错误位计数超过第一阈值时或者当数据读取计数超过第二阈值时。

109. 发明授权

US07697318B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07697318B2
公开(公告)日：2010-04-13
申请号：US11964260
申请日：2007-12-26
申请人： Ryo Fukuda , Daisaburo Takashima
发明人： Ryo Fukuda , Daisaburo Takashima
IPC分类号： G11C11/24
CPC分类号： G11C11/405 , G11C5/063 , G11C7/18 , G11C8/14 , G11C11/4097 , H01L27/0207 , H01L27/10897
摘要： A memory cell array includes a plurality of memory cells arranged at intersections of bit line pairs and word lines. Each memory cell includes a first transistor having one main electrode connected to a first bit line, a second transistor having one main electrode connected to a second bit line, a first node electrode for data-storage connected to the other main electrode of the first transistor, a second node electrode for data-storage connected to the other main electrode of the second transistor, and a shield electrode formed surrounding the first and second node electrodes. The first and second transistors have respective gates both connected to an identical word line, and the first and second bit lines are connected to an identical sense amp. The first and second node electrodes, the first and second bit lines, the word line and the shield electrode are isolated from each other using insulating films.
摘要翻译：存储单元阵列包括布置在位线对和字线的交点处的多个存储单元。每个存储单元包括具有连接到第一位线的一个主电极的第一晶体管，具有连接到第二位线的一个主电极的第二晶体管，用于数据存储的第一节点电极连接到第一晶体管的另一个主电极，连接到第二晶体管的另一个主电极的用于数据存储的第二节点电极和围绕第一和第二节点电极形成的屏蔽电极。第一和第二晶体管具有连接到相同字线的相应门，并且第一和第二位线连接到相同的感测放大器。第一和第二节点电极，第一和第二位线，字线和屏蔽电极使用绝缘膜彼此隔离。

110. 发明申请

US20090231902A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090231902A1
公开(公告)日：2009-09-17
申请号：US12401184
申请日：2009-03-10
申请人： Daisaburo Takashima
发明人： Daisaburo Takashima
IPC分类号： G11C11/22 , G11C11/24 , G11C8/00 , G11C11/416
CPC分类号： G11C11/22 , G11C5/063 , H01L27/11504 , H01L27/11507
摘要： A memory includes ferroelectric capacitors; cell transistors each including a drain connected to one electrode of each ferroelectric capacitor, and a gate connected to the word line; and memory cell blocks each including a reset transistor, a block selection transistor, and memory cells including the ferroelectric capacitors and the cell transistors, wherein sources of the cell transistors are connected to the plate lines, the other electrode of the ferroelectric capacitor is connected to one of the sub-bit lines, a source and a drain of the block selection transistor are connected to one of the sub-bit lines and one of the bit lines, a source of the reset transistor is connected to one of the plate lines or a fixed potential, and a drain of the reset transistor in each memory cell block is connected to one of the sub-bit lines, and the memory cell blocks configure a memory cell array.
摘要翻译：存储器包括铁电电容器; 每个单体晶体管包括连接到每个铁电电容器的一个电极的漏极和连接到该字线的栅极; 以及包括复位晶体管，块选择晶体管和包括铁电电容器和单元晶体管的存储单元的存储单元块，其中单元晶体管的源极连接到板极线，强电介质电容器的另一个电极连接到子位线之一，块选择晶体管的源极和漏极连接到子位线之一和位线中的一个，复位晶体管的源极连接到板线之一或每个存储单元块中的复位晶体管的固定电位和漏极连接到一个子位线，并且存储单元块配置存储单元阵列。

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