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101. 发明授权

US06815375B2 Methods of forming dielectric materials and methods of processing semiconductor substrates 有权
标题翻译：形成介电材料的方法和处理半导体衬底的方法
公开(公告)号：US06815375B2
公开(公告)日：2004-11-09
申请号：US10701301
申请日：2003-11-03
申请人： John T. Moore
发明人： John T. Moore
IPC分类号： H01L2131
CPC分类号： H01L21/0217 , C23C16/0218 , C23C16/345 , H01L21/02271 , H01L21/02315 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28238 , H01L21/3144 , H01L21/3185 , H01L29/513 , H01L29/518
摘要： The invention encompasses a method of forming silicon nitride on a silicon-oxide-comprising material. The silicon-oxide-comprising material is exposed to activated nitrogen species from a nitrogen-containing plasma to introduce nitrogen into an upper portion of the material. The nitrogen is thermally annealed within the material to bond at least some of the nitrogen to silicon proximate the nitrogen. After the annealing, silicon nitride is chemical vapor deposited on the nitrogen-containing upper portion of the material. The invention also encompasses a method of forming a transistor device. A silicon-oxide-comprising layer is formed over a substrate. The silicon-oxide-comprising layer is exposed to nitrogen from a nitrogen-containing plasma to introduce nitrogen into an upper portion of the layer. The nitrogen is thermally annealed within the layer to bond at least some of the nitrogen silicon proximate the nitrogen. After the annealing, silicon nitride is chemical vapor deposited on the nitrogen-containing upper portion of the layer. At least one conductive gate layer is formed over the silicon nitride, and defines a gate layer. A pair of source/drain regions are formed proximate the gate layer and gatedly connected to one another through a channel region that is beneath the gate layer. Additionally, the invention encompasses transistor device structures.

102. 发明授权

US06751114B2 Method for programming a memory cell 失效
标题翻译：编程存储单元的方法
公开(公告)号：US06751114B2
公开(公告)日：2004-06-15
申请号：US10109088
申请日：2002-03-28
申请人： Terry L. Gilton , John T. Moore
发明人： Terry L. Gilton , John T. Moore
IPC分类号： G11C1700
CPC分类号： G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C2013/0076 , G11C2013/009
摘要： A method for reading and verifying the state of a memory cell during a write operation before writing allows a decision to be made whether to write to the cell or not based on the current state of the cell.
摘要翻译：在写入之前的写入操作期间读取和验证存储器单元的状态的方法允许基于单元的当前状态来决定是否写入单元。

103. 发明授权

US06727192B2 Methods of metal doping a chalcogenide material 有权
标题翻译：金属掺杂硫族化物材料的方法
公开(公告)号：US06727192B2
公开(公告)日：2004-04-27
申请号：US09797635
申请日：2001-03-01
申请人： John T. Moore , Terry L. Gilton
发明人： John T. Moore , Terry L. Gilton
IPC分类号： H01L21324
CPC分类号： H01L45/04 , H01L27/101 , H01L28/24 , H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1658 , H01L45/1675
摘要： A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and chalcogenide material and diffuse at least some of the metal outwardly into the chalcogenide material. A method of metal doping a chalcogenide material includes surrounding exposed outer surfaces of a projecting metal mass with chalcogenide material. Irradiating is conducted through the chalcogenide material to the projecting metal mass effective to break a chalcogenide bond of the chalcogenide material at an interface of the projecting metal mass outer surfaces and diffuse at least some of the projecting metal mass outwardly into the chalcogenide material. In certain aspects, the above implementations are incorporated in methods of forming non-volatile resistance variable devices. In one implementation, a non-volatile resistance variable device in a highest resistance state for a given ambient temperature and pressure includes a resistance variable chalcogenide material having metal ions diffused therein. Opposing first and second electrodes are received operatively proximate the resistance variable chalcogenide material. At least one of the electrodes has a conductive projection extending into the resistance variable chalcogenide material.
摘要翻译：金属掺杂硫族化物材料的方法包括在衬底上形成金属。在金属上形成硫族化物材料。通过硫属化物材料对金属进行辐射，有效地在金属和硫族化物材料的界面处破坏硫族化物材料的硫族化物键，并将至少一些金属向外扩散到硫族化物材料中。金属掺杂硫族化物材料的方法包括用硫族化物材料包围突出的金属块的暴露的外表面。通过硫族化物材料将辐射照射到突出金属质量块上，有效地在突出的金属质量外表面的界面处破坏硫族化物材料的硫族化物键，并将至少一些突出的金属块向外扩散到硫族化物材料中。在某些方面，上述实施方式被并入形成非易失性电阻可变器件的方法中。在一个实施方案中，对于给定的环境温度和压力，最高电阻状态的非易失性电阻可变器件包括在其中扩散有金属离子的电阻变化硫属化物材料。反向的第一和第二电极在电阻可变硫属化物材料上可操作地接收。至少一个电极具有延伸到电阻可变硫族化物材料中的导电突起。

104. 发明授权

US06713807B2 Films doped with carbon for use in integrated circuit technology 有权
公开(公告)号：US06713807B2
公开(公告)日：2004-03-30
申请号：US10229351
申请日：2002-08-28
申请人： Ronald A. Weimer , John T. Moore
发明人： Ronald A. Weimer , John T. Moore
IPC分类号： H01L27108
CPC分类号： H01L21/0276 , H01L21/02126 , H01L21/02219 , H01L21/02271 , H01L21/31116 , H01L21/3145 , H01L21/3146 , H01L21/3148 , H01L21/31604 , H01L21/31633 , H01L21/76802 , H01L21/76829 , H01L21/76897 , H01L27/10811 , H01L27/10855 , H01L27/10888 , H01L28/91 , Y10S257/90 , Y10S438/97
摘要： The invention pertains to films comprising silicon, oxygen and carbon and the use of the films in integrated circuit technology, such as capacitor constructions, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capacitors, DRAMs and semiconductive material assemblies.

105. 发明授权

US06686298B1 Methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates 有权
标题翻译：在半导体衬底上形成结构的方法，以及形成与半导体衬底相关的晶体管的方法
公开(公告)号：US06686298B1
公开(公告)日：2004-02-03
申请号：US09602089
申请日：2000-06-22
申请人： Kevin L. Beaman , John T. Moore
发明人： Kevin L. Beaman , John T. Moore
IPC分类号： H01L2131
CPC分类号： H01L21/823842 , H01L21/823857 , H01L27/105 , H01L27/1052 , H01L27/11546 , Y10S257/90
摘要： The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 Å above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer.
摘要翻译：本发明包括在半导体衬底上形成结构的方法。在至少一些基底上形成含二氧化硅层。在含二氧化硅层内形成氮。二氧化硅内的基本上所有的氮基本上都在衬底之上至少10埃。在二氧化硅层内形成氮之后，在二氧化硅层上形成导电掺杂的硅。

106. 发明授权

US06660657B1 Methods of incorporating nitrogen into silicon-oxide-containing layers 有权
标题翻译：将氮掺入含氧化硅的层中的方法
公开(公告)号：US06660657B1
公开(公告)日：2003-12-09
申请号：US09633556
申请日：2000-08-07
申请人： Gurtej S. Sandhu , John T. Moore , Neal R. Rueger
发明人： Gurtej S. Sandhu , John T. Moore , Neal R. Rueger
IPC分类号： H01L2131
CPC分类号： H01L21/02332 , H01L21/0234 , H01L21/265 , H01L21/28061 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/513 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer. Source/drain regions are formed within the semiconductive substrate, and are gatedly connected to one another by the at least one conductive layer. The invention also encompasses transistor structures.
摘要翻译：本发明包括将氮掺入含氧化硅的层中的方法。将含氧化硅的层暴露于含氮等离子体中以将氮引入层中。氮气随后在层内热退火以将至少一些氮与硅结合在层内。本发明还包括形成晶体管的方法。在半导体衬底上形成栅氧化层。栅氧化层包括二氧化硅。将栅极氧化层暴露于含氮等离子体中以将氮引入层中，并且在暴露期间该层保持在小于或等于400℃。随后，层内的氮被热退火以将至少大部分氮与硅结合。在栅极氧化物层上形成至少一个导电层。源极/漏极区域形成在半导体衬底内，并且通过至少一个导电层彼此门控连接。本发明还包括晶体管结构。

107. 发明授权

US06639243B2 DRAM cell constructions 有权
标题翻译： DRAM单元结构
公开(公告)号：US06639243B2
公开(公告)日：2003-10-28
申请号：US10012233
申请日：2001-12-05
申请人： Fernando Gonzalez , Kevin L. Beaman , John T. Moore , Ron Weimer
发明人： Fernando Gonzalez , Kevin L. Beaman , John T. Moore , Ron Weimer
IPC分类号： H01L27108
CPC分类号： H01L27/10858 , H01L27/1082 , H01L27/1203 , H01L28/91 , Y10S257/906
摘要： The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate having a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which has a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further includes a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure includes a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.
摘要翻译：本发明包括形成DRAM单元的方法。第一衬底被形成为包括通过绝缘材料彼此分离的第一DRAM子结构。具有单晶材料的第二半导体衬底被结合到第一衬底。在接合之后，第二DRAM子结构形成为与第一DRAM子结构电连接。本发明还包括具有电容器结构的半导体结构以及限定为包围电容器结构的第一衬底。半导体结构还包括结合到第一衬底和电容器结构上的单晶硅衬底。另外，半导体结构包括在单晶硅衬底上的晶体管栅极，并且与电容器结构可操作地连接以限定DRAM单元。

108. 发明授权

US06462402B2 Microelectronic substrate comprised of etch stop layer, stiffening layer, and endpointing layer 有权
标题翻译：微电子衬底由蚀刻停止层，加强层和终点层组成
公开(公告)号：US06462402B2
公开(公告)日：2002-10-08
申请号：US09778318
申请日：2001-02-06
申请人： John T. Moore
发明人： John T. Moore
IPC分类号： H01L21304
CPC分类号： B24B37/013 , B24B49/16 , H01L21/31053 , Y10S257/915
摘要： A method and apparatus for endpointing a planarization process of a microelectronic substrate. In one embodiment, the microelectronic substrate can include a semiconductor base, a first material, such as an oxide, disposed on the base, a second material, such as a nitride, disposed on the first material to stiffen the first material, and an endpointing material, such as polysilicon, disposed on the second material. The endpointing material can have a hardness and/or a fracture resistance that is less than a hardness and/or a fracture resistance of the stiffening material and, in one embodiment, can have a coefficient of friction that is different than surrounding material of the microelectronic substrate so as to be detected when exposed to a planarizing medium.
摘要翻译：一种用于终点微电子衬底的平坦化处理的方法和装置。在一个实施例中，微电子衬底可以包括设置在基底上的半导体基底，第一材料，例如氧化物，设置在第一材料上以加固第一材料的第二材料，例如氮化物，以及终点材料，例如多晶硅，设置在第二材料上。端点材料可以具有小于硬化材料的硬度和/或耐断裂性的硬度和/或抗断裂性，并且在一个实施例中，可以具有与微电子的周围材料不同的摩擦系数以便当暴露于平坦化介质时被检测。

109. 发明授权

US06429151B1 Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers 有权
标题翻译：包括氮化硅的半导体晶片组件，形成氮化硅的方法以及减少半导体晶片上的应力的方法
公开(公告)号：US06429151B1
公开(公告)日：2002-08-06
申请号：US09619468
申请日：2000-07-19
申请人： John T. Moore , Scott J. DeBoer , Mark Fischer
发明人： John T. Moore , Scott J. DeBoer , Mark Fischer
IPC分类号： H01L2131
CPC分类号： H01L21/3185 , H01L21/32 , H01L21/76202
摘要： In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of said at least two portions generating a compressive force against the other of the at least two portions, and the other of the at least two portions generating a tensile force against the one of the at least two portions. In another aspect, the invention includes a method of reducing stress on semiconductive wafer, the semiconductive wafer having a pair of opposing surfaces and having more silicon nitride over one of the opposing surfaces than over the other of the opposing surfaces, the method comprising providing the silicon nitride over the one of the opposing surfaces to comprise a first portion, a second portion and a third portion, the first, second and third portions being elevationally displaced relative to one another, the second portion being between the first and third portions, the second portion having a greater stoichiometric amount of silicon than the first and third portions, the semiconductive wafer being subjected to less stress than if the silicon nitride over the one of the opposing surfaces had a constant stoichiometric amount of silicon throughout its thickness. In yet other aspects, the invention includes semiconductive wafer assemblies.
摘要翻译：在一个方面，本发明包括半导体晶片处理方法，包括在半导体晶片的表面上形成氮化硅层，所述氮化硅层包括至少两个部分，所述至少两个部分中的一个产生抵抗所述至少两个部分中的另一个，并且所述至少两个部分中的另一部分产生相对于所述至少两个部分中的一个部分的张力。在另一方面，本发明包括减少半导体晶片上的应力的方法，该半导体晶片具有一对相对的表面，并且在相对表面的一个之上具有比另一个相对表面更多的氮化硅，该方法包括提供所述相对表面中的一个上的氮化硅包括第一部分，第二部分和第三部分，所述第一部分，第二部分和第三部分相对于彼此正向移位，所述第二部分位于第一部分和第三部分之间，第二部分具有比第一和第三部分更大的化学计算量的硅，与相对表面上的一个相反的表面上的氮化硅在整个厚度上具有恒定的化学计量的硅时，半导体晶片受到的应力较小。在另一方面，本发明包括半导体晶片组件。

110. 发明授权

US06271153B1 Semiconductor processing method and trench isolation method 有权
公开(公告)号：US06271153B1
公开(公告)日：2001-08-07
申请号：US09603848
申请日：2000-06-26
申请人： John T. Moore
发明人： John T. Moore
IPC分类号： H01L21469
CPC分类号： H01L21/76224 , H01L21/3221
摘要： The invention includes semiconductor processing methods, including trench isolation. In one implementation, an oxide layer is deposited over a substrate. The deposited oxide layer is exposed to a chlorine containing gas effective to getter metals outwardly therefrom. In one implementation, a dielectric layer, for example silicon dioxide, is plasma enhanced chemical vapor deposited over a substrate within a chamber comprising an internal metal surface under conditions effective to incorporate metal from the chamber surface within the dielectric layer. The dielectric layer is then exposed to a chlorine containing gas effective to getter at least some of said metal outwardly therefrom. In one implementation, a trench isolation method comprises forming a series of isolation trenches into a semiconductive substrate. Silicon dioxide is chemical vapor deposited to within the trenches, with the silicon dioxide comprising metal impurity therein. The silicon dioxide within the trenches is densified using an atmosphere comprising chlorine which is effective to remove metal impurity from the silicon dioxide. In one implementation, some dielectric isolation material is chemical vapor deposited to within the trenches. After the chemical vapor deposition, the substrate is exposed to oxidation conditions effective to oxidize the trench sidewalls, with most preferably there having been no dedicated trench sidewall oxidation step conducted prior to the chemical vapor depositing.

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