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101. 发明申请

US20110250230A1 CELL CAPABLE OF EXPRESSING EXOGENOUS GITR LIGAND 有权
标题翻译：能表达外源GITR配体的电池
公开(公告)号：US20110250230A1
公开(公告)日：2011-10-13
申请号：US13062999
申请日：2009-09-11
申请人： Hiroshi Shiku , Hiroaki Ikeda , Jun Mitsui , Yuki Takenaka , Junichi Mineno , Ikunoshin Kato
发明人： Hiroshi Shiku , Hiroaki Ikeda , Jun Mitsui , Yuki Takenaka , Junichi Mineno , Ikunoshin Kato
IPC分类号： A61K39/00 , C12N15/63 , A61P35/00 , C12N5/10
CPC分类号： A61K39/0005 , A61K35/12 , A61K38/00 , A61K38/191 , A61K39/0011 , A61K2039/5152 , A61K2039/5156 , C07K14/70575 , C07K2319/30 , C12N2799/022 , C12N2799/027
摘要： Disclosed are: a cell capable of expressing an exogenous GITRL or an exogenous GITRL derivative; a method for producing the cell; a therapeutic or prophylactic agent comprising the cell as an active ingredient; use of the cell in the manufacture of a therapeutic or prophylactic agent; a method comprising a step of administering the cell to a subject; a viral vector carrying a gene encoding a GITRL or a GITRL derivative; a therapeutic or prophylactic agent comprising the viral vector as an active ingredient; use of the viral vector in the manufacture of a therapeutic or prophylactic agent; and a method comprising a step of administering the viral vector to a subject.
摘要翻译：公开了能够表达外源GITRL或外源性GITRL衍生物的细胞; 电池的制造方法; 包含该细胞作为活性成分的治疗或预防剂; 在制造治疗或预防剂中使用细胞; 一种方法，包括将细胞施用于受试者的步骤; 携带编码GITRL或GITRL衍生物的基因的病毒载体; 包含病毒载体作为活性成分的治疗或预防剂; 病毒载体在制备治疗或预防药物中的应用; 以及包括将病毒载体施用于受试者的步骤的方法。

102. 发明申请

US20110239446A1 METHOD FOR MANUFACTURING NONAQUEOUS SECONDARY BATTERY ELECTRODE 有权
标题翻译：制造非水性二次电池电极的方法
公开(公告)号：US20110239446A1
公开(公告)日：2011-10-06
申请号：US13139319
申请日：2009-12-11
申请人： Ryuta Morishima , Hitoshi Sakai , Hiroaki Ikeda , Hiroyuki Akita , Hidehito Matsuo
发明人： Ryuta Morishima , Hitoshi Sakai , Hiroaki Ikeda , Hiroyuki Akita , Hidehito Matsuo
IPC分类号： H01M4/1393
CPC分类号： H01M10/0525 , H01M4/0404 , H01M4/131 , H01M4/133 , H01M4/1393 , H01M4/505 , H01M4/525 , H01M4/587 , H01M4/621 , H01M4/75 , Y02E60/122 , Y02P70/54 , Y02T10/7011 , Y10T29/49108 , Y10T29/49115
摘要： A method is provided for manufacturing an electrode that has a porous inorganic layer on the surface of an active material layer and is suitable for constructing a nonaqueous secondary battery with excellent input-output performance. In this manufacturing method, an electrode perform, which has an active material layer (344) consisting primarily of active material particles (42) and supported on a collector (342), is prepared. The water concentration of at least the surface (344a) of the active material layer (344) is adjusted to 100 ppm to 500 ppm. A slurry (S) containing inorganic particles (44), a binder and an organic solvent is coated on the surface (344a) of the active material layer with the water concentration thus adjusted, to form a porous inorganic layer.
摘要翻译：提供一种制造在活性物质层的表面具有多孔无机层的电极的方法，适用于构成输出输出性能优良的非水二次电池。在该制造方法中，准备具有主要由活性物质粒子（42）构成并负载在集电体（342）上的活性物质层（344）的电极。将至少活性物质层（344）的表面（344a）的水浓度调整为100ppm〜500ppm。将含有无机颗粒（44），粘合剂和有机溶剂的浆料（S）以如此调节的水浓度涂覆在活性物质层的表面（344a）上，形成多孔无机层。

103. 发明申请

US20110234645A1 IMAGE DISPLAY APPARATUS, PICTURE SIGNAL PROCESSING METHOD, AND PROGRAM 有权
标题翻译：图像显示设备，图像信号处理方法和程序
公开(公告)号：US20110234645A1
公开(公告)日：2011-09-29
申请号：US12998769
申请日：2008-12-26
申请人： Shigenobu Jyou , Hiroaki Ikeda , Reiichi Kobayashi
发明人： Shigenobu Jyou , Hiroaki Ikeda , Reiichi Kobayashi
IPC分类号： G09G5/10
CPC分类号： G09G3/002 , G09G3/3611 , G09G2320/0238 , G09G2360/147
摘要： An image display apparatus includes: a panel (16a) that includes a plurality of picture elements that change transmittance of light according to picture levels; a detection unit (12) that detects, in one-image portions of the panel (16a), picture levels for each of the plurality of picture elements from picture signals that indicate the picture levels of each picture element; and a processor (18) that, based on the picture levels of one-image portions that were detected by the detection unit (12), adjusts the transmittance of light of the plurality of picture elements such that the image realized by the picture signal is brighter when a value that corresponds to brightness is greater than a predetermined threshold value.
摘要翻译：图像显示装置包括：面板（16a），其包括根据图像水平改变光的透射率的多个图像元素; 检测单元（12），其从所述面板（16a）的单图像部分中检测用于指示每个图像元素的图像水平的图像信号中的每个所述多个图像元素的图像水平; 以及处理器（18），其基于由所述检测单元（12）检测到的一个图像部分的图像电平来调整所述多个图像元素的光的透射率，使得由所述图像信号实现的图像是当对应于亮度的值大于预定阈值时更亮。

104. 发明申请

US20110201154A1 SEMICONDUCTOR DEVICE INCLUDING STACKED SEMICONDUCTOR CHIPS 有权
标题翻译：半导体器件包括堆叠半导体器件
公开(公告)号：US20110201154A1
公开(公告)日：2011-08-18
申请号：US13094214
申请日：2011-04-26
申请人： Kayoko SHIBATA , Hiroaki Ikeda
发明人： Kayoko SHIBATA , Hiroaki Ikeda
IPC分类号： H01L21/768
CPC分类号： G11C11/407 , H01L23/5226 , H01L23/535 , H01L23/544 , H01L25/0657 , H01L2223/5444 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2224/05599
摘要： A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.
摘要翻译：公开了一种包括多个半导体芯片和多个通线组的半导体器件。每个通线组由唯一数量的通线组成。与通过线组相关联的数字彼此互为互补。当对于每条直线组选择其中一根直线时，半导体芯片中的一个通过多条通线组中所选择的直通线的组合来指定。

105. 发明授权

US07952201B2 Semiconductor device including stacked semiconductor chips 有权
标题翻译：包括堆叠半导体芯片的半导体器件
公开(公告)号：US07952201B2
公开(公告)日：2011-05-31
申请号：US12759198
申请日：2010-04-13
申请人： Kayoko Shibata , Hiroaki Ikeda
发明人： Kayoko Shibata , Hiroaki Ikeda
IPC分类号： H01L23/538 , H01L21/768 , H01L25/065
CPC分类号： G11C11/407 , H01L23/5226 , H01L23/535 , H01L23/544 , H01L25/0657 , H01L2223/5444 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2224/05599
摘要： A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.
摘要翻译：公开了一种包括多个半导体芯片和多个通线组的半导体器件。每个通线组由唯一数量的通线组成。与通过线组相关联的数字彼此互为互补。当对于每条直线组选择其中一根直线时，半导体芯片中的一个通过多条通线组中所选择的直通线的组合来指定。

106. 发明授权

US07893540B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07893540B2
公开(公告)日：2011-02-22
申请号：US12537723
申请日：2009-08-07
申请人： Masakazu Ishino , Hiroaki Ikeda , Kayoko Shibata
发明人： Masakazu Ishino , Hiroaki Ikeda , Kayoko Shibata
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/6835 , G11C5/02 , G11C5/025 , H01L23/481 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/81005 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06586 , H01L2225/06596 , H01L2924/00014 , H01L2924/15311 , H01L2924/1532 , H01L2924/15787 , H01L2924/181 , H01L2924/30105 , H01L2224/81 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.
摘要翻译：半导体存储器件具有多个芯片和接口芯片，其规格可以容易地改变，同时抑制其可靠性的劣化。该器件具有插入器芯片。连接到芯片的第一内部电极形成在插入器芯片的第一表面上。连接到接口芯片的第二内部电极和连接到外部电极的第三内部电极形成在插入器芯片的第二表面上。只要需要，接口芯片可以安装在插入器芯片的第二表面上。因此，只要客户要求的适当的接口芯片安装在插入器芯片上，存储器件就可以具有对客户所期望的任何规格。因此，核心芯片不需要以裸芯片的形式大量存放。

107. 发明授权

US07841210B2 Method of manufacturing glass substrate and information recording medium 有权
标题翻译：制造玻璃基板和信息记录介质的方法
公开(公告)号：US07841210B2
公开(公告)日：2010-11-30
申请号：US11868381
申请日：2007-10-05
申请人： Hiroaki Ikeda , Masaru Suzuki , Kazuna Sasaki , Yumi Mukai , Jun Ozawa
发明人： Hiroaki Ikeda , Masaru Suzuki , Kazuna Sasaki , Yumi Mukai , Jun Ozawa
IPC分类号： C03C21/00
CPC分类号： C03C21/002 , B01D46/543 , C03C17/23 , C03C17/38 , C03C19/00 , C03C21/001 , C03C2218/154 , C03C2218/31 , C03C2218/365 , G11B7/2531 , G11B7/26
摘要： In a method of manufacturing a glass substrate for an information recording medium including a step for chemically strengthening the glass substrate by contacting the glass substrate with chemical strengthening processing liquid containing chemical strengthening salt, concentration of Fe and Cr is 500 ppb or less in said chemical strengthening salt, respectively. The concentration may be detected by the use of an ICP (Inductively Coupled Plasma) emission spectrometry analyzing method or a fluorescent X-ray spectroscopy analyzing method.
摘要翻译：在制造用于信息记录介质的玻璃基板的方法中，包括通过使玻璃基板与含有化学强化盐的化学强化处理液接触来化学强化玻璃基板的步骤，在所述化学品中Fe和Cr的浓度为500ppb以下分别加强盐。可以通过使用ICP（电感耦合等离子体）发射光谱分析法或荧光X射线光谱分析法来检测浓度。

108. 发明授权

US07773925B2 Image forming apparatus 有权
标题翻译：图像形成装置
公开(公告)号：US07773925B2
公开(公告)日：2010-08-10
申请号：US12042719
申请日：2008-03-05
申请人： Hiroaki Ikeda
发明人： Hiroaki Ikeda
IPC分类号： G03G15/00 , G03G15/01 , G03G15/16
CPC分类号： G03G15/0131 , G03G15/5058 , G03G2215/00059 , G03G2215/0141 , G03G2215/0161
摘要： A misregistration correcting unit correcting image misregistration on an endless belt in an electrophotographic image forming apparatus is disclosed that includes an image creation part that creates on the endless belt misregistration correction pattern sets each including a pattern of mark groups each being one of a horizontal line mark group formed of horizontal line segment marks and an oblique line mark group formed of oblique line segment marks; a position detecting part that detects the mark positions; a position detection counting part that counts the number of the detected positions of each mark group and detects an abnormal mark group whose number of the detected positions is other than a prescribed number; a detection result storing part that stores information on the detected mark positions; and a misregistration calculating part that calculates the amount of misregistration based on the stored position information excluding that of the abnormal mark group.
摘要翻译：公开了一种校正电子照相图像形成装置中的环形带上的图像重合失调的对准校正单元，其包括在环形带对准校正图案组中产生的图像创建部件，每个包括标记组的图案，每个标记组是水平线标记由水平线段标记组成的组和由斜线段标记形成的斜线标记组; 检测标记位置的位置检测部; 位置检测计数部，其对每个标记组的检测位置的数量进行计数，并检测检测到的位置数不同于规定数量的异常标记组; 检测结果存储部，其存储关于检测到的标记位置的信息; 以及基于除了异常标记组的位置信息之外的存储位置信息来计算重合失调量的重合排列计算部。

109. 发明授权

US07763496B2 Stacked semiconductor memory device and control method thereof 有权
标题翻译：叠层半导体存储器件及其控制方法
公开(公告)号：US07763496B2
公开(公告)日：2010-07-27
申请号：US11708579
申请日：2007-02-21
申请人： Hiroaki Ikeda , Kayoko Shibata
发明人： Hiroaki Ikeda , Kayoko Shibata
IPC分类号： H01L21/44
CPC分类号： H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06586 , H01L2924/15311
摘要： A stacked semiconductor memory device includes an interface chip and a plurality of core chips, in which the interface chip and the plurality of core chips are stacked. The core chips are mutually connected by a plurality of data through electrodes. The core chips each include a plurality of memory arrays. In response to an access request, the plurality of memory arrays corresponding to a predetermined data through electrode are activated, and the plurality of activated memory arrays and the predetermined data through electrode are sequentially connected. Thereby, even though it requires approximately ten-odd ns for transferring the first data, similarly to the conventional case, it is possible to transfer the subsequent data at high speed determined by the reaction rate (1 to 2 ns) of the through electrode. As a result, it becomes possible to increase a bandwidth while suppressing the number of through electrodes.
摘要翻译：堆叠式半导体存储器件包括接口芯片和多个芯片，其中接口芯片和多个芯片芯片堆叠在其中。核心芯片通过电极通过多个数据相互连接。核心芯片各自包括多个存储器阵列。响应于访问请求，对应于预定数据通过电极的多个存储器阵列被激活，并且多个激活的存储器阵列和预定的数据通过电极被顺序地连接。因此，即使对于传送第一数据需要大约十几ns，与常规情况类似，可以以通过电极的反应速率（1至2ns）确定的高速传送随后的数据。结果，可以在抑制贯通电极的数量的同时增加带宽。

110. 发明申请

US20090315147A1 SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体芯片和半导体器件
公开(公告)号：US20090315147A1
公开(公告)日：2009-12-24
申请号：US12548095
申请日：2009-08-26
申请人： Hideaki Saito , Yasuhiko Hagihara , Hiroaki Ikeda
发明人： Hideaki Saito , Yasuhiko Hagihara , Hiroaki Ikeda
IPC分类号： H01L29/93
CPC分类号： H01L29/945 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A wire embedded in a semiconductor substrate is covered with an insulating film, and a bias voltage is applied to the semiconductor substrate or to the wire to form a depletion layer extending from an edge of the insulating film. Alternatively, a semiconductor layer having a different conductivity type from the semiconductor substrate is formed within the semiconductor substrate to surround the insulating film.
摘要翻译：嵌入在半导体衬底中的导线被绝缘膜覆盖，并且偏置电压被施加到半导体衬底或线，以形成从绝缘膜的边缘延伸的耗尽层。或者，在半导体衬底内形成具有与半导体衬底不同的导电类型的半导体层以包围绝缘膜。

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