会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 104. 发明授权
    • Barrier and interrupt mechanism for high latency and out of order DMA device
    • 阻塞和中断机制,用于高延迟和无序的DMA设备
    • US07603490B2
    • 2009-10-13
    • US11621776
    • 2007-01-10
    • Giora BiranLuis E. De la TorreBernard C. DrerupJyoti GuptaRichard Nicholas
    • Giora BiranLuis E. De la TorreBernard C. DrerupJyoti GuptaRichard Nicholas
    • G06F13/28G06F13/32
    • G06F13/28
    • A direct memory access (DMA) device includes a barrier and interrupt mechanism that allows interrupt and mailbox operations to occur in such a way that ensures correct operation, but still allows for high performance out-of-order data moves to occur whenever possible. Certain descriptors are defined to be “barrier descriptors.” When the DMA device encounters a barrier descriptor, it ensures that all of the previous descriptors complete before the barrier descriptor completes. The DMA device further ensures that any interrupt generated by a barrier descriptor will not assert until the data move associated with the barrier descriptor completes. The DMA controller only permits interrupts to be generated by barrier descriptors. The barrier descriptor concept also allows software to embed mailbox completion messages into the scatter/gather linked list of descriptors.
    • 直接存储器访问(DMA)设备包括屏障和中断机制,允许中断和邮箱操作以确保正确操作的方式发生,但仍然允许在可能的情况下发生高性能无序数据移动。 某些描述符被定义为“屏障描述符”。 当DMA设备遇到屏障描述符时,它确保所有先前的描述符在屏障描述符完成之前完成。 DMA设备进一步确保在与屏障描述符关联的数据移动完成之前,屏障描述符产生的任何中断都不会断言。 DMA控制器仅允许由屏障描述符生成中断。 屏障描述符概念还允许软件将邮箱完成消息嵌入到描述符的分散/收集链接列表中。