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101. 发明授权

US6130162A Method of preparing passivated copper line and device manufactured thereby 有权
标题翻译：钝化铜线的制作方法及其制造装置
公开(公告)号：US6130162A
公开(公告)日：2000-10-10
申请号：US224983
申请日：1999-01-04
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L21/768 , H01L23/532 , H01L21/44 , H01L21/443
CPC分类号： H01L23/53238 , H01L21/76841 , H01L21/76849 , H01L21/76852 , H01L21/76885 , H01L2924/0002 , Y10S257/915
摘要： A method of forming a copper conductor for a thin film electronic device comprises: forming layers over a conductor into a stack of barrier layer superjacent on top of the substrate, a copper layer on top of the barrier layer, and a hard mask layer on top of the copper layer. The forming a mask on top of the hard mask layer and pattern the stack by etching through the layers down to the substrate on the sides of the mask forming the copper layer into a copper conductor line and leaving sidewalls of the copper conductor line exposed. Grow a copper germanide (Cu.sub.3 Ge) compound passivation layer is selectively grown only on the sidewalls of the copper conductor line.
摘要翻译：一种形成用于薄膜电子器件的铜导体的方法包括：在导体上形成层叠在衬底顶部以上的阻挡层堆叠，在阻挡层顶部的铜层和顶部的硬掩模层的铜层。在硬掩模层的顶部上形成掩模，并通过将层压蚀成形成铜层的掩模的侧面上的衬底到铜导体线中并且使铜导体线的侧壁露出而形成叠层。生长铜锗化合物（Cu3Ge）化合物钝化层仅选择性地生长在铜导线的侧壁上。

102. 发明授权

US06099701A AlCu electromigration (EM) resistance 有权
标题翻译： AlCu电迁移（EM）电阻
公开(公告)号：US06099701A
公开(公告)日：2000-08-08
申请号：US342034
申请日：1999-06-28
申请人： Chung-Shi Liu , Shau-Lin Shue , Chen-Hua Yu
发明人： Chung-Shi Liu , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L21/768 , H01L23/532 , C23C14/34 , H01L21/4763
CPC分类号： H01L21/7685 , H01L21/76841 , H01L23/53223 , H01L2924/0002
摘要： A method of manufacturing a Al-Cu line stack comprised of Ti-rich TIN, TiN, Ti-rich TiN, Al-Cu, Ti-rich TiN, TiN layers. A key feature of the invention is the sputtering of the Ti-rich TiN layers and TiN layers in the same Ti sputter chamber by turning off and on the N.sub.2 gas flow. For example, the Ti-rich TiN layer is formed by sputtering Ti with the N.sub.2 gas initially turned off. The overlying TiN layer is sputtered with the N.sub.2 gas turned on and the process stabilizes. The Ti-rich TiN layer is sputtered during a N.sub.2 off step (no N.sub.2 gas flow). The invention's Ti-rich TiN, TiN, Ti-rich TiN, Al-Cu, Ti-rich TiN, TiN layers increase the electromigration resistance.
摘要翻译：一种由富Ti的TIN，TiN，富Ti的TiN，Al-Cu，富Ti的TiN，TiN层构成的Al-Cu线叠层的制造方法。本发明的一个关键特征是通过关闭和在N2气流上溅射相同Ti溅射室中的富钛TiN层和TiN层。例如，通过溅射Ti，最初关闭N 2气体来形成富Ti的TiN层。上覆的TiN层被溅射，N2气开启，工艺稳定。在N 2脱氮步骤（无N2气流）下溅镀Ti富Ti Ti层。本发明的富钛TiN，TiN，富钛TiN，Al-Cu，Ti富TiN，TiN层增加了电迁移率。

103. 发明授权

US06046108A Method for selective growth of Cu.sub.3 Ge or Cu.sub.5 Si for passivation of damascene copper structures and device manufactured thereby 有权
标题翻译：选择性生长Cu3Ge或Cu5Si用于钝化镶嵌铜结构的方法及其制造的器件
公开(公告)号：US06046108A
公开(公告)日：2000-04-04
申请号：US344402
申请日：1999-06-25
申请人： Chung-Shi Liu , Chen-Hua Yu , Tien-I Bao , Syun-Ming Jang
发明人： Chung-Shi Liu , Chen-Hua Yu , Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76867 , H01L21/7684 , H01L21/76849
摘要： Form a dielectric layer on a surface of a conductive substrate with a trench through the top surface down to the substrate. Form a barrier layer over the dielectric layer including the exposed surface of the conductive substrate and the exposed sidewalls of the dielectric layer. Form a copper conductor over the barrier layer and overfilling the narrow hole in the trench. Etch away material from the surface of the copper conductor by a CMP process lowering the copper leaving a thin layer of copper over the barrier layer above the dielectric layer aside from the hole. Form a copper passivation by combining an element selected from silicon and germanium with copper on the exposed surfaces of the copper surfaces forming an interface in the narrower hole between the copper and the copper compound located below the dielectric top level. Etch away material from the surface of the copper compound and the barrier layer to planiarize the copper compound by etching down to the dielectric top level leaving a thin layer of the copper passivation compound covering the copper conductor in the narrower hole.
摘要翻译：在具有沟槽的导电基底的表面上形成电介质层，通过顶表面向下延伸到衬底。在包括导电基底的暴露表面和电介质层暴露的侧壁的电介质层上形成阻挡层。在阻挡层上形成一个铜导体，并且填充沟槽中的窄孔。通过CMP工艺从铜表面蚀刻掉材料，在除了孔之外的电介质层之上的阻挡层上方，降低铜，从而留下薄的铜层。通过将选自硅和锗的元素与铜的暴露表面上的铜组合形成铜钝化，在铜和化合物之间的较窄的孔中形成界面，位于电介质顶层之下。从铜化合物的表面和阻挡层的表面蚀刻掉材料，以通过蚀刻到电介质顶层来平面化铜化合物，留下在较窄的孔中覆盖铜导体的铜钝化化合物的薄层。

104. 发明授权

US09021682B2 Apparatus for stud bump formation 有权
标题翻译：用于柱形凸块形成的装置
公开(公告)号：US09021682B2
公开(公告)日：2015-05-05
申请号：US13527459
申请日：2012-06-19
申请人： Chien Ling Hwang , Yeong-Jyh Lin , Yi-Li Hsiao , Ming-Da Cheng , Tsai-Tsung Tsai , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
发明人： Chien Ling Hwang , Yeong-Jyh Lin , Yi-Li Hsiao , Ming-Da Cheng , Tsai-Tsung Tsai , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
IPC分类号： H01R43/052 , H01L21/48 , H01L23/00
CPC分类号： H01L24/11 , H01L21/4853 , H01L24/13 , H01L24/78 , H01L2224/056 , H01L2224/1111 , H01L2224/1134 , H01L2224/13005 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13164 , H01L2224/13169 , H01L2224/451 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48 , H01L2224/7855 , H01L2224/78621 , H01L2224/85051 , H01L2224/854 , H01L2924/00011 , H01L2924/00012 , H01L2924/00014 , H01L2924/206 , Y10T29/49192 , Y10T29/49213 , Y10T29/514 , Y10T29/5177 , Y10T29/53217 , Y10T29/53235 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/01049 , H01L2224/4554
摘要： An apparatus includes a spool configured to supply a wire, a cutting device configured to form a notch in the wire, and a capillary configured to bond the wire and to form a stud bump. The apparatus is further configured to pull the wire to break at the notch, with a tail region attached to the stud bump.
摘要翻译：一种装置包括：线圈，其被配置为供应线，被配置为在所述线中形成切口的切割装置，以及被配置为结合所述线并形成柱形凸块的毛细管。该设备还被配置为拉动线在凹口处断裂，尾部区域附接到柱形凸块。

105. 发明授权

US08735273B2 Forming wafer-level chip scale package structures with reduced number of seed layers 有权
标题翻译：形成具有减少种子层数的晶片级芯片级封装结构
公开(公告)号：US08735273B2
公开(公告)日：2014-05-27
申请号：US13179299
申请日：2011-07-08
申请人： Wen-Hsiung Lu , Ming-Da Cheng , Chih-Wei Lin , Yi-Wen Wu , Hsiu-Jen Lin , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
发明人： Wen-Hsiung Lu , Ming-Da Cheng , Chih-Wei Lin , Yi-Wen Wu , Hsiu-Jen Lin , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
IPC分类号： H01L21/44
CPC分类号： H01L24/03 , H01L21/566 , H01L21/76885 , H01L23/3114 , H01L23/3157 , H01L23/525 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02311 , H01L2224/02331 , H01L2224/0235 , H01L2224/02375 , H01L2224/0346 , H01L2224/0347 , H01L2224/03903 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05552 , H01L2224/05567 , H01L2224/05655 , H01L2224/05664 , H01L2224/11334 , H01L2224/11849 , H01L2224/1191 , H01L2224/13022 , H01L2224/13083 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2924/181 , H01L2924/00014 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/00012 , H01L2924/01047 , H01L2924/01029 , H01L2924/00
摘要： A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed.
摘要翻译：一种方法包括在覆盖半导体衬底的金属焊盘上形成钝化层。在钝化层中形成第一开口，金属垫的一部分通过第一开口暴露。种子层形成在钝化层之上并且电耦合到金属焊盘。种子层还包括钝化层上的部分。在种子层上形成第一掩模，其中第一掩模具有直接在金属焊盘的至少一部分上的第二开口。在种子层和第二开口中形成PPI。在第一掩模上形成第二掩模，第二掩模形成在第二掩模中。金属凸块的一部分形成在第三开口中。在形成金属凸块的部分的步骤之后，去除第一和第二掩模。

106. 发明授权

US08617946B2 Integrated circuits including metal gates and fabrication methods thereof 有权
标题翻译：集成电路，包括金属栅极及其制造方法
公开(公告)号：US08617946B2
公开(公告)日：2013-12-31
申请号：US12846474
申请日：2010-07-29
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L21/8238
CPC分类号： H01L27/092 , H01L21/265 , H01L21/28088 , H01L21/8238 , H01L21/823835 , H01L21/823842 , H01L29/4966 , H01L29/665 , H01L29/66545 , H01L29/66575
摘要： A method of forming an integrated circuit is provided. The method includes forming a gate electrode of an NMOS transistor over a substrate by a gate-first process. A gate electrode of a PMOS transistor is formed over the substrate by a gate-last process.
摘要翻译：提供一种形成集成电路的方法。该方法包括通过栅极首先工艺在衬底上形成NMOS晶体管的栅电极。 PMOS晶体管的栅极通过栅极最后工艺形成在衬底的上方。

107. 发明申请

US20130277838A1 Methods and Apparatus for Solder Connections 有权
标题翻译：焊接连接方法与装置
公开(公告)号：US20130277838A1
公开(公告)日：2013-10-24
申请号：US13452507
申请日：2012-04-20
申请人： Chen-Hua Yu , Hao-Yi Tsai , Chien-Hsiun Lee , Chung-Shi Liu , Hsien-Wei Chen
发明人： Chen-Hua Yu , Hao-Yi Tsai , Chien-Hsiun Lee , Chung-Shi Liu , Hsien-Wei Chen
IPC分类号： H01L21/60 , H01L23/498
CPC分类号： H01L24/11 , H01L24/02 , H01L24/05 , H01L24/13 , H01L24/14 , H01L2224/02125 , H01L2224/02165 , H01L2224/02335 , H01L2224/0239 , H01L2224/024 , H01L2224/03464 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05024 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05562 , H01L2224/05567 , H01L2224/05569 , H01L2224/05572 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/1132 , H01L2224/1134 , H01L2224/11849 , H01L2224/13022 , H01L2224/13026 , H01L2224/13076 , H01L2224/13078 , H01L2224/13082 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/14051 , H01L2224/14131 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01079 , H01L2924/01322 , H01L2924/06 , H01L2924/351 , H01L2924/3512 , H01L2224/05552 , H01L2924/00
摘要： Methods and apparatus for solder connections. An apparatus includes a substrate having a conductive terminal on a surface; a passivation layer overlying the surface of the substrate and the conductive terminal; an opening in the passivation layer exposing a portion of the conductive terminal; at least one stud bump bonded to the conductive terminal in the opening and extending in a direction normal to the surface of the substrate; and a solder connection formed on the conductive terminal in the opening and enclosing the at least one stud bump. Methods for forming the solder connections are disclosed.
摘要翻译：焊接方法和装置。一种装置包括：在表面上具有导电端子的基板; 覆盖在衬底表面上的钝化层和导电端子; 所述钝化层中的开口暴露所述导电端子的一部分; 至少一个凸起凸块，其结合到所述开口中的所述导电端子并且沿垂直于所述基板的表面的方向延伸; 以及形成在所述开口中的所述导电端子上并且包围所述至少一个螺柱凸块的焊接连接。公开了形成焊料连接的方法。

108. 发明授权

US08540136B1 Methods for stud bump formation and apparatus for performing the same 有权
标题翻译：螺栓凸块形成方法及其执行方法
公开(公告)号：US08540136B1
公开(公告)日：2013-09-24
申请号：US13605403
申请日：2012-09-06
申请人： Yeong-Jyh Lin , Hsin-Hung Liao , Chien Ling Hwang , Yi-Li Hsiao , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
发明人： Yeong-Jyh Lin , Hsin-Hung Liao , Chien Ling Hwang , Yi-Li Hsiao , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
IPC分类号： B23K31/02 , B23K37/00
CPC分类号： B23K31/02 , B21D53/36 , B23K20/007 , H01L2224/78301 , Y10T29/49
摘要： Methods for forming stud bumps and apparatuses for forming stud bumps are disclosed. According to an embodiment, a method includes clamping a wire with a clamp. The clamp includes at least two opposing plates, and at least one of the opposing plates includes a protruding feature that intersects the wire when the wire is clamped forming a first notch in the wire. The method further includes bonding the wire to a bonding surface, releasing the wire from the clamp, passing the wire a notch pitch distance through the clamp, clamping the wire with the clamp forming a second notch in the wire, and breaking the wire leaving a bonded portion of the wire on the bonding surface. The second notch is the notch pitch distance from the first notch along the wire.
摘要翻译：公开了用于形成柱形凸块的方法和用于形成凸块凸块的装置。根据实施例，一种方法包括用夹具夹紧线。所述夹具包括至少两个相对的板，并且当所述线被夹紧形成所述线中的第一凹口时，所述相对板中的至少一个包括与所述线相交的突出特征。该方法还包括将线接合到接合表面，将线从夹具中释放出来，使线穿过钳口的间距距离通过夹具夹紧线，夹具在线中形成第二凹口，并将线断开，接合表面上的导线的接合部分。第二个凹口是距离第一个凹口沿导线的切口间距距离。

109. 发明授权

US08492891B2 Cu pillar bump with electrolytic metal sidewall protection 有权
标题翻译：铜柱凸起与电解金属侧壁保护
公开(公告)号：US08492891B2
公开(公告)日：2013-07-23
申请号：US12765250
申请日：2010-04-22
申请人： Wen-Hsiung Lu , Ming-Da Cheng , Chih-Wei Lin , Jacky Chang , Chung-Shi Liu , Chen-Hua Yu
发明人： Wen-Hsiung Lu , Ming-Da Cheng , Chih-Wei Lin , Jacky Chang , Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0346 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05572 , H01L2224/11452 , H01L2224/11462 , H01L2224/1147 , H01L2224/11823 , H01L2224/11825 , H01L2224/11906 , H01L2224/13022 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13099 , H01L2224/13147 , H01L2224/13455 , H01L2224/13565 , H01L2224/1357 , H01L2224/13639 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2924/0001 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01038 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552
摘要： A copper pillar bump has a sidewall protection layer formed of an electrolytic metal layer. The electrolytic metal layer is an electrolytic nickel layer, an electrolytic gold layer, and electrolytic copper layer, or an electrolytic silver layer.
摘要翻译：铜柱凸起具有由电解金属层形成的侧壁保护层。电解金属层是电解镍层，电解金层，电解铜层或电解银层。

110. 发明申请

US20130026644A1 Photoactive Compound Gradient Photoresist 有权
标题翻译：光敏复合梯度光刻胶
公开(公告)号：US20130026644A1
公开(公告)日：2013-01-31
申请号：US13192113
申请日：2011-07-27
申请人： Chen-Hua Yu , Chung-Shi Liu , Hung-Jui Kuo
发明人： Chen-Hua Yu , Chung-Shi Liu , Hung-Jui Kuo
IPC分类号： H01L23/528 , H01L21/28 , H01L23/31
CPC分类号： H01L23/5226 , G03F7/0045 , G03F7/095 , H01L21/311 , H01L21/76804 , H01L24/24 , H01L24/82 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/24146 , H01L2224/73259 , H01L2224/8203 , H01L2224/82101 , H01L2224/82106 , H01L2224/94 , H01L2225/06524 , H01L2924/10253 , H01L2924/1431 , H01L2924/1434 , H01L2224/82 , H01L2224/81
摘要： A system and method for forming photoresists over semiconductor substrates is provided. An embodiment comprises a photoresist with a concentration gradient. The concentration gradient may be formed by using a series of dry film photoresists, wherein each separate dry film photoresist has a different concentration. The separate dry film photoresists may be formed separately and then placed onto the semiconductor substrate before being patterned. Once patterned, openings through the photoresist may have a tapered sidewall, allowing for a better coverage of the seed layer and a more uniform process to form conductive materials through the photoresist.
摘要翻译：提供了一种用于在半导体衬底上形成光致抗蚀剂的系统和方法。一个实施方案包括具有浓度梯度的光致抗蚀剂。浓度梯度可以通过使用一系列干膜光致抗蚀剂形成，其中每个单独的干膜光致抗蚀剂具有不同的浓度。单独的干膜光致抗蚀剂可以单独形成，然后在图案化之前放置在半导体衬底上。一旦被图案化，通过光致抗蚀剂的开口可以具有锥形侧壁，允许更好地覆盖种子层，以及更均匀的工艺以通过光致抗蚀剂形成导电材料。

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