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101. 发明申请

US20070298572A1 FIELD EFFECT TRANSISTORS (FETs) WITH MULTIPLE AND/OR STAIRCASE SILICIDE 有权
标题翻译：具有多个和/或多个硅化物的场效应晶体管（FET）
公开(公告)号：US20070298572A1
公开(公告)日：2007-12-27
申请号：US11850076
申请日：2007-09-05
申请人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
发明人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6659
摘要： A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region. Then, (i) a first shallow contact region is formed in direct physical contact with the first S/D extension region, and (ii) a first deep contact region is formed in direct physical contact with the first S/D region and the first shallow contact region.
摘要翻译：一种半导体结构及其形成方法。首先，提供半导体结构，其包括（a）包括（i）沟道区和（ii）第一和第二源/漏（S / D）延伸区的半导体层，以及（iii）第一和第二S / D 区域，（b）通过限定基本上垂直于第一接口表面的参考方向的第一接口表面方向与沟道区域物理接触的栅极电介质区域，以及（c）与栅极电介质直接物理接触的栅极区域区域，其中栅极电介质区域夹在栅极区域和沟道区域之间并使电绝缘。然后，（i）第一浅接触区域形成为与第一S / D延伸区域直接物理接触，并且（ii）第一深接触区域形成为与第一S / D区域和第一浅/ 浅接触区域。

102. 发明申请

US20070298552A1 HIGH PERFORMANCE 3D FET STRUCTURES, AND METHODS FOR FORMING THE SAME USING PREFERENTIAL CRYSTALLOGRAPHIC ETCHING 有权
标题翻译：高性能3D FET结构及其使用优选结晶蚀刻形成其的方法
公开(公告)号：US20070298552A1
公开(公告)日：2007-12-27
申请号：US11851464
申请日：2007-09-07
申请人： Thomas Dyer , Haining Yang
发明人： Thomas Dyer , Haining Yang
IPC分类号： H01L21/84
CPC分类号： H01L21/823807 , H01L21/823821 , H01L27/0922 , H01L27/1211 , H01L29/04 , H01L29/66795 , H01L29/7853
摘要： The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.
摘要翻译：本发明涉及高性能三维（3D）场效应晶体管（FET）。具体而言，可以使用具有沿着第一组等效晶面中的一个取向的底表面和沿着第二不同组的等效晶面取向的多个附加表面的3D半导体结构，以形成具有载体通道定向的高性能3D FET 沿着第二个不同组的等效晶面。更重要的是，这种3D半导体结构可以容易地在具有底表面和多个附加表面的附加3D半导体结构的同一衬底上形成，所述另外的三维半导体结构全部沿着第一组等效晶面取向。附加的3D半导体结构可以用于形成附加的3D FET，其与上述3D FET互补，并且具有沿着第一组等效晶面取向的载流子通道。

103. 发明申请

US20070148836A1 Reduced-resistance finFETs and methods of manufacturing the same 有权
标题翻译：降低电阻finFET及其制造方法
公开(公告)号：US20070148836A1
公开(公告)日：2007-06-28
申请号：US11316244
申请日：2005-12-22
申请人： Kangguo Cheng , Louis Hsu , Jack Mandelman , Haining Yang
发明人： Kangguo Cheng , Louis Hsu , Jack Mandelman , Haining Yang
IPC分类号： H01L21/84 , H01L21/336
CPC分类号： H01L29/785 , H01L21/823418 , H01L21/823437 , H01L29/41791 , H01L29/665 , H01L29/6653 , H01L29/66795 , H01L29/78618 , H01L2029/7858 , Y10S438/96
摘要： In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了制造finFET的第一种方法。第一种方法包括以下步骤：（1）提供衬底; 和（2）在所述衬底上形成所述finFET的至少一个源极/漏极扩散区域。每个源极/漏极扩散区域包括（a）非硅化硅的内部区域; 和（b）硅化物形成在非硅化硅区域的顶表面和侧壁上。提供了许多其他方面。

104. 发明申请

US20070134870A1 Method to enhance device performance with selective stress relief 有权
标题翻译：通过选择性应力消除来增强设备性能的方法
公开(公告)号：US20070134870A1
公开(公告)日：2007-06-14
申请号：US11299542
申请日：2005-12-12
申请人： Yong Lee , Haining Yang , Victor Chan
发明人： Yong Lee , Haining Yang , Victor Chan
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.
摘要翻译：在衬底的一个区域中的应力层下方具有应力消除层的半导体器件的制造结构和方法。在第一示例中，应力消除层形成在衬底的第一区域（例如，PFET区域）上，而不是在第二区域（例如，NFET区域）之上。应力层在第一区域中的应力消除层上方和第二区域中的器件和衬底/硅化物之上。 NFET晶体管的性能由于NFET沟道中的整体拉伸应力而增强，而由于包含应力消除层而降低/消除了PFET晶体管性能的降低。在第二示例性实施例中，应力消除层形成在第二区域上，但不是第一区域并且应力层的应力被反转。

105. 发明申请

US20070093030A1 Reduction of boron diffusivity in pfets 失效
标题翻译：降低pfets中的硼扩散率
公开(公告)号：US20070093030A1
公开(公告)日：2007-04-26
申请号：US10596249
申请日：2003-12-08
申请人： Frederick Buehrer , Dureseti Chidambarrao , Bruce Doris , Hsiang-Jen Huang , Haining Yang
发明人： Frederick Buehrer , Dureseti Chidambarrao , Bruce Doris , Hsiang-Jen Huang , Haining Yang
IPC分类号： H01L21/336 , H01L21/322 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/7842 , H01L21/22 , H01L21/26513 , H01L21/26586 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L29/1083 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify final boron concentrations. In the case of a field effect transistor, the gate structure may be formed with or without sidewalls to regulate the location of the boundary relative to source/drain, extension and/or halo implants. Different boron diffusion rates can be produced in the lateral and vertical directions and diffusion rates comparable to arsenic can be achieved. Reduction of junction capacitance of both nFETs and pFETs can be achieved simultaneously with the same process steps.
摘要翻译：应用于由半导体材料的结构或主体（例如衬底或层）限定的边界处的应力膜提供了靠近边界的半导体材料中的拉应力和压缩应力的变化，并用于在退火过程中修饰硼扩散速率，从而改变最终的硼浓度。在场效应晶体管的情况下，栅极结构可以形成有或不具有侧壁以调节边界相对于源极/漏极，延伸和/或晕轮植入物的位置。可以在横向和垂直方向上产生不同的硼扩散速率，并且可以实现与砷相当的扩散速率。可以通过相同的工艺步骤同时实现nFET和pFET的结电容的减小。

106. 发明申请

US20070080401A1 STRUCTURE AND METHOD FOR FORMING ASYMMETRICAL OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS 有权
标题翻译：在场效应晶体管中形成非对称叠加电容的结构与方法
公开(公告)号：US20070080401A1
公开(公告)日：2007-04-12
申请号：US11163165
申请日：2005-10-07
申请人： Haining Yang
发明人： Haining Yang
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/823425 , H01L21/26586 , H01L21/823468 , H01L29/6656 , H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： A method for forming asymmetric spacer structures for a semiconductor device includes forming a spacer layer over at least a pair of adjacently spaced gate structures disposed over a semiconductor substrate. The gate structures are spaced such that the spacer layer is formed at a first thickness in a region between the gate structures and at a second thickness elsewhere, the second thickness being greater than said first thickness. The spacer layer is etched so as to form asymmetric spacer structures for the pair of adjacently spaced gate structures.
摘要翻译：用于形成用于半导体器件的非对称间隔结构的方法包括在设置在半导体衬底上的至少一对相邻间隔开的栅极结构上形成间隔层。栅极结构间隔开，使得间隔层在栅极结构之间的区域中以第一厚度形成，并且在其它位置处形成第二厚度，第二厚度大于所述第一厚度。蚀刻间隔层以便形成用于一对相邻隔开的栅极结构的非对称间隔结构。

107. 发明申请

US20060286786A1 METHOD AND APPARATUS FOR INCREASE STRAIN EFFECT IN A TRANSISTOR CHANNEL 有权
标题翻译：在晶体管通道中增加应变效应的方法和装置
公开(公告)号：US20060286786A1
公开(公告)日：2006-12-21
申请号：US11467446
申请日：2006-08-25
申请人： Haining Yang , Huilong Zhu
发明人： Haining Yang , Huilong Zhu
IPC分类号： H01L29/768 , H01L21/336 , H01L21/3205
CPC分类号： H01L29/6653 , H01L29/66545 , H01L29/7842
摘要： A semiconductor device having a transistor channel with an enhanced stress is provided. To achieve the enhanced stress transistor channel, a nitride film is preferentially formed on the device substrate with little to no nitride on a portion of the gate stack. The nitride film may be preferentially deposited only on the silicon substrate in a non-conformal layer, where little to no nitride is deposited on the upper portions of the gate stack. The nitride film may also be uniformly deposited on the silicon substrate and gate stack in a conformal layer, with the nitride film proximate the upper regions of the gate stack preferentially removed in a later step. In some embodiments, nitride near the top of the gate stack is removed by removing the upper portion of the gate stack. In any of the methods, stress in the transistor channel is enhanced by minimizing nitride deposited on the gate stack, while having nitride deposited on the substrate.
摘要翻译：提供了具有增强应力的晶体管沟道的半导体器件。为了实现增强的应力晶体管沟道，在栅极堆叠的一部分上，在器件衬底上优先形成氮化物膜，几乎没有氮化物。氮化物膜可以优选仅在非保形层中沉积在硅衬底上，其中在栅堆叠的上部上沉积很少至无氮化物。氮化物膜也可以均匀地沉积在保形层上的硅衬底和栅极堆叠上，其中靠近栅极堆叠的上部区域的氮化物膜在稍后的步骤中优先被去除。在一些实施例中，通过去除栅极堆叠的上部来去除靠近栅极堆叠顶部的氮化物。在任何方法中，通过使沉积在栅极堆叠上的氮化物最小化，同时在衬底上沉积氮化物来增强晶体管沟道中的应力。

108. 发明申请

US20060244075A1 FIELD EFFECT TRANSISTORS (FETs) WITH MULTIPLE AND/OR STAIRCASE SILICIDE 失效
标题翻译：具有多个和/或多个硅化物的场效应晶体管（FET）
公开(公告)号：US20060244075A1
公开(公告)日：2006-11-02
申请号：US10908087
申请日：2005-04-27
申请人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
发明人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6659
摘要： A semiconductor structure and method for forming the same. The semiconductor structure comprises a field effect transistor (FET) having a channel region disposed between first and second source/drain (S/D) extension regions which are in turn in direct physical contact with first and second S/D regions, respective. First and second silicide regions are formed such that the first silicide region is in direct physical contact with the first S/D region and the first S/D extension region, whereas the second silicide region is in direct physical contact with the second S/D region and the second S/D extension region. The first silicide region is thinner for regions in contact with first S/D extension region than for regions in contact with the first S/D region. Similarly, the second silicide region is thinner for regions in contact with second S/D extension region than for regions in contact with the second S/D region.
摘要翻译：一种半导体结构及其形成方法。半导体结构包括场效应晶体管（FET），其具有设置在第一和第二源极/漏极（S / D）延伸区域之间的沟道区域，第一和第二源极/漏极（S / D）延伸区域又分别与第一和第二S / D区域直接物理接触。形成第一和第二硅化物区域，使得第一硅化物区域与第一S / D区域和第一S / D延伸区域直接物理接触，而第二硅化物区域与第二S / D区域直接物理接触区域和第二S / D扩展区域。对于与第一S / D延伸区域接触的区域，第一硅化物区域比与第一S / D区域接触的区域更薄。类似地，对于与第二S / D延伸区域接触的区域，第二硅化物区域比与第二S / D区域接触的区域更薄。

109. 发明申请

US20060228848A1 DUAL-HYBRID LINER FORMATION WITHOUT EXPOSING SILICIDE LAYER TO PHOTORESIST STRIPPING CHEMICALS 失效
标题翻译：双色混合衬里形成，不露出硅胶层到光电材料剥离化学品
公开(公告)号：US20060228848A1
公开(公告)日：2006-10-12
申请号：US10907415
申请日：2005-03-31
申请人： Victor Chan , Haining Yang , Yong Lee , Eng Lim
发明人： Victor Chan , Haining Yang , Yong Lee , Eng Lim
IPC分类号： H01L21/471
CPC分类号： H01L29/7843 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L29/665 , H01L29/66575 , H01L29/78
摘要： Methods of fabricating a semiconductor device including a dual-hybrid liner in which an underlying silicide layer is protected from photoresist stripping chemicals by using a hard mask as a pattern during etching, rather than using a photoresist. The hard mask prevents exposure of a silicide layer to photoresist stripping chemicals and provides very good lateral dimension control such that the two nitride liners are well aligned.
摘要翻译：制造包括双重混合衬垫的半导体器件的方法，其中通过在蚀刻期间使用硬掩模作为图案来保护底层硅化物层免受光致抗蚀剂剥离化学品，而不是使用光致抗蚀剂。硬掩模防止硅化物层暴露于光致抗蚀剂剥离化学品，并提供非常好的横向尺寸控制，使得两个氮化物衬垫良好对准。

110. 发明授权

US07101744B1 Method for forming self-aligned, dual silicon nitride liner for CMOS devices 失效
标题翻译：用于形成用于CMOS器件的自对准双氮化硅衬垫的方法
公开(公告)号：US07101744B1
公开(公告)日：2006-09-05
申请号：US10906670
申请日：2005-03-01
申请人： Thomas W. Dyer , Haining Yang
发明人： Thomas W. Dyer , Haining Yang
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823828 , H01L21/823864 , H01L29/7843
摘要： A method for forming a self-aligned, dual silicon nitride liner for CMOS devices includes forming a first type nitride layer over a first polarity type device and a second polarity type device, and forming a topographic layer over the first type nitride layer. Portions of the first type nitride layer and the topographic layer over the second polarity type device are patterned and removed. A second type nitride layer is formed over the second polarity type device, and over remaining portions of the topographic layer over the first polarity type device so as to define a vertical pillar of second type nitride material along a sidewall of the topographic layer, the second type nitride layer in contact with a sidewall of the first type nitride layer. The topographic layer is removed and the vertical pillar is removed.
摘要翻译：用于形成用于CMOS器件的自对准双氮化硅衬垫的方法包括在第一极性类型器件和第二极性器件上形成第一氮化物层，并在第一氮化物层上形成形貌层。第一类型氮化物层和第二极性类型器件上的形貌层的部分被图案化和去除。在第二极性类型器件上形成第二类型氮化物层，并且在第一极性类型器件上方形成地形层的剩余部分，以沿着地形层的侧壁限定第二类型氮化物材料的垂直柱，第二氮化物层与第一氮化物层的侧壁接触。去除地形层并移除垂直柱。

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