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91. 发明授权

US5655137A Method and apparatus for pre-processing inputs to parallel architecture computers 失效
标题翻译：用于对并行架构计算机的输入进行预处理的方法和装置
公开(公告)号：US5655137A
公开(公告)日：1997-08-05
申请号：US409256
申请日：1995-03-23
申请人： Aram K. Kevorkian
发明人： Aram K. Kevorkian
IPC分类号： G06F17/12 , G06F17/16 , G06F17/11
CPC分类号： G06F17/12 , G06F17/16
摘要： A pre-processing method and pre-processor decompose a first problem belong to a class of linear algebra problems comprising an input sparse symmetric matrix into a suite of sub-problems. The pre-processor generates a suite of signals representing the information content of a permutation of the rows and columns of the sparse symmetric matrix. These signals are used to define a block-bordered diagonal form leading to a sparse Schur-complement resolution wherein each sub-problem corresponds to a perfect parallelism in the first problem. The preprocessor allocates the sub-problems to sub-processors in a network of parallel architecture computers. The sub-processors solve the sub-problems concurrently and combine the results in a front-end computer, which outputs a solution to the first problem.
摘要翻译：预处理方法和预处理器将属于一类线性代数问题的第一问题分解成包括输入稀疏对称矩阵成一系列子问题。预处理器产生一组表示稀疏对称矩阵的行和列的排列的信息内容的信号。这些信号用于定义块边界对角线形式，导致稀疏Schur补码分辨率，其中每个子问题对应于第一个问题中的完美并行性。预处理器将子问题分配给并行架构计算机网络中的子处理器。子处理器同时解决子问题，并将结果结合在前端计算机中，从而为第一个问题输出解决方案。

92. 发明授权

US5446908A Method and apparatus for pre-processing inputs to parallel architecture computers 失效
标题翻译：用于对并行架构计算机的输入进行预处理的方法和装置
公开(公告)号：US5446908A
公开(公告)日：1995-08-29
申请号：US964594
申请日：1992-10-21
申请人： Aram K. Kevorkian
发明人： Aram K. Kevorkian
IPC分类号： G06F17/12 , G06F17/16 , G06F15/347 , G06F15/32
CPC分类号： G06F17/12 , G06F17/16
摘要： A pre-processing method and pre-processor decomposed a first problem belong to a class of linear algebra problems comprising an input sparse symmetric matrix into a suite of sub-problems. The pro-processor generates a suite of signals representing the information content of a permutation of the rows and columns of fire sparse symmetric matrix. These signals are used to define a block-bordered block-diagonal form leading to a Schur-complement resolution wherein each sub-problem corresponds to a perfect parallelism in the first problem. The preprocessor allocates the sub-problems to sub-processors in a network of parallel architecture computers. The sub-processors solve the sub-problems concurrently and combine the results in a front-end computer, which outputs a solution to the first problem.
摘要翻译：预处理方法和预处理器将属于一类线性代数问题的第一问题分解成包括输入稀疏对称矩阵成一系列子问题。处理器产生一组表示火稀疏对称矩阵的行和列排列的信息内容的信号。这些信号用于定义块边界对角线形式，导致Schur补码分辨率，其中每个子问题对应于第一个问题中的完美并行性。预处理器将子问题分配给并行架构计算机网络中的子处理器。子处理器同时解决子问题，并将结果结合在前端计算机中，从而为第一个问题输出解决方案。

93. 发明授权

US5442569A Method and apparatus for system characterization and analysis using finite element methods 失效
标题翻译：使用有限元方法进行系统表征和分析的方法和装置
公开(公告)号：US5442569A
公开(公告)日：1995-08-15
申请号：US82409
申请日：1993-06-23
申请人： Minetada Osano
发明人： Minetada Osano
IPC分类号： G06F17/16 , G06F17/12 , G06F17/13 , G06F17/50 , G06F15/20
CPC分类号： G06F17/12 , G06F17/5018
摘要： A method and apparatus for analyzing and producing systems based upon finite element modeling and partial differential equations is presented. The apparatus includes the capability for parallel processing and decomposition of a model into parts. The method permits a model to be assembled from parts stored in a memory or database. The model is produced by interconnecting into a package the partition subsystems through an interface. The system does not require processing of data relating to an entire model at a single time. It thus permits analyses to be performed with reduced processing times and memory capacity requirements.
摘要翻译：提出了一种基于有限元建模和偏微分方程分析和生产系统的方法和装置。该装置包括并行处理和将模型分解成部件的能力。该方法允许从存储在存储器或数据库中的部件组装模型。该模型是通过一个接口将分区子系统连接到一个包中生成的。该系统不需要一次处理与整个模型有关的数据。因此，允许以缩短的处理时间和存储容量要求执行分析。

94. 发明授权

US5138704A Data processing apparatus having a parallel arrangement of data communication and data computation 失效
标题翻译：具有数据通信和数据计算的并行布置的数据处理装置
公开(公告)号：US5138704A
公开(公告)日：1992-08-11
申请号：US608030
申请日：1990-10-31
申请人： Junichi Takahashi , Takashi Kimura
发明人： Junichi Takahashi , Takashi Kimura
IPC分类号： G06F15/80 , G06F17/12
CPC分类号： G06F15/8007
摘要： A control method for processing elements (PE) in a parallel processing system, such as an array processor, in which data processing is carried out with data transfer between the PEs, and wherein the data transfer between the PEs is performed simultaneously with the data operations in the PEs to improve the processing speed of the parallel processing system. Three buffer memories are respectively connected to a data input path from one data procesing apparatus, a data output path to another data processing apparatus, and data paths for transmitting data from or to the data operation unit in the data processing apparatus itself having these three buffer memories. Connections between these buffer memories and the data paths are switched, in such a manner that one of these buffer memories is connected to the external data input path from one data processing apparatus, while the other two buffer memories, are connected to the data output path to another data processing apparatus and the data paths from or to the data operation unit, respectively. When receiving data in the buffer memory connected to the data input path from one data processing apparatus, the buffer memory connected to the data output path transmits data to another data processing apparatus, and the buffer memory connected to the data paths from or to the data operation unit sends data to this unit and receives the operation results from this unit.
摘要翻译：一种用于在诸如阵列处理器的并行处理系统中处理元件（PE）的控制方法，其中通过PE之间的数据传输执行数据处理，并且其中PE之间的数据传送与数据操作同时执行在PE中提高并行处理系统的处理速度。三个缓冲存储器分别从一个数据处理装置的数据输入路径，到另一个数据处理装置的数据输出路径和用于从具有这三个缓冲器的数据处理装置本身中的数据操作单元发送数据的数据路径回忆这些缓冲存储器和数据路径之间的连接被切换，使得这些缓冲存储器中的一个从一个数据处理装置连接到外部数据输入路径，而另外两个缓冲存储器连接到数据输出路径分别向另一数据处理装置和从数据操作单元传送数据路径。当从连接到数据输入路径的缓冲存储器接收数据时，连接到数据输出路径的缓冲存储器将数据发送到另一个数据处理装置，并将连接到数据路径的缓冲存储器从数据发送到数据操作单元向本机发送数据并从本机接收操作结果。

95. 发明授权

US4787057A Finite element analysis method using multiprocessor for matrix manipulations with special handling of diagonal elements 失效
标题翻译：有限元分析方法使用多处理器进行特殊处理对角元素的矩阵操作
公开(公告)号：US4787057A
公开(公告)日：1988-11-22
申请号：US870566
申请日：1986-06-04
申请人： Steven W. Hammond
发明人： Steven W. Hammond
IPC分类号： G06F17/12 , G06F17/16 , G06F7/52
CPC分类号： G06F17/16 , G06F17/12
摘要： Loading and storing a matrix associated with equations defining a physical system into the memory of a multiprocessor is accomplished by scanning along one orthogonal axis of the matrix and loading non-zero elements into memory associated with a plurality of the processors to form a transpose vector, with diagonal elements of the matrix being stored in the memory of a selected one of the processors. Each stored matrix element is provided with an index which identifies the origin of the element along the other axis of the matrix.
摘要翻译：将与定义物理系统的等式相关联的矩阵加载和存储到多处理器的存储器中通过沿矩阵的一个正交轴扫描并将非零元素加载到与多个处理器相关联的存储器中以形成转置向量来实现，其中矩阵的对角元素存储在所选择的一个处理器的存储器中。每个存储的矩阵元素都具有一个索引，该索引标识沿矩阵的另一个轴的元素的原点。

96. 发明公开

US20230252276A1 CALIBRATION OF ELECTRICAL PARAMETERS IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK 审中-公开
公开(公告)号：US20230252276A1
公开(公告)日：2023-08-10
申请号：US17727650
申请日：2022-04-22
申请人： Silicon Storage Technology, Inc.
发明人： Hieu Van Tran
IPC分类号： G06N3/063 , G06F17/12 , H03M1/14
CPC分类号： G06N3/0635 , G06F17/12 , H03M1/142
摘要： Numerous examples are disclosed for performing calibration of various electrical parameters in a deep learning artificial neural network. In one example, a system comprises a digital-to-analog converter for receiving an input of k bits and generating a first analog output, a mapping scalar for converting the first analog output into a second analog output, and an analog-to-digital converter for generating an output of n bits from the second analog output, where n is a different value than k.

97. 发明授权

US11698945B2 All-to-all connected oscillator networks for solving combinatorial optimization problems 有权
公开(公告)号：US11698945B2
公开(公告)日：2023-07-11
申请号：US16832056
申请日：2020-03-27
申请人： Massachusetts Institute of Technology
发明人： Jeffrey Chou , Suraj Deepak Bramhavar , Siddhartha Ghosh , William Herzog
IPC分类号： G06F17/11 , G06F17/12 , G06F17/13
CPC分类号： G06F17/11 , G06F17/12 , G06F17/13
摘要： An analog computing system with coupled non-linear oscillators can solve complex combinatorial optimization problems using the weighted Ising model. The system is composed of a fully-connected LC oscillator network with low-cost electronic components and compatible with traditional integrated circuit technologies. Each LC oscillator, or node, in the network can be coupled to each other node in the array with a multiply and accumulate crossbar array or optical interconnects. When implemented with four nodes, the system performs with single-run ground state accuracies of 98% on randomized MAX-CUT problem sets with binary weights and 84% with five-bit weight resolutions. The four-node system can obtain solutions within five oscillator cycles with a time-to-solution that scales directly with oscillator frequency. A scaling analysis suggests that larger coupled oscillator networks may be used to solve computationally intensive problems faster and more efficiently than conventional algorithms.

98. 发明公开

US20230169142A1 OPTIMAL SOLUTION CALCULATION DEVICE FOR OPTIMIZATION PROBLEM AND OPTIMAL SOLUTION CALCULATION METHOD FOR OPTIMIZATION PROBLEM 审中-公开
公开(公告)号：US20230169142A1
公开(公告)日：2023-06-01
申请号：US17919432
申请日：2020-06-04
申请人： Mitsubishi Electric Corporation
发明人： Junya HATTORI , Masaya ENDO , Yuko OMAGARI
IPC分类号： G06F17/12
CPC分类号： G06F17/12
摘要： An optimal solution calculation device for an optimization problem includes an initial condition generation unit for generating an executable initial solution and an equality constraint set with respect to an optimization problem, an optimization calculation unit for calculating a solution of a simultaneous linear equation generated from an evaluation function and for calculating an evaluated solution that is a solution to minimize or maximize the evaluation function, and an update unit. A convergence determination unit of the optimization calculation unit determines that an iterative solution has converged when a residual norm is equal to or less than a convergence determination threshold value, and outputs the converged iterative solution as the evaluated solution. The update unit determines the evaluated solution as an optimal solution when an update of the equality constraint set is determined to be unnecessary, and the convergence determination threshold value is the first threshold value.

99. 发明授权

US11604419B2 Method of determining information about a patterning process, method of reducing error in measurement data, method of calibrating a metrology process, method of selecting metrology targets 有权
公开(公告)号：US11604419B2
公开(公告)日：2023-03-14
申请号：US17241142
申请日：2021-04-27
申请人： ASML NETHERLANDS B.V.
发明人： Joannes Jitse Venselaar , Anagnostis Tsiatmas , Samee Ur Rehman , Paul Christiaan Hinnen , Jean-Pierre Agnes Henricus Marie Vaessen , Nicolas Mauricio Weiss , Gonzalo Roberto Sanguinetti , Thomai Zacharopoulou , Martijn Maria Zaal
IPC分类号： G03F7/20 , G06F17/12
摘要： Methods of determining information about a patterning process. In a method, measurement data from a metrology process applied to each of a plurality of metrology targets on a substrate is obtained. The measurement data for each metrology target includes at least a first contribution and a second contribution. The first contribution is from a parameter of interest of a patterning process used to form the metrology target. The second contribution is from an error in the metrology process. The method further includes using the obtained measurement data from all of the plurality of metrology targets to obtain information about an error in the metrology process, and using the obtained information about the error in the metrology process to extract a value of the parameter of interest for each metrology target.

100. 发明申请

US20230048097A1 SIMULTANEOUS AND CONSISTENT HANDLING OF IMAGE DATA AND ASSOCIATED NOISE MODEL IN IMAGE PROCESSING AND IMAGE SYNTHESIS 有权
公开(公告)号：US20230048097A1
公开(公告)日：2023-02-16
申请号：US17815978
申请日：2022-07-29
申请人： Dotphoton AG
发明人： Christoph CLAUSEN , Bruno SANGUINETTI
IPC分类号： H04N5/367 , G06F17/12 , H04N5/347
摘要： A method for processing image data having noise and information, including: acquiring input raw image data having pixels of an image sensor used to take the image data, processing the input data, and outputting processed image-output data. The step of acquiring input data includes acquiring an input-noise model from the input data, and the step of processing the input raw image data includes a preprocessing operation and determining an output-noise model adapted to reflect noise in the output data, and producing output raw-image data consistent with the output-noise model, and the step of outputting the processed image data includes storing and/or transmitting the output raw image data and the output-noise model, which together form the output data, in a manner linking the output raw image data to the output-noise model, thereby allowing processing of the output data, as input data, such that the processing is adapted for pipeline processing.

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