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91. 发明授权

US06629120B1 Method and apparatus for performing a mask-driven interval multiplication operation 有权
标题翻译：用于执行掩模驱动间隔乘法运算的方法和装置
公开(公告)号：US06629120B1
公开(公告)日：2003-09-30
申请号：US09710454
申请日：2000-11-09
申请人： G. William Walster , Dmitri Chiriaev
发明人： G. William Walster , Dmitri Chiriaev
IPC分类号： G06F752
CPC分类号： G06F7/49989 , G06F7/523
摘要： One embodiment of the present invention provides a system that facilitates performing a mask-driven multiplication operation between arithmetic intervals within a computer system. The system first receives interval operands, including a first interval and a second interval, to be multiplied together to produce a resulting interval. Next, the system uses the operand values to create a mask. The system uses this mask to perform a multi-way branch to the code for the interval operands. In one embodiment of the present invention, creating the mask additionally involves: determining whether the first interval and/or second intervals are empty, and modifying the mask so the multi-way branch directs the execution flow of the program to appropriate code for this case. In one embodiment of the present invention, if the first interval is empty or if the second interval is empty, the multi-way branch directs the execution flow of the program to code that sets the resulting interval to be empty.
摘要翻译：本发明的一个实施例提供一种有助于在计算机系统内的运算间隔之间进行掩模驱动乘法运算的系统。系统首先接收包括第一间隔和第二间隔的间隔操作数，以便相乘以产生得到的间隔。接下来，系统使用操作数值创建掩码。系统使用该掩码对间隔操作数的代码执行多路分支。在本发明的一个实施例中，创建掩模还包括：确定第一间隔和/或第二间隔是否为空，以及修改掩码，使得多路分支将程序的执行流程引导到适用于该情况的代码。在本发明的一个实施例中，如果第一间隔为空或者如果第二间隔为空，则多路分支将程序的执行流引导到将所得间隔设置为空的代码。

92. 发明授权

US06625633B1 Divider and method with high radix 失效
标题翻译：高分子的分隔线和方法
公开(公告)号：US06625633B1
公开(公告)日：2003-09-23
申请号：US09585894
申请日：2000-06-01
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： G06F752
CPC分类号： G06F7/535 , G06F2207/5353
摘要： A high radix divider capable of reducing the size of the circuit of a quotient/remainder judgement unit in a radix 2k restoring division divider for finding a quotient k number of bits at a time, comparing multiples B, 2B, and 3B of a divisor B with a remainder R in parallel in two-input comparators and a three-input comparator and performing radix 4 division by finding a quotient 2 bits at a time. At this time, using a three-input comparator 313 in the comparison of 3B=(B+2B)≦R to realize comparison without the addition (B+2B), also, finding a new remainder Re in a three-input adder/subtractor for the simultaneous complex addition/subtraction R−(x+y) by a single ripple carry.
摘要翻译：一个高基数分频器，其能够减小基数2k恢复分频器中的商/余数判断单元的电路的大小，以便一次找到商k个位数，将B，2B和3B的倍数比较具有两个输入比较器并联的余数R的除数B和三输入比较器，并且一次通过寻找商2位执行小数4除法。此时，在比较3B =（B + 2B）<= R的情况下使用三输入比较器313来实现比较而没有加法（B + 2B），同样，在三输入加法器中找到新的余数Re /减法器，用于通过单个纹波进位同时复加数/减法R-（x + y）。

93. 发明授权

US06604121B1 Digital division device and method using a reduced-sized lookup table 失效
标题翻译：数字分割装置和方法使用缩小的查找表
公开(公告)号：US06604121B1
公开(公告)日：2003-08-05
申请号：US09451695
申请日：1999-11-30
申请人： Travis E. Ell , John C. Morris
发明人： Travis E. Ell , John C. Morris
IPC分类号： G06F752
CPC分类号： G06F7/535 , G06F2207/5356 , G11B5/59633
摘要： Devices and methods are provided for estimating a high-precision quotient using a smaller-than-conventional lookup table. The devices include a numerator register feeding a numerator value (as a succession of bits or words) into a forward signal path. The forward path includes a partial quotient generator, an accumulator, and a latch. The devices further include a feedback signal path emerging from the latch output, undergoing division by bit-shifting, and terminating as an input to the accumulator. A multiple divide implementation for use in a particular servo control system is also presented.
摘要翻译：提供了用于使用小于常规查找表来估计高精度商的装置和方法。这些装置包括一个分子寄存器，其将分子值（作为一连串的位或字）馈送到前向信号路径中。前向路径包括部分商发生器，累加器和锁存器。这些装置还包括从锁存器输出出现的反馈信号路径，经由位移移位并被终止为累加器的输入。还提出了用于特定伺服控制系统的多分割实现。

94. 发明授权

US06598064B1 Split multiplier array and method of operation 有权
标题翻译：拆分乘法器阵列和操作方法
公开(公告)号：US06598064B1
公开(公告)日：2003-07-22
申请号：US09477487
申请日：2000-01-04
申请人： Daniel W. Green
发明人： Daniel W. Green
IPC分类号： G06F752
CPC分类号： G06F7/5324 , G06F7/483 , G06F7/5312
摘要： A multiplier circuit for use in a data processor. The multiplier circuit contains a partial products generating circuit that receives a multiplicand value and a multiplier value and generates a group of partial products. The multiplier circuit also contains a split array for adding the partial products. A first summation array has a first group of adders that sum the even partial products to produce an even summation value. A second summation array has a second group of adders that sum the odd partial products to produce an odd summation value. The even and odd summation values are then summed to produce the output of the multiplier.
摘要翻译：用于数据处理器的乘法器电路。乘法器电路包含接收被乘数值和乘数值的部分乘积生成电路，并生成一组部分乘积。乘法器电路还包含用于添加部分乘积的分割数组。第一求和阵列具有第一组加法器，其将偶数部分乘积求和以产生偶求和值。第二求和阵列具有第二组加法器，其将奇数部分乘积求和以产生奇数和值。然后将偶和奇数求和值相加以产生乘数的输出。

95. 发明授权

US06578062B1 Method and circuit for digital division 有权
标题翻译：数字分割方法与电路
公开(公告)号：US06578062B1
公开(公告)日：2003-06-10
申请号：US09418168
申请日：1999-10-13
申请人： Cliff Gold , John Lee
发明人： Cliff Gold , John Lee
IPC分类号： G06F752
CPC分类号： G06F7/535
摘要： A method and apparatus for calculating a quotient from a dividend and a divisor, wherein the divisor can be represented as (2N+2M) where N is greater than M, and wherein the dividend comprises an X-bit binary number divisible by the divisor without a remainder. The values of N and M for the dividend are determined such that the divisor is equal to the value (2N+2M). The M-th through the (N−1)-th bits of the dividend are selected as lower order bits of the quotient. The (N−1)-th and the (2N−M−1)-th bits of the dividend are examined. If the (N−1)-th bit of the dividend is “1” and if the (2N−M−1)-th bit of the dividend is “0”, then one is subtracted from a value represented by the (2N−M)-th through the (X−1)-th bits of the dividend to obtain a result as higher order bits of the quotient. Otherwise, the (2N−M)-th through the (X−1)-th bits of the dividend are selected as higher order bits of the quotient. Finally, the higher order bits and the lower order bits are concatenated to obtain the quotient.
摘要翻译：一种用于从除数和除数计算商的方法和装置，其中除数可以表示为（2N + 2M）其中N大于M，并且其中除数包括除数除以除数除数的X位二进制数，剩下的确定用于分红的N和M的值，使得除数等于值（2N + 2M）。被除数的第M到第（N-1）位被选为商的低阶位。检查分红的第（N-1）和（2N-M-1）位。如果被除数的第（N-1）位为“1”，并且如果被除数的第（2N-M-1）位为“0”，则从由（2N -M）通过被除数的（X-1）位来获得作为商的较高阶位的结果。否则，选择被除数的（2N-M）到第（X-1）个比特作为商的高阶比特。最后，将高阶位和低阶位相连以获得商。

96. 发明授权

US06560624B1 Method of executing each of division and remainder instructions and data processing device using the method 失效
标题翻译：使用该方法执行每个分割和余数指令和数据处理设备的方法
公开(公告)号：US06560624B1
公开(公告)日：2003-05-06
申请号：US09477001
申请日：2000-01-03
申请人： Sugako Otani , Hiroyuki Kondo
发明人： Sugako Otani , Hiroyuki Kondo
IPC分类号： G06F752
CPC分类号： G06F7/535 , G06F9/3001 , G06F9/3016 , G06F9/30167 , G06F9/325 , G06F2207/3816 , G06F2207/5352
摘要： A data processing device comprises an instruction decoding unit for decoding a code of either a division instruction or a remainder instruction applied thereto, the instruction code having a size field for storing data size information. When a control unit receives a decoded result from the instruction decoding unit, the decoded result indicating the data size information stored in the size field of the instruction code, it presets a number of times that one loop iteration comprised of steps required for executing either the division instruction or the remainder instruction is to be carried out, based on the data size information. An ALU disposed within an arithmetic unit performs the loop iteration for either the division instruction or the remainder instruction only the number of times preset by the control unit.
摘要翻译：数据处理装置包括：指令解码单元，用于解码分配指令或应用于其的余数指令的代码，所述指令代码具有用于存储数据大小信息的大小字段。当控制单元从指令解码单元接收到解码结果时，指示存储在指令代码的大小字段中的数据大小信息的解码结果，它预设一次循环迭代的次数，该循环迭代包括执行任一将根据数据大小信息执行除法指令或余数指令。设置在算术单元内的ALU对分割指令或余数指令执行循环迭代，仅执行由控制单元预设的次数。

97. 发明授权

US06490607B1 Shared FP and SIMD 3D multiplier 有权
标题翻译：共享FP和SIMD 3D乘数
公开(公告)号：US06490607B1
公开(公告)日：2002-12-03
申请号：US09416401
申请日：1999-10-12
申请人： Stuart F. Oberman
发明人： Stuart F. Oberman
IPC分类号： G06F752
CPC分类号： G06F7/53 , G06F7/4991 , G06F7/49936 , G06F7/49963 , G06F7/49994 , G06F7/5338 , G06F7/5443 , G06F9/30036 , G06F9/3017 , G06F9/3804 , G06F9/3885 , G06F17/16 , G06F2207/3824 , G06F2207/3828
摘要： A multiplier configured to perform multiplication of both scalar floating point values (X×Y) and packed floating point values (i.e., X1×Y1 and X2×Y2). In addition, the multiplier may be configured to calculate X×Y−Z. The multiplier comprises selection logic for selecting source operands, a partial product generator, an adder tree, and two or more adders configured to sum the results from the adder tree to achieve a final result. The multiplier may also be configured to perform iterative multiplication operations to implement such arithmetical operations such as division and square root. The multiplier may be configured to generate two versions of the final result, one assuming there is an overflow, and another assuming there is not an overflow. A computer system and method for performing multiplication are also disclosed.
摘要翻译：配置为执行两个标量浮点值（XxY）和压缩浮点值（即X1xY1和X2xY2）的乘法的乘法器。此外，乘法器可以被配置为计算XxY-Z。乘法器包括用于选择源操作数的选择逻辑，部分乘积生成器，加法器树和被配置为对来自加法器树的结果求和以获得最终结果的两个或更多个加法器。乘法器还可以被配置为执行迭代乘法运算以实现诸如除法和平方根的算术运算。乘法器可以被配置为生成最终结果的两个版本，一个假设有溢出，另一个假设没有溢出。还公开了一种用于执行乘法的计算机系统和方法。

98. 发明授权

US06477556B1 Method and apparatus for arithmetic operation and recording medium of method of operation 有权
公开(公告)号：US06477556B1
公开(公告)日：2002-11-05
申请号：US09381869
申请日：1999-09-27
申请人： Mitsuru Matsui
发明人： Mitsuru Matsui
IPC分类号： G06F752
CPC分类号： G06F7/72 , G06Q10/04 , H04L9/3013
摘要： An integer Z101 is divided by an integer I102 to obtain a remainder R109. The integer I102 includes a polynomial of power of a basic operational unit of a computer. In this way, the integer I for divisor is limited based on the basic operational unit of the computer, thus a shift operation, which is required for a conventional operation method, can be eliminated. The remainder can be calculated by only addition and subtraction. Accordingly, a code size becomes compact and the remainder of the integer can be calculated at a high speed.

99. 发明授权

US06470372B1 Method for the performance of an integer division 有权
标题翻译：执行整数除法的方法
公开(公告)号：US06470372B1
公开(公告)日：2002-10-22
申请号：US09282370
申请日：1999-03-31
申请人： Guy Monier
发明人： Guy Monier
IPC分类号： G06F752
CPC分类号： G06F7/535 , G06F7/728
摘要： A method for performing in a modular arithmetic coprocessor an integer division of a first binary data element by a second binary data element. The result is obtained by making an iterative loop of operations including an integer division of the first data element by a most significant word of the second data element. A test is performed to determine if the result of the division performed corresponds to a word of the final result sought. The first data element is modified by subtracting from it a data element produced by multiplying the second data element by the word of the final result sought that has been previously produced.
摘要翻译：一种用于在模算术协处理器中执行第二二进制数据元素的第一二进制数据元素的整数除法的方法。结果是通过进行包括由第二数据元素的最高有效字的第一数据元素的整数除法的迭代循环来获得的。执行测试以确定执行的划分的结果是否与寻求的最终结果的单词相对应。通过从其中减去通过将第二数据元素乘以先前产生的最终结果的字来产生的数据元素来修改第一数据元素。

100. 发明授权

US06460064B1 Multiplier for operating n bits and n/2 bits and method therefor 失效
标题翻译：用于操作n位和n / 2位的乘数及其方法
公开(公告)号：US06460064B1
公开(公告)日：2002-10-01
申请号：US09280449
申请日：1999-03-30
申请人： Dong Sun Lee
发明人： Dong Sun Lee
IPC分类号： G06F752
CPC分类号： G06F7/5338 , G06F7/5318 , G06F2207/382
摘要： A multiplier for multiplying n bits and n/2 bits is disclosed, wherein a word multiplication is implemented by input of two words. The apparatus includes an encoder receiving the two words and pretreating one of the two words, a partial product generating unit outputting a partial product by multiplying the pretreated word and the unpretreated word from the encoder in accordance with a word control signal, a Wallace tree adder dividing the partial product into first and second output signals, and an adder receiving the first and second output signals and outputting word and byte multiplication output results in accordance with the word control signal.
摘要翻译：公开了用于乘以n位和n / 2位的乘法器，其中通过输入两个字来实现字乘法。该装置包括接收两个字并且预处理两个字中的一个的编码器，通过根据字控制信号将经预处理的字和未经处理的字乘以编码器的未经处理的字来输出部分乘积的部分乘积生成单元，华莱士树加法器将部分积分解为第一和第二输出信号，以及加法器，接收第一和第二输出信号，并根据字控制信号输出字和字乘法输出结果。

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