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    • 91. 发明申请
    • APPARATUS AND METHOD FOR A FREQUENCY SPECIFIC ANTENNA AND RECEIVER
    • 用于频率特定天线和接收机的装置和方法
    • US20140140709A1
    • 2014-05-22
    • US14133772
    • 2012-07-18
    • William A. Ganter
    • William A. Ganter
    • H04B10/61H01Q21/08
    • H04B10/6151H01Q21/08H04B7/10H04L5/04H04L27/06
    • A frequency specific receiver and method can receive a transmitted polarized carrier signal wave, the carrier signal wave having a carrier frequency, encoding one or more data bits, includes a synchronization filter to determine a reference time at 0π of the carrier signal wave from a forward wave received at a forward antenna element and a rear wave received at a rear antenna element, positioned apart from one another by a distance of ¼ wavelength of the transmitted carrier signal wave and oriented in a polarization direction of the transmitted carrier signal wave. A first A/D converter samples the forward wave at π/2, π, 3π/2 and 2π radians and a second A/D converter samples the rear wave at π/2, π, 3π/2 and 2π radians. A control processor decodes a value of the encoded data bit by calculation of an average computation and a calculation of a correlation computation.
    • 频率特定接收机和方法可以接收传输的偏振载波信号波,具有编码一个或多个数据比特的载波频率的载波信号波包括一个同步滤波器,用于确定0&pgr的基准时间; 在前方天线元件接收到的前向波的载波信号波和在后方天线元件接收到的后波,位于距离发射载波信号波的1/4波长的距离上, 传输载波信号波。 第一个A / D转换器以&pgr; / 2,&pgr; 3&pgr; / 2和2&pgr; 弧度和第二个A / D转换器以&pgr; / 2,&pgr; 3&pgr; / 2和2&pgr 弧度。 控制处理器通过计算平均计算和相关计算的计算来解码编码数据位的值。
    • 100. 发明授权
    • Single-wire asynchronous serial interface
    • 单线异步串行接口
    • US07672393B2
    • 2010-03-02
    • US11497601
    • 2006-08-02
    • Isaac Y. Chen
    • Isaac Y. Chen
    • H04L25/49
    • H04L25/4923H04L5/04H04L7/044
    • The present invention discloses a single-wire asynchronous serial interface, and a method for transmitting commands and data through one transmission wire, wherein the transmission wire is capable of transmitting signals of three level states. The disclosed interface comprises a signal level extraction circuit receiving signals transmitted through the wire and outputting logic or functional bits according to the received signals; a clock extraction circuit generating clock signals according to the functional bits, and a memory circuit controlled by the clock signals and storing the logic bits. The disclosed method comprises: using two of the level states to represent logic 0 and, logic 1, and the third of the states as a functional bit; and determining whether a group of signals is a command or data by the existence of a functional bit within the group.
    • 本发明公开了一种单线异步串行接口,以及一种通过一条传输线传输命令和数据的方法,其中传输线能传输三电平状态信号。 所公开的接口包括:信号电平提取电路,接收通过线路传输的信号,并根据接收到的信号输出逻辑或功能位; 根据功能位产生时钟信号的时钟提取电路和由时钟信号控制并存储逻辑比特的存储器电路。 所公开的方法包括:使用两个电平状态来表示逻辑0,逻辑1和第三状态作为功能位; 以及通过所述组内的功能位的存在来确定一组信号是否是命令或数据。