专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US08649511B2 Method and processing circuit for dealing with galois field computation 有权
标题翻译：用于处理伽罗瓦域计算的方法和处理电路
公开(公告)号：US08649511B2
公开(公告)日：2014-02-11
申请号：US12820148
申请日：2010-06-22
申请人： Chia-Yu Hung , Tsung-Li Yeh
发明人： Chia-Yu Hung , Tsung-Li Yeh
IPC分类号： H04K1/00
CPC分类号： G06F7/726 , H04L9/0631 , H04L2209/122
摘要： A method for dealing with Galois Field computation includes: providing an operating circuit which has at least a multiplicative inverse unit; and using the multiplicative inverse unit to execute at least a plurality of isomorphism maps for deriving a multiplicative inverse at a specific Galois Field corresponding to an input data, wherein the plurality of isomorphism maps include at least a change of basis.
摘要翻译：用于处理伽罗瓦域计算的方法包括：提供至少具有乘法逆单位的操作电路; 以及使用所述乘法逆单元执行至少多个同构映射，以在对应于输入数据的特定伽罗瓦域导出乘法逆，其中所述多个同构映射至少包括基础变化。

92. 发明申请

US20130336475A1 DEVICE 审中-公开
标题翻译：设备
公开(公告)号：US20130336475A1
公开(公告)日：2013-12-19
申请号：US13523020
申请日：2012-06-14
申请人： Yuji NAGAI , Taku KATO , Tatsuyuki MATSUSHITA
发明人： Yuji NAGAI , Taku KATO , Tatsuyuki MATSUSHITA
IPC分类号： H04L9/00
CPC分类号： H04L9/3242 , H04L9/3273 , H04L2209/122 , H04L2209/60 , H04N21/4182 , H04N21/4185
摘要： A device includes a first memory area being used to store a first key and secret identification information unique to the device; a second memory area being used to store encrypted secret identification information generated by encrypting the secret identification information; a first data generator configured to generate a second key by encrypting a host constant with the first key in AES operation; a second data generator configured to generate a session key by encrypting a random number with the second key in AES operation; a one-way function processor configured to generate an authentication information by processing the secret identification information with the session key in one-way function operation; and a data output interface configured to output the encrypted secret identification information and the authentication information to outside of the device.
摘要翻译：一种设备包括用于存储第一密钥的第一存储器区域和该设备唯一的秘密识别信息; 第二存储区域用于存储通过加密秘密识别信息而生成的加密的秘密识别信息; 第一数据生成器，被配置为通过在AES操作中用第一密钥加密主机常数来生成第二密钥; 第二数据发生器，被配置为通过在AES操作中用第二密钥加密随机数来生成会话密钥; 单向功能处理器，被配置为通过在单向功能操作中用所述会话密钥处理所述秘密识别信息来生成认证信息; 以及数据输出接口，被配置为将加密的秘密识别信息和认证信息输出到设备外部。

93. 发明申请

US20130326630A1 PRE-PROCESSOR FOR PHYSICAL LAYER SECURITY 审中-公开
标题翻译：物理层安全预处理器
公开(公告)号：US20130326630A1
公开(公告)日：2013-12-05
申请号：US13908000
申请日：2013-06-03
申请人： Whisper Communications, LLC
发明人： Cenk Argon
IPC分类号： G06F21/60
CPC分类号： H04L1/0059 , H04L1/0061 , H04L1/0065 , H04L1/0067 , H04L1/0071 , H04L9/0875 , H04L63/14 , H04L63/162 , H04L2209/12 , H04L2209/122
摘要： Systems and methods of secure data exchange are disclosed. One such method includes obtaining user data at a physical layer of a transmitter and securing the user data at the physical layer. The user data is secured by processing the user data with a series of non-recursive convolutional encoders interspersed with one or more bit-level permuters. The secured user data is transmitted.
摘要翻译：披露了安全数据交换的系统和方法。一种这样的方法包括在发射机的物理层处获取用户数据并将用户数据保护在物理层。用一系列非递归卷积编码器处理用户数据来保护用户数据，这些非递归卷积编码器散布有一个或多个位级别的置换器。发送安全用户数据。

94. 发明授权

US08594322B2 Encoding/decoding apparatus 有权
标题翻译：编码/解码装置
公开(公告)号：US08594322B2
公开(公告)日：2013-11-26
申请号：US11775749
申请日：2007-07-10
申请人： Guido Marco Bertoni , Jefferson Eugene Owen
发明人： Guido Marco Bertoni , Jefferson Eugene Owen
IPC分类号： H04L9/06 , H04L9/28
CPC分类号： H04L9/0637 , G09C1/00 , H04L2209/122 , H04L2209/125
摘要： An encoding/decoding apparatus comprises a central processing unit and an encryption/decryption accelerator coupled to the central processing unit. The accelerator comprises an input for input data to be encrypted/decrypted, an arithmetic logic unit coupled to said input for performing selectable operations on data obtained from said input data and an output for encrypted/decrypted data coupled to said arithmetic logic unit.
摘要翻译：编码/解码装置包括中央处理单元和耦合到中央处理单元的加密/解密加速器。加速器包括用于要加密/解密的输入数据的输入，耦合到所述输入的算术逻辑单元，用于对从所述输入数据获得的数据进行可选择操作，以及输出用于与所述算术逻辑单元耦合的加密/解密数据。

95. 发明申请

US20130178221A1 Method and Apparatus for Managing Transmit Power for Device-To-Device Communication 有权
标题翻译：用于管理设备到设备通信的发射功率的方法和装置
公开(公告)号：US20130178221A1
公开(公告)日：2013-07-11
申请号：US13782190
申请日：2013-03-01
申请人： MOTOROLA MOBILITY LLC
发明人： Hyejung Jung , Vijay Nangia
IPC分类号： H04W52/28
CPC分类号： H04W52/281 , H04L9/0844 , H04L9/3271 , H04L63/04 , H04L63/061 , H04L63/08 , H04L63/166 , H04L2209/122 , H04L2209/80 , H04W52/146 , H04W52/16 , H04W52/325 , H04W52/34 , H04W52/346 , H04W52/367 , H04W52/383
摘要： A method and apparatus for managing transmit power for device-to-device communication is provided. According to an embodiment of the invention, a UE uses a component carrier of one cell to engage in D2D communication. In parallel with its D2D communication, the UE uses one or more other component carriers of one or more other cells to engage in cellular communication. The UE configures its D2D transmit power as well as its cellular transmit power so that its total transmit power does not exceed the UEs maximum power limit, and so that the transmit power on a component carrier of a cell does not exceed the maximum power limit for the cell that provides the component carrier.
摘要翻译：提供了一种用于管理设备到设备通信的发射功率的方法和装置。根据本发明的实施例，UE使用一个小区的分量载波进行D2D通信。与其D2D通信并行，UE使用一个或多个其他小区的一个或多个其他分量载波进行蜂窝通信。 UE配置其D2D发射功率及其蜂窝发射功率，使得其总发射功率不超过UE最大功率限制，并且使得小区的分量载波上的发射功率不超过用于提供组件载体的单元。

96. 发明申请

US20120321075A1 FAULT-RESISTANT EXPONENTIATIONI ALGORITHM 有权
标题翻译：阻抗指数算法
公开(公告)号：US20120321075A1
公开(公告)日：2012-12-20
申请号：US13487457
申请日：2012-06-04
申请人： Marc Joye , Mohamed Karroumi
发明人： Marc Joye , Mohamed Karroumi
IPC分类号： H04L9/28
CPC分类号： G06F7/723 , G06F2207/7261 , G06F2207/7271 , H04L9/003 , H04L9/004 , H04L9/302 , H04L2209/122
摘要： A method for performing a m-ary right-to-left exponentiation using a base x, a secret exponent d and a modulus N, wherein m is a power of 2. A device having a processor and m+1 registers R[0]-R[m] in at least one memory: initializes register R[0] to h for a chosen value h, wherein the order of the value h is a divisor of m*(m−1)/2, register R[m] to x(m−1) and the registers other than R[0] and R[m] to the value h; updates register R[r] to R[r] times x, wherein r is the remainder of a division of d by (m−1) mod N; obtains a working exponent q that is the quotient of the division of d by (m−1); performs l iterations, starting at i=0, of: setting R[qi] to R[qi] times R[m] and raising R[m] to the power of m, where l is the length of q in base m and qi is the i-th digit of the representation of q in base m and ql−1 is non-zero; verifies the correctness of the result by checking that R[m] equals the product of registers R[0]-R[m−1] to the power of m−1; and outputs the product of R[l]j, where 1≦j≦m−1, only if the correctness is successfully verified.
摘要翻译：一种用于使用基数x，秘密指数d和模数N执行从右到左取幂的方法，其中m是2的幂。具有处理器并且m + 1寄存器R [0] 在至少一个存储器中的-R [m]：将寄存器R [0]初始化为h以选择值h，其中值h的顺序是m *（m-1）/ 2的除数，寄存器R [m ]到x（m-1）以及除R [0]和R [m]之外的寄存器到值h; 将寄存器R [r]更新为R [r]乘以x，其中r是d除以（m-1）mod N的余数的剩余部分; 得到一个工作指数q，即d（m-1）的除法的商; 从i = 0开始执行l次迭代，将R [qi]设置为R [qi]次R [m]，并将R [m]提高到m的幂，其中l是基本m中q的长度， qi是基数m中q的表示的第i位数，ql-1是非零; 通过检查R [m]等于寄存器R [0] -R [m-1]的乘积与m-1的幂来验证结果的正确性; 并且仅当正确性被成功验证时才输出R [1] j的乘积，其中1＆nlE; j＆nlE; m-1。

97. 发明申请

US20120201374A1 SYSTEMS AND METHODS FOR IMPLEMENTING BLOCK CIPHER ALGORITHMS ON ATTACKER-CONTROLLED SYSTEMS 审中-公开
标题翻译：用于在攻击者控制系统上实施块卡尔算法的系统和方法
公开(公告)号：US20120201374A1
公开(公告)日：2012-08-09
申请号：US13448385
申请日：2012-04-16
申请人： Mathieu Ciet , Augustin J. Farrugia , Filip Toma Paun
发明人： Mathieu Ciet , Augustin J. Farrugia , Filip Toma Paun
IPC分类号： H04L9/28
CPC分类号： H04L9/002 , H04L9/0618 , H04L9/0631 , H04L2209/043 , H04L2209/122 , H04L2209/125 , H04L2209/16
摘要： Systems and methods for an implementation of block cipher algorithms (e.g., AES) use lookup tables to obscure key information, increasing difficulty of reverse engineering efforts. The implementation encodes round key information into a first plurality of tables (T1), which when used for lookup operations also complete SubBytes operations, and output state in an encoded format. A Shiftrows operation is performed arithmetically on the output state. A second plurality of tables (T2) are used to perform a polynomial multiplication portion of MixColumns operation, and an XOR portion of MixColumns is performed arithmetically on the columns. Encoding from the T1 tables is made to match a decoding built into the T2 tables. Subsets of the T1 tables use the same T2 tables, reducing a memory footprint for the T2 tables. Multiple AES keys can be embedded in different sets of T1 tables that encode for the same set of T2 tables.
摘要翻译：用于实施块密码算法（例如，AES）的系统和方法使用查找表来掩盖关键信息，增加了逆向工程努力的难度。该实施方式将循环密钥信息编码到第一多个表（T1）中，当用于查找操作时也完成子字节操作，并且以编码格式输出状态。对输出状态进行算术运算。使用第二多个表（T2）来执行MixColumns操作的多项式乘法部分，并且对列进行算术运算的MixColumn的XOR部分。使T1表格的编码与T2表中内置的解码相匹配。 T1表的子集使用相同的T2表，减少了T2表的内存占用。可以将多个AES密钥嵌入到为同一组T2表编码的不同的T1表中。

98. 发明授权

US08009827B2 Encryption processing method and encryption processing device 有权
标题翻译：加密处理方法和加密处理装置
公开(公告)号：US08009827B2
公开(公告)日：2011-08-30
申请号：US11653879
申请日：2007-01-17
申请人： Toshio Okochi , Takashi Endo , Takashi Watanabe , Tatsuya Kameyama , Shunsuke Ota
发明人： Toshio Okochi , Takashi Endo , Takashi Watanabe , Tatsuya Kameyama , Shunsuke Ota
IPC分类号： H04L9/28
CPC分类号： H04L9/003 , G06F21/72 , G06F21/75 , G06F21/755 , H04L2209/122
摘要： An increase in safety from attacks by use of hardware-like methods by small-sized hardware is achieved. An encryption processing device includes a logical circuit capable of programmably setting logics for executing cipher processing, a memory that stores plural pieces of logical configuration information corresponding to an identical cipher processing algorithm, and a CPU that selectively sets plural logics corresponding to an identical cipher processing algorithm in the logical circuit. Even in processing using an identical cipher key, by changing the logic of the logical circuit for each processing, power consumption in cipher processing can be varied, and places a timing in which malfunctions occur can be varied. Moreover, an increase in the scale of hardware for realizing plural logics can be curbed.
摘要翻译：实现了通过使用小型硬件的类似硬件的方法的攻击来提高安全性。加密处理装置包括能够可编程地设置用于执行密码处理的逻辑的逻辑电路，存储与相同密码处理算法相对应的多条逻辑配置信息的存储器，以及选择性地设置与相同的密码处理对应的多个逻辑的CPU 算法在逻辑电路中。即使在使用相同的加密密钥的处理中，通过改变每个处理的逻辑电路的逻辑，可以改变密码处理中的功耗，并且可以改变发生故障的定时。此外，可以抑制用于实现多个逻辑的硬件规模的增加。

99. 发明申请

US20110176673A1 Encrypting apparatus 审中-公开
标题翻译：加密设备
公开(公告)号：US20110176673A1
公开(公告)日：2011-07-21
申请号：US13064460
申请日：2011-03-25
申请人： Dai Yamamoto , Kouichi Itoh , Masayoshi Isobe , Souichi Okada
发明人： Dai Yamamoto , Kouichi Itoh , Masayoshi Isobe , Souichi Okada
IPC分类号： H04L9/28
CPC分类号： H04L9/0643 , G09C1/00 , H04L2209/122
摘要： An encrypting apparatus includes a digest part using a SHA-2 algorithm of which a basic unit of operation is 32*Y (Y=1 or 2) bits. The digest part includes a shift register including a series of registers, and a predetermined number of adders performing an addition operation based on data stored in the shift register. The shift register includes a (32*Y)/X-bit register, where X=2k (k is an integer such that 1≦k≦4 when Y=1 and 1≦k≦5 when Y=2). Each of the adders has a data width of (32*Y)/X bits and performs the addition operation in each cycle in which the data stored in the shift register is shifted between the registers with the data width of (32*Y)/X bits.
摘要翻译：加密装置包括使用SHA-2算法的摘要部分，其基本操作单元是32×Y（Y = 1或2）位。摘要部分包括一个包括一系列寄存器的移位寄存器和一个预定数量的加法器，它们基于存储在移位寄存器中的数据执行加法运算。移位寄存器包括一个（32 * Y）/ X位寄存器，其中X = 2k（k是当Y = 1和1＆nlE; k＆nlE; 5，当Y = 2时，1＆nlE; k＆nlE; 4的整数）。每个加法器的数据宽度为（32×Y）/ X位，并且在存储在移位寄存器中的数据在数据宽度为（32 * Y）/ X位的寄存器之间移位的每个周期中执行相加操作， X位。

100. 发明申请

US20110173439A1 Stateless Cryptographic Protocol-based Hardware Acceleration 有权
标题翻译：基于无状态密码协议的硬件加速
公开(公告)号：US20110173439A1
公开(公告)日：2011-07-14
申请号：US13069221
申请日：2011-03-22
申请人： Randy Chou , Brijesh Nambiar
发明人： Randy Chou , Brijesh Nambiar
IPC分类号： H04L9/00 , H04L29/06
CPC分类号： H04W52/281 , H04L9/0844 , H04L9/3271 , H04L63/04 , H04L63/061 , H04L63/08 , H04L63/166 , H04L2209/122 , H04L2209/80
摘要： According to one embodiment of the invention, a method comprises an operation of commencing a first phrase and passing control of an authentication handshaking protocol. The first phase is commenced for establishing a secure communication path by a data path processor within a first network device. The first phrase comprises an exchange of data during an authentication handshaking protocol. The passing of control for authentication handshaking protocol by the data path processor to a control path processor is conducted to complete the authentication handshaking protocol.
摘要翻译：根据本发明的一个实施例，一种方法包括开始第一短语和通过认证握手协议的控制的操作。开始第一阶段以通过第一网络设备内的数据路径处理器建立安全的通信路径。第一个短语包括认证握手协议期间的数据交换。数据路径处理器对控制路径处理器的认证握手协议的控制被传递以完成认证握手协议。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式