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91. 发明申请

US20030174720A1 Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost 失效
标题翻译：光纤通道仲裁环路无缓冲开关电路，增加带宽，而不会显着增加成本
公开(公告)号：US20030174720A1
公开(公告)日：2003-09-18
申请号：US10348620
申请日：2003-01-21
发明人： Alistair D. Black , Kurt Chan
IPC分类号： H04L012/28
CPC分类号： H04L12/4637 , H04L12/40084 , H04L12/4625 , H04L49/103 , H04L49/15 , H04L49/254 , H04L49/30 , H04L49/357 , H04L49/40 , H04N21/4341
摘要： A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive is used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which. causes both ports to establish a data path through the backplane crossbar switch.
摘要翻译：公开了一种通过FCAL交换机传输数据的交换机，交换架构和过程。该开关使用多个开关控制电路，每个开关控制电路都耦合到一个FCAL网络，并且都连接到交叉开关。开关控制电路通过协议总线耦合在一起用于协调目的。每个FCAL循环都可能发生本地会话，并且通过交换机交叉的会话可以同时发生。 OPN原语用于在传输任何数据之前建立连接，从而无需开关控制电路中的缓冲存储器。每个OPN的目的地地址用于寻址每个交换机控制电路中的查找表，以确定目的地节点是否是本地的。如果没有，则查找目的地并在协议总线上进行连接请求。如果远程端口不忙，它会发回应答。导致两个端口通过背板交叉开关建立数据路径。

92. 发明授权

US06587477B1 Data transmitting apparatus, data receiving apparatus and data transmission control apparatus 有权
公开(公告)号：US06587477B1
公开(公告)日：2003-07-01
申请号：US09586915
申请日：2000-06-05
申请人： Hidetoshi Takeda , Hiroyuki Iitsuka , Takuya Nishimura , Masazumi Yamada
发明人： Hidetoshi Takeda , Hiroyuki Iitsuka , Takuya Nishimura , Masazumi Yamada
IPC分类号： H04J316
CPC分类号： H04L12/40058 , H04L12/40 , H04L12/40065 , H04L12/40071 , H04L12/40078 , H04L12/40084 , H04L12/403 , H04L12/6418 , H04L41/0896 , H04L47/10 , H04L47/13 , H04L47/22 , H04L47/2416 , H04L47/28 , H04L47/36 , H04L47/70 , H04N21/23602 , H04N21/2381 , H04N21/2402 , H04N21/4135 , H04N21/4147 , H04N21/4342 , H04N21/4344 , H04N21/4345 , H04N21/43632 , H04N21/44231
摘要： It is objected to simplify a procedure concerning bandwidth acquisition. Bandwidth acquiring means 809 of a second transmitting apparatus 814 acquires a bandwidth which was used by a first transmitting apparatus 806 by using a propagation delay identifier 804 read from first transmitting apparatus 806 and a maximum transmission data size 805 after stopping transmission of first transmitting apparatus 806. Each apparatus is composed so that transmission is started using this bandwidth and because returning and re-acquisition are not accompanied when the transmission is switched, necessary procedure can be simplified. Further, it is possible to effectively use the bandwidth by using a propagation delay identifier.

93. 发明申请

US20030120739A1 HALF DUPLEX LINK WITH ISOCHRONOUS AND ASYNCHRONOUS ARBITRATION 失效
标题翻译： HALF双重链接与异步和异步仲裁
公开(公告)号：US20030120739A1
公开(公告)日：2003-06-26
申请号：US09215559
申请日：1998-12-18
发明人： JOHN I. GARNEY , BRENT S. BAXTER
IPC分类号： G06F015/167
CPC分类号： H04L12/40058 , H04L12/40084 , H04L12/6418
摘要： Transactions are scheduled over a half duplex link between a first device, such as an IO unit, and a second device, such as a memory controller. Information flowing over the half duplex link is divided into a plurality of service periods, and an isochronous transaction, such as an isochronous memory read or write, is scheduled in a service period N if the isochronous transaction is ready to be serviced before service period N at the first or second device. An asynchronous transaction ready to be serviced at the first or second device, such as an asynchronous memory read or write, is scheduled if no isochronous transaction is ready to be serviced. The asynchronous transaction may be scheduled by (a) scheduling an asynchronous transaction ready to be serviced at the first device if no asynchronous transaction is ready to be serviced at the second device; (b) scheduling an asynchronous transaction ready to be serviced at the second device if no asynchronous transaction is ready to be serviced at the first device; and (c) scheduling an asynchronous transaction ready to be serviced at the first or second device, according to an arbitration algorithm, if asynchronous transactions are ready to be serviced at both the first device and the second device. The amount of buffer space available in the first or second device may also be used to schedule asynchronous transactions.
摘要翻译：事务被安排在诸如IO单元的第一设备和诸如存储器控制器的第二设备之间的半双工链路上。在半双工链路上流动的信息被划分为多个服务周期，并且如果在服务周期N之前准备服务等时事务，则在服务周期N中调度诸如同步存储器读或写等同步事务在第一或第二设备。如果没有等时事务准备好服务，则调度在第一或第二设备上准备好服务的异步事务，例如异步存储器读或写。可以通过以下方式来调度异步事务：（a）如果没有异步事务准备好在第二设备处服务，则调度准备好在第一设备处服务的异步事务; （b）如果没有异步事务准备好在第一设备处被服务，则调度准备在第二设备处服务的异步事务; 以及（c）如果异步事务准备好在第一设备和第二设备都被服务，则根据仲裁算法来调度准备好在第一或第二设备处服务的异步事务。第一或第二设备中可用的缓冲空间量也可用于调度异步事务。

94. 发明申请

US20030037161A1 Fly-by serial bus arbitration 有权
公开(公告)号：US20030037161A1
公开(公告)日：2003-02-20
申请号：US10231802
申请日：2002-08-30
发明人： William S. Duckwall , Michael D. Teener
IPC分类号： G06F015/16
CPC分类号： H04L12/40058 , H04L12/40084 , H04L12/40136 , H04L12/417 , H04L29/06 , H04L69/18 , H04L69/323 , H04L69/324
摘要： In a first embodiment, multi-speed concatenated packet strings are transmitted by a first node on a serial bus. To accommodate multi-speed packets, a speed signal is transmitted immediately prior to the packet. In a second embodiment, ACK-concatenation is used to allow a node to transmit a data packet immediately after transmitting an acknowledge signal on the bus. The data packet need not be related to the ACK packet. In a third embodiment, a node which receives a first data packet followed by a data end signal on a child port, concatenates a second data packet onto the first data packet during retransmission. The second data packet is also transmitted down the bus in the direction of the node which originally transmitted the first data packet.

95. 发明申请

US20020103947A1 Fly-by serial bus arbitration 失效
标题翻译：飞行串行总线仲裁
公开(公告)号：US20020103947A1
公开(公告)日：2002-08-01
申请号：US10059556
申请日：2002-01-28
发明人： William S. Duckwall , Michael D. Teener
IPC分类号： G06F013/00
CPC分类号： H04L12/40058 , H04L12/40084 , H04L12/40136 , H04L12/417 , H04L29/06 , H04L69/18 , H04L69/323 , H04L69/324
摘要： In a first embodiment, multi-speed concatenated packet strings are transmitted by a first node on a serial bus. To accommodate multi-speed packets, a speed signal is transmitted immediately prior to the packet. In a second embodiment, ACK-concatenation is used to allow a node to transmit a data packet immediately after transmitting an acknowledge signal on the bus. The data packet need not be related to the ACK packet. In a third embodiment, a node which receives a first data packet followed by a data end signal on a child port, concatenates a second data packet onto the first data packet during retransmission. The second data packet is also transmitted down the bus in the direction of the node which originally transmitted the first data packet
摘要翻译：在第一实施例中，多速串联分组串由串行总线上的第一节点发送。为了适应多速分组，在分组之前立即发送速度信号。在第二实施例中，使用ACK级联来允许节点在总线上发送确认信号之后立即发送数据分组。数据包不需要与ACK包相关。在第三实施例中，在子端口接收第一数据分组后跟数据结束信号的节点在重传期间将第二数据分组连接到第一数据分组上。第二数据分组也沿着最初发送第一数据分组的节点的方向沿总线发送

96. 发明申请

US20020029271A1 Method to control a network device in a network comprising several devices 失效
标题翻译：控制包括若干设备的网络中的网络设备的方法
公开(公告)号：US20020029271A1
公开(公告)日：2002-03-07
申请号：US09754152
申请日：2001-01-04
发明人： Andreas Schwager
IPC分类号： G06F015/16 , G06F015/173
CPC分类号： H04L12/40084 , H04J3/1682 , H04L12/2803 , H04L12/282 , H04L12/40065 , H04L12/40117 , H04L12/403 , H04L47/13 , H04L2012/40234
摘要： A method to control a network device in a network comprising several devices includes a first controller that operates to prevent another controller from performing an unwanted overtaking of a network device that is currently controlled by the first controller. In one embodiment, the first controller has the ability to reserve a controllable network device to thereby become its primary controller, so that the first controller may maintain control over the controllable network device against control demands of other controllers present in the network.
摘要翻译：一种用于控制包括若干设备的网络中的网络设备的方法包括：第一控制器，其操作以防止另一控制器执行当前由第一控制器控制的网络设备的不希望的超车。在一个实施例中，第一控制器具有保留可控网络设备从而成为其主控制器的能力，使得第一控制器可以保持对可控网络设备的控制，以抵抗存在于网络中的其他控制器的控制需求。

97. 发明授权

US06243386B1 Fibre channel learning bridge, learning half bridge, and protocol 有权
标题翻译：光纤通道学习桥，学习半桥和协议
公开(公告)号：US06243386B1
公开(公告)日：2001-06-05
申请号：US09395644
申请日：1999-09-14
申请人： Kurt Chan , Alistair D. Black
发明人： Kurt Chan , Alistair D. Black
IPC分类号： H04L1242
CPC分类号： H04L12/4637 , H04L12/40084 , H04L12/4625 , H04L49/103 , H04L49/15 , H04L49/254 , H04L49/30 , H04L49/357 , H04L49/40 , H04N21/4341
摘要： A learning half bridge and bridge for a Fibre Channel Arbitrated Loop and switching protocol. A half bridge can be coupled to a local loop segment and a remote loop segment. The half bridge includes transmit and receive ports implementing predetermined switching and conflict resolution rules and a memory storing a forwarding table. Typically the switching rules are implemented using state machines. The state machines implement a switching protocol that controls transitions between states which control switching connections, writing of data to memory and reading of data from memory and preemption of conflicting OPN primitives. Each half bridge includes a local return segment that can be switched by the state machines to bypass the remote loop segment if both the source node and destination node are on the local loop segment so as to make the local loop segment a complete Fibre Channel Arbitrated Loop. Each half bridge learns the locations of nodes by watching the direction of flow, the loop segment from which certain primitives arrived and sequence of OPN, RRDY and CLS primitives propagating on the loop segments and records data in the forwarding table in memory reflecting the locations of nodes about which conclusions have been drawn in accordance with learning rules. A learning bridge is comprised of two half bridges having their remote loop segments cross coupled. Full bridges can be combined with accelerated or nonaccelerated hubs. Conflicting OPNs are preempted using a highest priority address rule.
摘要翻译：用于光纤通道仲裁环路和交换协议的学习半桥和桥接器。半桥可以耦合到本地环路段和远程环路段。半桥包括实现预定切换和冲突解决规则的发送和接收端口以及存储转发表的存储器。通常，切换规则是使用状态机实现的。状态机实现了一种控制切换连接的状态之间的转换的切换协议，将数据写入存储器以及从存储器读取数据以及抢占冲突的OPN原语。每个半桥包括本地返回段，如果源节点和目标节点都在本地环路段上，则可以由状态机切换以绕过远程环路段，以使本地环路段成为完整的光纤通道仲裁环路。每个半桥通过观察流的方向，某些原语到达的循环段以及在循环段上传播的OPN，RRDY和CLS原语的序列，并将存储器中的数据记录在存储器中的位置来记录节点的位置，根据学习规则绘制结论的节点。一个学习桥由两个半桥组成，它们的远端环路交叉耦合。全桥可以与加速或非加速轮毂相结合。使用最高优先级的地址规则抢占冲突的OPN。

98. 发明授权

US6128316A Data transmitting apparatus data receiving apparatus and data transmission control apparatus 失效
标题翻译：数据发送装置数据接收装置和数据发送控制装置
公开(公告)号：US6128316A
公开(公告)日：2000-10-03
申请号：US945629
申请日：1998-04-23
申请人： Hidetoshi Takeda , Hiroyuki Iitsuka , Takuya Nishimura , Masazumi Yamada
发明人： Hidetoshi Takeda , Hiroyuki Iitsuka , Takuya Nishimura , Masazumi Yamada
IPC分类号： H04L12/24 , H04L12/40 , H04L12/403 , H04L12/54 , H04L12/64 , H04L12/801 , H04L12/805 , H04L12/815 , H04L12/841 , H04L12/853 , H04N5/00 , H04N7/24 , H04N7/52 , H04J3/16
CPC分类号： H04L12/40058 , H04L12/40 , H04L12/40065 , H04L12/40071 , H04L12/40078 , H04L12/40084 , H04L12/403 , H04L12/5695 , H04L12/6418 , H04L41/0896 , H04L47/10 , H04L47/13 , H04L47/22 , H04L47/2416 , H04L47/28 , H04L47/36 , H04N21/23602 , H04N21/2381 , H04N21/2402 , H04N21/4135 , H04N21/4147 , H04N21/4342 , H04N21/4344 , H04N21/4345 , H04N21/43632 , H04N21/44231
摘要： It is objected to simplify a procedure concerning bandwidth acquisition. Bandwidth acquiring means 809 of a second transmitting apparatus 814 acquires a bandwidth which was used by a first transmitting apparatus 806 by using a propagation delay identifier 804 read from first transmitting apparatus 806 and a maximum transmission data size 805 after stopping transmission of first transmitting apparatus 806. Each apparatus is composed so that transmission is started using this bandwidth and because returning and re-acquisition are not accompanied when the transmission is switched, necessary procedure can be simplified. Further, it is possible to effectively use the bandwidth by using a propagation delay identifier.
摘要翻译： PCT No.PCT / JP96 / 01123 Sec。 371日期：1998年4月23日 102（e）日期1998年4月23日PCT 1996年4月25日PCT公布。出版物WO96 / 34477 日期1996年10月31日反对简化带宽获取过程。第二发送装置814的带宽获取装置809在停止第一发送装置806的发送之后，通过使用从第一发送装置806读取的传播延迟标识符804和最大发送数据大小805获取由第一发送装置806使用的带宽每个装置的组合使得使用该带宽开始传输，并且由于在传输被切换时不伴随返回和重新获取，因此可以简化必要的程序。此外，可以通过使用传播延迟标识符来有效地使用带宽。

99. 发明授权

US5978379A Fiber channel learning bridge, learning half bridge, and protocol 失效
标题翻译：光纤通道学习桥，学习半桥和协议
公开(公告)号：US5978379A
公开(公告)日：1999-11-02
申请号：US786891
申请日：1997-01-23
申请人： Kurt Chan , Alistair D. Black
发明人： Kurt Chan , Alistair D. Black
IPC分类号： G06F13/36 , G06F13/00 , H04L12/46 , H04L12/56 , C06F13/14
CPC分类号： H04L12/4637 , H04L12/40084 , H04L12/4625 , H04L49/357 , H04N21/4341 , H04L49/103 , H04L49/15 , H04L49/254 , H04L49/30 , H04L49/40
摘要： A learning half bridge and bridge for a Fibre Channel Arbitrated Loop and switching protocol. A half bridge can be coupled to a local loop segment and a remote loop segment. The half bridge includes transmit and receive ports implementing predetermined switching and conflict resolution rules and a memory storing a forwarding table. Typically the switching rules are implemented using state machines. The state machines implement a switching protocol that controls transitions between states which control switching connections, writing of data to memory and reading of data from memory and preemption of conflicting OPN primitives. Each half bridge includes a local return segment that can be switched by the state machines to bypass the remote loop segment if both the source node and destination node are on the local loop segment so as to make the local loop segment a complete Fibre Channel Arbitrated Loop. Each half bridge learns the locations of nodes by watching the direction of flow, the loop segment from which certain primitives arrived and sequence of OPN, RRDY and CLS primitives propagating on the loop segments and records data in the forwarding table in memory reflecting the locations of nodes about which conclusions have been drawn in accordance with learning rules. A learning bridge is comprised of two half bridges having their remote loop segments cross coupled. Full bridges can be combined with accelerated or nonaccelerated hubs. Conflicting OPNs are preempted using a highest priority address rule.
摘要翻译：用于光纤通道仲裁环路和交换协议的学习半桥和桥接器。半桥可以耦合到本地环路段和远程环路段。半桥包括实现预定切换和冲突解决规则的发送和接收端口以及存储转发表的存储器。通常，切换规则是使用状态机实现的。状态机实现了一种控制切换连接的状态之间的转换的切换协议，将数据写入存储器以及从存储器读取数据以及抢占冲突的OPN原语。每个半桥包括本地返回段，如果源节点和目标节点都在本地环路段上，则可以由状态机切换以绕过远程环路段，以使本地环路段成为完整的光纤通道仲裁环路。每个半桥通过观察流的方向，某些原语到达的循环段以及在循环段上传播的OPN，RRDY和CLS原语的序列，并将存储器中的数据记录在存储器中的位置来记录节点的位置，根据学习规则绘制结论的节点。一个学习桥由两个半桥组成，它们的远程环路交叉耦合。全桥可以与加速或非加速轮毂相结合。使用最高优先级的地址规则抢占冲突的OPN。

100. 发明授权

US5802057A Fly-by serial bus arbitration 失效
公开(公告)号：US5802057A
公开(公告)日：1998-09-01
申请号：US565690
申请日：1995-12-01
申请人： William S. Duckwall , Michael D. Teener
发明人： William S. Duckwall , Michael D. Teener
IPC分类号： H04L12/40 , H04L12/64 , H04L29/06 , H04L29/08 , H04J3/22 , H04L12/417
CPC分类号： H04L12/40058 , H04L12/40084 , H04L12/40136 , H04L29/06 , H04L12/417 , H04L69/18 , H04L69/323 , H04L69/324
摘要： In a first embodiment, multi-speed concatenated packet strings are transmitted by a first node on a serial bus. To accommodate multi-speed packets, a speed signal is transmitted immediately prior to the packet. In a second embodiment, ACK-concatenation is used to allow a node to transmit a data packet immediately after transmitting an acknowledge signal on the bus. The data packet need not be related to the ACK packet. In a third embodiment, a node which receives a first data packet followed by a data end signal on a child port, concatenates a second data packet onto the first data packet during retransmission. The second data packet is also transmitted down the bus in the direction of the node which originally transmitted the first data packet.

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