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91. 发明授权

US06404364B1 Multistage converter employing digital dither 有权
标题翻译：采用数字抖动的多级转换器
公开(公告)号：US06404364B1
公开(公告)日：2002-06-11
申请号：US09645003
申请日：2000-08-24
申请人： H. Scott Fetterman , David Arthur Rich
发明人： H. Scott Fetterman , David Arthur Rich
IPC分类号： H03M120
CPC分类号： H03M1/0641 , H03M1/0695 , H03M1/167 , H03M1/442
摘要： A multistage converter and method for converting a sampled analog signal to a corresponding digital representation. Each stage of the converter receives an analog input signal and produces a partial digital output. A first stage receives the sampled analog signal as the analog input signal. Each stage provides a residue output, which is the analog input signal to a subsequent stage. The residue is the analog input signal to the stage, less the analog equivalent of the partial digital output from the stage, possibly with a gain change. A voltage range over which a sample of an analog signal can vary is defined by a lower limit and an upper limit. A lower comparator threshold is established within the voltage range. An upper comparator threshold is established within the voltage range, between the lower comparator threshold and the upper limit. The analog input to the stage is quantized based on the lower and upper comparator thresholds to generate a quantized sampled analog signal. When the quantizes sampled analog signal is between the lower and upper comparator thresholds, dither is added to the quantized sampled analog signal to produce the partial digital output. The partial digital outputs from each stage are provided to an error corrector circuit that removes redundancy and effects of the dither and generates the digital representation corresponding to the sampled analog input. The effect of dither is to improve the spurious free dynamic range (SFDR) of the digital representation of the analog input.
摘要翻译：一种用于将采样的模拟信号转换成相应的数字表示的多级转换器和方法。转换器的每个级接收模拟输入信号并产生部分数字输出。第一级接收采样的模拟信号作为模拟输入信号。每个阶段提供一个残留输出，这是后续阶段的模拟输入信号。剩余部分是到阶段的模拟输入信号，少于级的部分数字输出的模拟等效，可能增益变化。模拟信号的样本可以变化的电压范围由下限和上限定义。在电压范围内建立较低的比较器阈值。在较低的比较器阈值和上限之间的电压范围内建立较高的比较器阈值。基于较低和较高的比较器阈值对该级的模拟输入进行量化，以产生量化的采样模拟信号。当量化采样的模拟信号在下比较器阈值和上限比较器阈值之间时，抖动被加到量化的采样模拟信号上以产生部分数字输出。来自每个级的部分数字输出被提供给错误校正器电路，其消除抖动的冗余和影响，并产生对应于采样的模拟输入的数字表示。抖动的影响是改善模拟输入的数字表示的无杂散动态范围（SFDR）。

92. 发明授权

US06268814B1 Carrier-dependent dithering for analog-to-digital conversion 有权
标题翻译：用于模数转换的载波相关抖动
公开(公告)号：US06268814B1
公开(公告)日：2001-07-31
申请号：US09524152
申请日：2000-03-14
申请人： Arild T. Kolsrud
发明人： Arild T. Kolsrud
IPC分类号： H03M120
CPC分类号： H03M1/0641 , H03M1/12
摘要： An analog-to-digital converter (ADC) includes a dither signal generator configured to add an analog dither signal to the analog input signal of the ADC prior to digitization (i.e., quantization). The amplitude of the dither signal is selected based upon the power levels of one or more carriers present in the bandwidth for which the ADC is designed to operate. Addition of the dither signal to the input signal in the analog domain reduces quantization noise such as conversion spurs that result from non-linearities in the ADC transfer function.
摘要翻译：模数转换器（ADC）包括抖动信号发生器，其被配置为在数字化（即，量化）之前将模拟抖动信号添加到ADC的模拟输入信号。抖动信号的幅度基于存在于ADC被设计为工作的带宽中的一个或多个载波的功率电平来选择。将模拟信号中的抖动信号添加到模拟域中的输入信号可减少量化噪声，例如由ADC传递函数中的非线性引起的转换杂散。

93. 发明授权

US06172629B2 Multistage analog-to-digital converter employing dither 失效
标题翻译：采用抖动的多级模数转换器
公开(公告)号：US06172629B2
公开(公告)日：2001-01-09
申请号：US09025956
申请日：1998-02-19
申请人： H. Scott Fetterman
发明人： H. Scott Fetterman
IPC分类号： H03M120
CPC分类号： H03M1/0641 , H03M1/0695 , H03M1/167 , H03M1/442
摘要： There is disclosed, a converter for converting an input signal from one form to another. The converter includes a slicing circuit adapted to slice a signal into levels. The slicing circuit includes at least one threshold for establishing slicing levels. Dither is employed to vary at least one slicing level in the slicing circuit.
摘要翻译：公开了一种用于将输入信号从一种形式转换成另一种形式的转换器。该转换器包括一个适于将信号切割成电平的分片电路。切片电路包括用于建立切片电平的至少一个阈值。抖动被用于在切片电路中改变至少一个切片电平。

94. 发明授权

US5510790A Digital circuit for the introduction of dither into an analog signal 失效
标题翻译：用于将抖动引入模拟信号的数字电路
公开(公告)号：US5510790A
公开(公告)日：1996-04-23
申请号：US233283
申请日：1994-04-25
申请人： Gary S. Borgen , Christian L. Houlberg
发明人： Gary S. Borgen , Christian L. Houlberg
IPC分类号： H03M1/06 , H03M1/12 , H03M1/18
CPC分类号： H03M1/0641 , H03M1/12
摘要： An electronics circuit for accurately digitizing an analog audio, video orike data signal into a fourteen bit digital equivalent signal/words having thirteen data bits and a sign bit and then introducing a dither component into the digital equivalent signal. A Read Only Memory which generates an eight bit dither component to be added to a selected eight bits of each fourteen bit digital equivalent sample. The combination of an automatic gain control circuit and a data selector circuit is provided which selects eight of the thirteen data bits of each sample to supply to a binary adder which adds the dither component to each sample. The eight selected bits of each thirteen bit data sample provide optimum video, audio or like information for the sample. A binary adder is also provided to add the dither component to each bit sample before providing the resultant signal to a missile's telemetry system.
摘要翻译：一种电子电路，用于将模拟音频，视频或类似数据信号精确数字化为具有十三个数据位和符号位的十四位数字等效信号/字，然后将抖动分量引入数字等效信号。只读存储器，其产生要添加到每个十四位数字等效样本的所选八位的八位抖动分量。提供自动增益控制电路和数据选择器电路的组合，其选择每个采样的十三个数据位中的八个以提供给二进制加法器，该二进制加法器将抖动分量加到每个采样中。每个十三位数据样本的八个选定位提供样品的最佳视频，音频或类似信息。还提供了二进制加法器，用于在将所得到的信号提供给导弹的遥测系统之前，将抖动分量加到每个比特采样中。

95. 发明授权

US5448237A Digital circuit for the introduction of dither into an analog signal 失效
标题翻译：用于将抖动引入模拟信号的数字电路
公开(公告)号：US5448237A
公开(公告)日：1995-09-05
申请号：US209508
申请日：1994-03-08
申请人： Gary S. Borgen , Jeffrey J. Pacl
发明人： Gary S. Borgen , Jeffrey J. Pacl
IPC分类号： H03M1/06 , H03M1/12 , H03M1/20
CPC分类号： H03M1/0641 , H03M1/12
摘要： An electronics circuit for digitizing an analog audio or like data signal to a six bit digital equivalent signal and then introducing a dither component into the digital equivalent signal. The electronics circuit includes an Erasable Programmed Read Only Memory (EPROM) which generates a six bit dither component to be added to the digital equivalent signal. A binary adder adds a dither bit to each of the six bits of the digital equivalent signal and then provides a three bit equivalent digital signal. The three bit equivalent digital signal is then written in parallel into a first storage register, while one bit of the three bit digital equivalent signal is written into a second storage register. When a fuze active signal, which is input to the present invention, is a logic zero the first register is enabled for a read operation allowing the three bit equivalent digital data to be read from the first register to a parallel to serial converter which converts the data to a serial three bit digital format. When the fuze activate signal is a logic one the second register is enabled for a read operation allowing the one bit equivalent digital data to be read from the second register to the parallel to serial converter which converts the data to a serial one bit digital format.
摘要翻译：一种电子电路，用于将模拟音频或类似数据信号数字化为六位数字等效信号，然后将抖动分量引入数字等效信号。电子电路包括可擦除程序只读存储器（EPROM），其产生将被添加到数字等效信号的六位抖动分量。二进制加法器将数字等效信号的六位中的每一位加上抖动位，然后提供三位等效数字信号。然后将三位等效数字信号并行写入第一存储寄存器，而将三位数字等效信号的一位写入第二存储寄存器。当输入到本发明的引信有源信号为逻辑0时，第一寄存器用于读操作，允许将三位等效数字数据从第一寄存器读取到并行到串行转换器，并行转换器数据到串行三位数字格式。当引信激活信号为逻辑1时，第二个寄存器使能读操作，允许将一位等效的数字数据从第二寄存器读取到并行到串行转换器，并将其转换为串行一位数字格式。

96. 发明授权

US5245341A Video analog-to-digital converter 失效
标题翻译：视频模拟到数字转换器
公开(公告)号：US5245341A
公开(公告)日：1993-09-14
申请号：US828837
申请日：1992-01-31
申请人： Heinz Maeder
发明人： Heinz Maeder
IPC分类号： H04N1/405 , H03M1/06 , H03M1/12 , H04N5/14 , H04N7/24 , H04N7/26 , H04N11/04
CPC分类号： H03M1/0641 , H03M1/0624 , H04N19/90 , H04N5/14 , H04N7/24 , H03M1/12
摘要： This invention relates to a video analog-to-digital converter (ADC) and to a method of digitizing a video analog signal. The video ADC (2) comprises a clock for providing a clock signal (HZ) which clocks a horizontal line rate, dither generating means (10) for generating a dither pattern synchronized with the horizontal clock signal. A preferred dither pattern comprises a staircase sequence of voltage steps, the voltage level of each step being constant for at least one horizontal line. The video ADC further comprises combining means for combining the dither pattern with the analog video signal, digitizing means (4, 6) for converting the combined dither pattern and video signal to a sequence of digital values and correcting means (12) coupled to the digitizing means and the dither generating means for subtracting the dither pattern from the digitized sequence of values so as to generate a sequence of digital values which represent said analog video signal. By superimposing a dither pattern to the analog video signal at the horizontal line rate, the operating point of the ADC can be altered. As a result, step errors of the ADC do not occur at the same horizontal position on a line and are therefore less visible.In a preferred arrangement, the dither pattern is superimposed on a plurality of reference voltage levels generated by bias means (8) and which are applied to the digitizing means so that the dither pattern and the analog video signal are combined in the digitizing means.

97. 发明授权

US5034905A Divider circuit using analog-digital converter 失效
标题翻译：分频电路采用模拟数字转换器
公开(公告)号：US5034905A
公开(公告)日：1991-07-23
申请号：US353108
申请日：1989-05-17
申请人： Stefan Widdau , Rainer Kurz , Jakob Schelten , Andreas Scholz
发明人： Stefan Widdau , Rainer Kurz , Jakob Schelten , Andreas Scholz
IPC分类号： G01T1/164 , G06J1/00 , H03M1/06 , H03M1/12
CPC分类号： H03M1/0619 , G01T1/1642 , G06J1/00 , H03M1/0641 , H03M1/12
摘要： A circuit arrangement for dividing an input signal A by a signal B, for eple for use in localizing radiation detection, has a dividing analog-to-digital converter receiving an addition signal A+q.times.B as well as the divisor signal B to form the quotient (A+q.times.B)/B from which a digital random value r is subtracted, where r corresponds to q. The ADC can be a Flash ADC and the resulting circuit has good differential linearity and is fast.
摘要翻译：用于将输入信号A除以例如用于定位辐射检测的信号B的电路装置具有分频模数转换器，其接收加法信号A + q×B以及除数信号B以形成商（A + q×B）/ B，其中减去数字随机值r，其中r对应于q。 ADC可以是闪存ADC，并且所得电路具有良好的差分线性度，并且速度快。

98. 发明授权

US5012242A Input data processor for D/A converter utilizing dithering 失效
标题翻译：用于D / A转换器的输入数据处理器利用抖动
公开(公告)号：US5012242A
公开(公告)日：1991-04-30
申请号：US491992
申请日：1990-03-12
申请人： Junichi Yoshio , Masami Suzuki
发明人： Junichi Yoshio , Masami Suzuki
IPC分类号： H03M1/66 , H03M1/06 , H03M1/08
CPC分类号： H03M1/0641 , H03M1/0863 , H03M1/66
摘要： An input data processor of the present invention has a dither signal adder for adding a dither signal to digital data which corresponds to an alternating signal of the type which crosses the zero level each time the alternating signal varies from a maximum to a minimum (i.e., positive max to negative max). The resultant signal of the digital signal added to the dither signal is sent to a level shift circuit which shifts the digital data output from the adder to a positive or negative level, which has sufficient magnitude to prevent the signal from crossing the zero level during variation from max to min. By eliminating zero crossing with this shifting operation, the present invention prevents inversion of the MSB of the digital signal, which also prevents glitches in the analog output. These glitches were previously caused by inversion of the MSB.
摘要翻译：本发明的输入数据处理器具有一个抖动信号加法器，用于将每个交流信号从最大值变化到最小值的交变信号与对应于交叉信号的交替信号相对应的数字数据相加（即，正极大至负最大值）。添加到抖动信号的数字信号的结果信号被发送到电平移位电路，该电平移位电路将从加法器输出的数字数据移位到正或负电平，其具有足够的量级，以防止信号在变化期间跨越零电平从最大到最小。通过消除这种移位操作的过零点，本发明防止数字信号的MSB反转，这也防止模拟输出中的毛刺。这些毛刺以前是由MSB的反转造成的。

99. 发明授权

US4937576A Dither circuit responsive to zero input signal level 失效
标题翻译：抖动电路响应零输入信号电平
公开(公告)号：US4937576A
公开(公告)日：1990-06-26
申请号：US440175
申请日：1989-11-22
申请人： Junichi Yoshio , Masami Suzuki , Masami Tsuchida , Kiyoshi Iwai
发明人： Junichi Yoshio , Masami Suzuki , Masami Tsuchida , Kiyoshi Iwai
IPC分类号： H03M1/04 , H03M1/06 , H03M1/08 , H03M1/20 , H03M1/66
CPC分类号： H03M1/0641 , H03M1/66
摘要： A dither circuit including an adder for receiving an input signal and a dither signal which is generated by a dither signal generator, a level detection circuit for detecting the signal level of the input signal, and a dither control circuit for stopping the feeding of the dither signal to the adder when the level detection circuit detects that the signal level of the input signal is zero.
摘要翻译：一种抖动电路，包括用于接收输入信号的加法器和由抖动信号发生器产生的抖动信号，用于检测输入信号的信号电平的电平检测电路，以及用于停止抖动馈送的抖动控制电路当电平检测电路检测到输入信号的信号电平为零时，向加法器发信号。

100. 发明授权

US4845498A Wide dynamic range digital to analog conversion method and systems 失效
标题翻译：宽动态范围数模转换方法和系统
公开(公告)号：US4845498A
公开(公告)日：1989-07-04
申请号：US232562
申请日：1988-08-12
申请人： Mitsumasa Kubo , Tetsuro Araki
发明人： Mitsumasa Kubo , Tetsuro Araki
IPC分类号： H03M1/06 , H03M1/66
CPC分类号： H03M1/0641 , H03M1/66
摘要： A method and apparatus well suited for the conversion of a digitized audio signal into analog form with as wide a dynamic range as possible. A digital dither signal is added to a digital audio or like data signal to provide a digital data/dither signal. This digital data/dither signal and the digital dither signal are both converted into an analog data/dither signal and an analog dither signal respectively, and the analog dither signal is subtracted from the analog data/dither signal to obtain an analog data signal equivalent to the digital data signal. The level of the incoming digital data signal may be so high that when the digital dither signal is added thereto, the total level of the data/dither signal may exceed the capacity of the digital to analog converter in use. In that case the digital dither signal is either gated off or reduced in level, with the result that the digital to analog converter inputs either the data signal only or the data/dither signal having a total level not exceeding its capacity.
摘要翻译：一种非常适合将数字化音频信号转换成模拟形式并具有尽可能宽的动态范围的方法和装置。将数字抖动信号添加到数字音频或类似数据信号以提供数字数据/抖动信号。该数字数据/抖动信号和数字抖动信号分别转换为模拟数据/抖动信号和模拟抖动信号，并从模拟数据/抖动信号中减去模拟抖动信号，以获得等效于数字数据信号。输入数字数据信号的电平可能会很高，当加上数字抖动信号时，数据/抖动信号的总电平可能超过使用中的数模转换器的容量。在这种情况下，数字抖动信号被选通或降低电平，结果是数模转换器仅输入数据信号或数据/抖动信号的总电平不超过其容量。

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