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91. 发明申请

US20140103969A1 HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF DRIVING THE SAME 有权
标题翻译：高电子移动性晶体管及其驱动方法
公开(公告)号：US20140103969A1
公开(公告)日：2014-04-17
申请号：US13868579
申请日：2013-04-23
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Woo-chul JEON , Jong-seob KIM , Ki-yeol PARK , Young-hwan PARK , Jae-joon OH , Jong-bong HA , Jai-kwang SHIN
IPC分类号： H01L29/778 , H03K3/012
CPC分类号： H01L29/7781 , H01L29/0619 , H01L29/1066 , H01L29/2003 , H01L29/42316 , H01L29/66431 , H01L29/66462 , H01L29/778 , H01L29/7782 , H01L29/7786 , H03K3/012
摘要： According to example embodiments, a HEMT includes a channel layer, a channel supply layer on the channel layer, a source electrode and a drain electrode spaced apart on the channel layer, a depletion-forming layer on the channel supply layer, and a plurality of gate electrodes on the depletion-forming layer between the source electrode and the drain electrode. The channel supply layer is configured to induce a two-dimensional electron gas (2DEG) in the channel layer. The depletion-forming layer is configured to form a depletion region in the 2DEG. The plurality of gate electrodes include a first gate electrode and a second gate electrode spaced apart from each other.
摘要翻译：根据示例性实施例，HEMT包括沟道层，沟道层上的沟道供应层，在沟道层上隔开的源电极和漏电极，沟道供应层上的耗尽形成层，以及多个在源电极和漏电极之间的耗尽形成层上的栅电极。通道供给层被配置为在通道层中诱导二维电子气（2DEG）。耗尽形成层被配置为在2DEG中形成耗尽区。多个栅电极包括彼此间隔开的第一栅电极和第二栅电极。

92. 发明授权

US08680575B2 Semiconductor device and method of fabrication 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08680575B2
公开(公告)日：2014-03-25
申请号：US13016888
申请日：2011-01-28
申请人： Prashant Majhi , Jack Kavalieros , Wilman Tsai
发明人： Prashant Majhi , Jack Kavalieros , Wilman Tsai
IPC分类号： H01L33/00
CPC分类号： H01L29/7782 , H01L21/02381 , H01L21/02387 , H01L21/0245 , H01L21/02494 , H01L21/02505 , H01L21/02532 , H01L29/1075
摘要： Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers.
摘要翻译：本发明的实施例描述了具有缓冲结构的半导体器件和制造缓冲结构的方法。缓冲结构形成在衬底和量子阱层之间，以防止由于晶格失配而引起的衬底和量子阱层中的缺陷。缓冲结构包括形成在基板上的第一缓冲层，形成在第一缓冲层上的多个阻挡构件和形成在多个阻挡构件上的第二缓冲器。多个阻挡构件防止第二缓冲层直接沉积在整个第一缓冲层上，以便最小化晶格失配并防止第一和第二缓冲层中的缺陷。

93. 发明授权

US08669591B2 E-mode HFET device 有权
标题翻译： E型HFET器件
公开(公告)号：US08669591B2
公开(公告)日：2014-03-11
申请号：US13337753
申请日：2011-12-27
申请人： Fabio Alessio Marino , Paolo Menegoli
发明人： Fabio Alessio Marino , Paolo Menegoli
IPC分类号： H01L29/66
CPC分类号： H01L29/1075 , H01L29/1029 , H01L29/42316 , H01L29/42364 , H01L29/42372 , H01L29/7782 , H01L29/7787
摘要： The present invention describes a transistor based on a Hetero junction FET structure, where the metal gate has been replaced by a stack formed by a highly doped compound semiconductor and an insulating layer in order to achieve enhancement mode operation and at the same time drastically reduce the gate current leakage. The combination of the insulating layer with a highly doped semiconductor allows the tuning of the threshold voltage of the device at the desired value by simply changing the composition of the semiconductor layer forming the gate region and/or its doping allowing a higher degree of freedom. In one of the embodiment, a back-barrier layer and a heavily doped threshold tuning layer are used to suppress Short Channel Effect phenomena and to adjust the threshold voltage of the device at the desired value. The present invention can be realized both with polar and non-polar (or semi-polar) materials.
摘要翻译：本发明描述了一种基于异质结结FET结构的晶体管，其中金属栅极被由高掺杂化合物半导体和绝缘层形成的叠层替代，以便实现增强模式操作，并同时大大减少栅极电流泄漏。绝缘层与高掺杂半导体的组合允许通过简单地改变形成栅极区域的半导体层的组成和/或其掺杂允许更高的自由度来将器件的阈值电压调谐到所需的值。在一个实施例中，使用后阻挡层和重掺杂阈值调谐层来抑制短沟道效应现象并且将器件的阈值电压调整到期望值。本发明可以用极性和非极性（或半极性）材料实现。

94. 发明申请

US20130221409A1 SEMICONDUCTOR DEVICES WITH 2DEG AND 2DHG 有权
标题翻译：具有2DEG和2DHG的半导体器件
公开(公告)号：US20130221409A1
公开(公告)日：2013-08-29
申请号：US13812725
申请日：2011-06-07
申请人： Akira Nakajima , Sankara Narayanan Ekkanath Madathil
发明人： Akira Nakajima , Sankara Narayanan Ekkanath Madathil
IPC分类号： H01L29/778
CPC分类号： H01L29/7782 , H01L27/095 , H01L29/1029 , H01L29/2003 , H01L29/42316 , H01L29/7786 , H01L29/7787 , H01L29/782 , H01L29/872
摘要： A semiconductor device comprises three semiconductor layers. The semiconductor layers are arranged to form a 2DHG and a 2DEG separated by a polarization layer. The device comprises a plurality of electrodes: first and second electrodes electrically connected to the 2DHG so that current can flow between them via the 2DHG and a third electrode electrically connected to the 2DEG so that when a positive voltage is applied to the third electrode, with respect to at least one of the other electrodes, the 2DEG and the 2DHG will be at least partially depleted.
摘要翻译：半导体器件包括三个半导体层。半导体层被布置成形成由偏振层分离的2DHG和2DEG。该装置包括多个电极：电连接到2DHG的第一和第二电极，使得电流可以经由2DHG在它们之间流动，第三电极与2DEG电连接，使得当正电压施加到第三电极时，相对于至少一个其它电极，2DEG和2DHG将至少部分耗尽。

95. 发明申请

US20130099286A1 COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：化合物半导体器件及其制造方法
公开(公告)号：US20130099286A1
公开(公告)日：2013-04-25
申请号：US13617377
申请日：2012-09-14
申请人： Tadahiro Imada
发明人： Tadahiro Imada
IPC分类号： H01L29/778 , H01L29/66
CPC分类号： H01L29/7782 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L29/2003 , H01L29/205 , H01L29/42368 , H01L29/4238 , H01L29/517 , H01L29/518 , H01L29/66431 , H01L29/66462 , H01L29/778 , H01L29/7786 , H01L29/7788 , H01L29/7789 , H03F1/3247
摘要： A first GaN layer, a first AlGaN layer, a second GaN layer and a third GaN layer are formed in layers on a substrate. A second AlGaN layer is formed on the sidewall of an opening formed in the multilayer structure. A gate electrode is formed to fill an electrode trench in an insulating film. A portion of the insulating film between the gate electrode and the second AlGaN layer functions as a gate insulating film. A source electrode is formed above the gate electrode and a drain electrode is formed below the gate electrode. This configuration enables implementation of a miniatuarizable, reliable vertical HEMT that has a sufficiently high withstand voltage and high output power and is capable of a normally-off operation without problems that could otherwise result from the use of a p-type compound semiconductor.
摘要翻译：第一GaN层，第一AlGaN层，第二GaN层和第三GaN层在基板上形成为多层。第二AlGaN层形成在形成在多层结构中的开口的侧壁上。形成栅电极以填充绝缘膜中的电极沟槽。栅极电极和第二AlGaN层之间的绝缘膜的一部分用作栅极绝缘膜。源极电极形成在栅极电极的上方，漏电极形成在栅电极下方。该配置使得能够实现具有足够高的耐受电压和高输出功率的微型可靠的可靠的垂直HEMT，并且能够进行常关断操作而没有由于使用p型化合物半导体而导致的问题。

96. 发明授权

US08283653B2 Non-planar germanium quantum well devices 有权
标题翻译：非平面锗量子阱器件
公开(公告)号：US08283653B2
公开(公告)日：2012-10-09
申请号：US12646477
申请日：2009-12-23
申请人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
发明人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
IPC分类号： H01L29/06
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
摘要翻译：公开了用于形成非平面锗量子阱结构的技术。特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。栅极金属可以跨鳍片结构沉积。排水/源极区域可以形成在翅片结构的相应端部处。

97. 发明授权

US08217383B2 High hole mobility p-channel Ge transistor structure on Si substrate 有权
标题翻译：硅衬底上的高空穴迁移率p沟道Ge晶体管结构
公开(公告)号：US08217383B2
公开(公告)日：2012-07-10
申请号：US12876922
申请日：2010-09-07
申请人： Mantu K. Hudait , Suman Datta , Jack T. Kavalieros , Peter G. Tolchinsky
发明人： Mantu K. Hudait , Suman Datta , Jack T. Kavalieros , Peter G. Tolchinsky
IPC分类号： H01L29/775 , H01L29/20
CPC分类号： H01L29/7782 , H01L21/02381 , H01L21/02433 , H01L21/02463 , H01L21/02505 , H01L21/02546 , H01L21/02573 , H01L21/0262 , H01L29/267 , H01L29/66431
摘要： The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种在硅（“Si”）衬底上实现高空穴迁移率p沟道锗（“Ge”）晶体管结构的装置和方法。一个示例性装置可以包括包括GaAs成核层，第一GaAs缓冲层和第二GaAs缓冲层的缓冲层。该示例性装置还可以包括第二GaAs缓冲层上的底部阻挡层，并具有大于1.1eV的带隙，底部势垒上的Ge活性通道层，并且相对于底部势垒的价带偏移大于0.3 eV和Ge活性通道层上的AlAs顶部势垒，其中AlAs顶部势垒具有大于1.1eV的带隙。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

98. 发明授权

US08039892B2 Semiconductor device and a method for manufacturing a semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08039892B2
公开(公告)日：2011-10-18
申请号：US11740749
申请日：2007-04-26
申请人： Christian Foerster
发明人： Christian Foerster
IPC分类号： H01L29/94
CPC分类号： H01L29/165 , H01L29/1054 , H01L29/161 , H01L29/42368 , H01L29/66431 , H01L29/66666 , H01L29/7782 , H01L29/7828
摘要： A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a channel formation region formed on a side wall, having a mixture of a first semiconductor material with a first lattice constant, a second semiconductor material and carbon, the second semiconductor material having a second lattice constant differing from the first lattice constant.
摘要翻译：公开了一种半导体器件。在一个实施例中，半导体器件包括形成在侧壁上的沟道形成区域，具有第一半导体材料与第一晶格常数的混合物，第二半导体材料和碳，第二半导体材料具有不同于第一个晶格常数。

99. 发明申请

US20110156098A1 BUFFER STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION 有权
标题翻译：半导体器件的缓冲结构和制造方法
公开(公告)号：US20110156098A1
公开(公告)日：2011-06-30
申请号：US13016888
申请日：2011-01-28
申请人： Prashant Majhi , Jack Kavalieros , Wilman Tsai
发明人： Prashant Majhi , Jack Kavalieros , Wilman Tsai
IPC分类号： H01L29/12 , H01L21/20
CPC分类号： H01L29/7782 , H01L21/02381 , H01L21/02387 , H01L21/0245 , H01L21/02494 , H01L21/02505 , H01L21/02532 , H01L29/1075
摘要： Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers.
摘要翻译：本发明的实施例描述了具有缓冲结构的半导体器件和制造缓冲结构的方法。缓冲结构形成在衬底和量子阱层之间，以防止由于晶格失配而引起的衬底和量子阱层中的缺陷。缓冲结构包括形成在基板上的第一缓冲层，形成在第一缓冲层上的多个阻挡构件和形成在多个阻挡构件上的第二缓冲器。多个阻挡构件防止第二缓冲层直接沉积在整个第一缓冲层上，以便最小化晶格失配并防止第一和第二缓冲层中的缺陷。

100. 发明申请

US20110147706A1 TECHNIQUES AND CONFIGURATIONS TO IMPART STRAIN TO INTEGRATED CIRCUIT DEVICES 有权
标题翻译：对集成电路设备进行驱动的技术和配置
公开(公告)号：US20110147706A1
公开(公告)日：2011-06-23
申请号：US12646697
申请日：2009-12-23
申请人： Marko Radosavljevic , Gilbert Dewey , Niloy Mukherjee , Ravi Pillarisetty
发明人： Marko Radosavljevic , Gilbert Dewey , Niloy Mukherjee , Ravi Pillarisetty
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/7782 , B82Y10/00 , H01L29/66431 , H01L29/66462 , H01L29/7783 , H01L29/7848
摘要： Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a first barrier layer coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier layer, the quantum well channel comprising a first material having a first lattice constant, and a source structure coupled to the quantum well channel, the source structure comprising a second material having a second lattice constant, wherein the second lattice constant is different than the first lattice constant to impart a strain on the quantum well channel. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了为诸如水平场效应晶体管等集成电路器件施加应变的技术和配置。集成电路器件包括半导体衬底，与半导体衬底耦合的第一势垒层，耦合到第一势垒层的量子阱沟道，量子阱沟道包括具有第一晶格常数的第一材料和耦合到量子阱沟道，源结构包括具有第二晶格常数的第二材料，其中第二晶格常数不同于在量子阱沟道上施加应变的第一晶格常数。可以描述和/或要求保护其他实施例。

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