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91. 发明申请

US20120135596A1 METHOD OF REMOVING NANOCRYSTALS 审中-公开
标题翻译：去除纳米晶体的方法
公开(公告)号：US20120135596A1
公开(公告)日：2012-05-31
申请号：US12022800
申请日：2008-01-30
申请人： Sung-Taeg Kang , Jinmiao J. Shen
发明人： Sung-Taeg Kang , Jinmiao J. Shen
IPC分类号： H01L21/28 , H01L21/31
CPC分类号： H01L21/0206 , B82Y10/00 , B82Y40/00 , H01L21/30604 , H01L27/11521 , H01L29/40114 , H01L29/42328 , H01L29/42332 , H01L29/7881
摘要： A method for forming a semiconductor structure includes providing a semiconductor layer, forming nanocrystals over the semiconductor layer, and using a solution comprising pure water, hydrogen peroxide, and ammonium hydroxide to remove at least a portion of the nanocrystals. A ratio by volume of pure water to ammonium hydroxide of the solution may be equivalent to or less than a ratio by volume of 10:1 of pure water to ammonium hydroxide when ammonium hydroxide has a concentration of 29% ammonia by weight. The step of using the solution to remove the at least a portion of the nanocrystals may be performed at a temperature of 50 degrees Celsius or more.
摘要翻译：一种用于形成半导体结构的方法包括提供半导体层，在半导体层上形成纳米晶体，以及使用包含纯水，过氧化氢和氢氧化铵的溶液以除去至少一部分纳米晶体。当氢氧化铵的浓度为29重量％时，纯水与氢氧化铵的体积比可以等于或小于纯水与氢氧化铵的体积比为10:1。使用溶液去除至少一部分纳米晶体的步骤可以在50摄氏度或更高的温度下进行。

92. 发明申请

US20120126376A1 SILICON DIOXIDE FILM AND PROCESS FOR PRODUCTION THEREOF, COMPUTER-READABLE STORAGE MEDIUM, AND PLASMA CVD DEVICE 审中-公开
标题翻译：二氧化硅膜及其制造方法，计算机可读存储介质和等离子体CVD装置
公开(公告)号：US20120126376A1
公开(公告)日：2012-05-24
申请号：US13121606
申请日：2009-09-29
申请人： Minoru Honda , Toshio Nakanishi , Masayuki Kohno , Junya Miyahara
发明人： Minoru Honda , Toshio Nakanishi , Masayuki Kohno , Junya Miyahara
IPC分类号： H01L29/06 , C23C16/52 , H01L21/316 , C23C16/511
CPC分类号： H01L21/31612 , C23C16/402 , C23C16/511 , H01J37/32192 , H01J37/32238 , H01L21/02164 , H01L21/02274 , H01L29/40114 , H01L29/40117 , H01L29/513 , H01L29/518 , H01L29/792
摘要： To produce a silicon dioxide film having concentration of hydrogen atoms below or equal to 9.9×1020 atoms/cm3 in the silicon dioxide film, as measured by using secondary ion mass spectrometry (SIMS), a plasma CVD, which generate plasma by introducing microwaves into a process chamber by using a planar antenna having a plurality of apertures and forms a film, is performed by setting the pressure inside the process chamber within a range from 0.1 Pa to 6.7 Pa and by using a gas of a compound composed of silicon atoms and chlorine atoms and an oxygen containing gas.
摘要翻译：为了通过使用二次离子质谱法（SIMS）测量在二氧化硅膜中产生低于或等于9.9×1020原子/ cm3的氢原子浓度的二氧化硅膜，通过引入微波产生等离子体的等离子体CVD 通过使用具有多个孔并形成膜的平面天线的处理室，通过将处理室内的压力设定在0.1Pa〜6.7Pa的范围内，通过使用由硅原子构成的化合物的气体和氯原子和含氧气体。

93. 发明申请

US20120122310A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20120122310A1
公开(公告)日：2012-05-17
申请号：US13053421
申请日：2011-03-22
申请人： Eimei NAKAYAMA
发明人： Eimei NAKAYAMA
IPC分类号： H01L21/28
CPC分类号： H01L21/28123 , H01L21/0212 , H01L21/02274 , H01L21/31116 , H01L21/32139 , H01L27/11524 , H01L29/40114
摘要： In one embodiment, a method of manufacturing a semiconductor device includes forming a first to fourth films over a semiconductor substrate. The method further includes patterning the fourth film to form sparse and dense portions in which patterns of the fourth film are sparse and dense, respectively, and etching the third film by using the patterns of the fourth film as a mask. The method further includes etching the third film by using the patterns of the third and fourth films as a mask so as to expose the first film between the patterns in the sparse portion, and so as to partially remove the second film between the patterns in the dense portion so that the second film between the patterns remains. The method further includes forming a fifth film on the first film exposed in the sparse portion to have a first thickness, and on the second film remaining in the dense portion to have a second thickness smaller than the first thickness by using a CXFYHZ gas, where X, Y, and Z are integers of zero or more and satisfy 0
摘要翻译：在一个实施例中，制造半导体器件的方法包括在半导体衬底上形成第一至第四膜。该方法还包括对第四膜进行图案化以分别形成其中第四膜的图案稀疏且致密的稀疏致密部分，并且通过使用第四膜的图案作为掩模来蚀刻第三膜。该方法还包括通过使用第三和第四膜的图案作为掩模来蚀刻第三膜，以便在稀疏部分中的图案之间暴露第一膜，并且部分地去除第二膜中的图案之间的第二膜使得图案之间的第二薄膜残留。该方法还包括在稀疏部分上露出的具有第一厚度的第一膜上形成第五膜，并且通过使用CXFYHZ气体，在残留在致密部分中的第二膜厚度小于第一厚度的第二膜上， X，Y和Z为0以上的整数，满足0

94. 发明申请

US20120104482A1 SEMICONDUCTOR DEVICES HAVING A CONTROL GATE ELECTRODE INCLUDING A METAL LAYER FILLING A GAP BETWEEN ADJACENT FLOATING GATES AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：具有控制栅极电极的半导体器件，包括在相邻浮动栅之间填充间隙的金属层及其制造方法
公开(公告)号：US20120104482A1
公开(公告)日：2012-05-03
申请号：US13241387
申请日：2011-09-23
申请人： Hong-Suk KIM , Jun Kyu AHN , Jae Young AHN , Ki Hyun HWANG , Yong Hyun KWON
发明人： Hong-Suk KIM , Jun Kyu AHN , Jae Young AHN , Ki Hyun HWANG , Yong Hyun KWON
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L29/40114
摘要： A semiconductor device includes a device isolation layer defining a plurality of active regions of a semiconductor substrate, floating gates and a control gate electrode in which the lowermost part of the electrode is constituted by a metal layer. The control gate electrode crosses over the active regions. The floating gates are disposed between the control gate electrode and the active regions. The tops of the floating gates are disposed at a level above the level of the top of the device isolation layer such that a gap is defined between adjacent ones of the floating gates. A region of the gap is filled with the metal layer of the control gate electrode.
摘要翻译：半导体器件包括限定半导体衬底的多个有源区的器件隔离层，浮置栅极和控制栅电极，其中电极的最下部分由金属层构成。控制栅电极跨越有源区。浮置栅极设置在控制栅电极和有源区之间。浮置栅极的顶部设置在高于器件隔离层的顶部的高度的水平面上，使得在相邻的浮动栅极之间限定间隙。间隙的区域被控制栅电极的金属层填充。

95. 发明申请

US20120034752A1 METHODS OF FORMING A GATE STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：形成门结构的方法和使用其制造半导体器件的方法
公开(公告)号：US20120034752A1
公开(公告)日：2012-02-09
申请号：US13195521
申请日：2011-08-01
申请人： Weon-Hong KIM , Hyung-Suk Jung , Ha-Jin Lim
发明人： Weon-Hong KIM , Hyung-Suk Jung , Ha-Jin Lim
IPC分类号： H01L21/336 , H01L21/02
CPC分类号： H01L21/28247 , H01L21/823425 , H01L27/10873 , H01L27/11521 , H01L27/11568 , H01L29/40114 , H01L29/40117 , H01L29/78
摘要： In a method of forming a gate structure, a gate pattern including a gate insulation layer pattern and a gate electrode sequentially stacked on a substrate is formed. The gate electrode includes a metal. A first plasma process is performed on the gate pattern using a reaction gas to reduce an oxidized edge portion of the gate electrode. The reaction gas includes nitrogen. A spacer is formed on a sidewall of the gate pattern. A threshold voltage is adjusted by reducing the oxidized edge portion of the gate electrode. Therefore, a semiconductor device including the gate pattern has excellent electrical characteristics.
摘要翻译：在形成栅极结构的方法中，形成包括依次层叠在基板上的栅极绝缘层图案和栅电极的栅极图案。栅电极包括金属。使用反应气体对栅极图案进行第一等离子体处理，以减少栅电极的氧化边缘部分。反应气体包括氮气。在栅极图案的侧壁上形成间隔物。通过减小栅电极的氧化边缘部分来调节阈值电压。因此，包括栅极图案的半导体器件具有优异的电气特性。

96. 发明申请

US20120018888A1 SEMICONDUCTOR DEVICES AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：US20120018888A1
公开(公告)日：2012-01-26
申请号：US13179879
申请日：2011-07-11
申请人： Min Sung KO
发明人： Min Sung KO
IPC分类号： H01L29/49 , H01L21/762
CPC分类号： H01L29/40114 , H01L27/11521
摘要： A method of forming semiconductor devices includes stacking an insulating layer and a polysilicon layer over a semiconductor substrate, forming a region where nitrogen (N) is scattered in a place adjacent to a surface of the polysilicon layer within the polysilicon layer using a plasma method, and depositing a doped polysilicon layer on the polysilicon layer including the region where nitrogen (N) is scattered.
摘要翻译：一种形成半导体器件的方法包括在半导体衬底上堆叠绝缘层和多晶硅层，使用等离子体方法形成在多晶硅层内与多晶硅层表面相邻的位置上氮（N）散射的区域，以及在包括氮（N）被散射的区域的多晶硅层上沉积掺杂多晶硅层。

97. 发明申请

US20120012918A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120012918A1
公开(公告)日：2012-01-19
申请号：US13146882
申请日：2011-02-24
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7881 , H01L29/40114
摘要： A semiconductor structure and the method for manufacturing the same, wherein the structure comprising a semiconductor substrate: a flash memory device formed on the semiconductor substrate; wherein the flash memory device comprising: a channel region formed on the semiconductor substrate; a gate stack structure formed on the channel region; wherein the gate stack structure comprises: a first gate dielectric layer formed on the channel region; a first conductive layer formed on the first gate dielectric layer; a second gate dielectric layer formed on the first conductive layer; a second conductive layer formed on the second gate dielectric layer; a heavily doped first-conduction-type region and a heavily doped second-conduction-type region at both sides of the channel region respectively, wherein the first conduction type is opposite to the second conduction type in the type of conduction.
摘要翻译：一种半导体结构及其制造方法，其中所述结构包括半导体衬底：形成在所述半导体衬底上的闪存器件; 其中所述闪存器件包括：形成在所述半导体衬底上的沟道区; 形成在沟道区上的栅叠层结构; 其中所述栅堆叠结构包括：形成在所述沟道区上的第一栅介质层; 形成在所述第一栅极介电层上的第一导电层; 形成在所述第一导电层上的第二栅介质层; 形成在所述第二栅极介电层上的第二导电层; 分别在沟道区两侧的重掺杂的第一导电型区域和重掺杂的第二导电型区域，其中第一导电类型与导电类型中的第二导电类型相反。

98. 发明申请

US20110140192A1 METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH FLOATING POLYSILICON LAYER 审中-公开
标题翻译：制造具有浮选多晶硅层的双位结构单元的方法
公开(公告)号：US20110140192A1
公开(公告)日：2011-06-16
申请号：US12969563
申请日：2010-12-15
申请人： MIENO FUMITAKE
发明人： MIENO FUMITAKE
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/7887 , H01L21/28114 , H01L29/40114 , H01L29/66825
摘要： A method for forming a twin-bit cell structure is provided. The method includes providing a semiconductor substrate including a surface region. A gate dielectric layer is formed overlying the surface region. The method forms a polysilicon gate structure overlying the gate dielectric layer. In a specific embodiment, the method subjects the gate polysilicon structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the gate polysilicon structure. Preferably, an undercut region is allowed to be formed underneath the gate polysilicon structure. The method includes forming an undoped polysilicon material overlying the polysilicon gate structure including the undercut region and the gate dielectric layer. The undoped polysilicon material is subjected to a selective etching process to form an insert region in a portion of the undercut region while the insert region remains filled with the undoped polysilicon material.
摘要翻译：提供了一种形成双位单元结构的方法。该方法包括提供包括表面区域的半导体衬底。形成覆盖在表面区域上的栅介质层。该方法形成覆盖栅极电介质层的多晶硅栅极结构。在具体实施例中，该方法使栅极多晶硅结构进入氧化环境，以形成覆盖栅极多晶硅结构的第一氧化硅层。优选地，在栅极多晶硅结构下方形成底切区域。该方法包括形成覆盖多晶硅栅极结构的未掺杂多晶硅材料，该多晶硅栅极结构包括底切区域和栅极介电层。对未掺杂的多晶硅材料进行选择性蚀刻处理，以在底切区域的一部分中形成插入区域，同时插入区域保持填充未掺杂的多晶硅材料。

99. 发明申请

US20110136317A1 Semiconductor device, method of fabricating the same, and semicondutor module, electronic circuit board, and electronic system including the device 审中-公开
标题翻译：半导体装置及其制造方法，半导体模块，电子电路板以及包括该装置的电子系统
公开(公告)号：US20110136317A1
公开(公告)日：2011-06-09
申请号：US12659830
申请日：2010-03-23
申请人： Sang-Yeol Kang , Youn-Soo Kim , Jae-Hyoung Choi , Jae-Soon Lim , Min-Young Park , Suk-Jin Chung
发明人： Sang-Yeol Kang , Youn-Soo Kim , Jae-Hyoung Choi , Jae-Soon Lim , Min-Young Park , Suk-Jin Chung
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , H01L21/02183 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/0228 , H01L27/10852 , H01L29/40114
摘要： Example embodiments relate to a semiconductor device including an oxide dielectric layer and a non-oxide dielectric layer, a method of fabricating the device, and a semiconductor module, an electronic circuit board, and an electronic system including the device. The semiconductor device may include a lower electrode, an oxide dielectric layer disposed on the lower electrode, a non-oxide dielectric layer disposed on the oxide dielectric layer, and an upper electrode disposed on the non-oxide dielectric layer.
摘要翻译：示例性实施例涉及包括氧化物介电层和非氧化物介电层的半导体器件，制造器件的方法，以及包括该器件的半导体模块，电子电路板和电子系统。半导体器件可以包括下电极，设置在下电极上的氧化物介电层，设置在氧化物电介质层上的非氧化物介电层，以及设置在非氧化物介电层上的上电极。

100. 发明申请

US20110133266A1 Flash Memory Having a Floating Gate in the Shape of a Curved Section 审中-公开
标题翻译：闪存在曲面形状中具有浮动门
公开(公告)号：US20110133266A1
公开(公告)日：2011-06-09
申请号：US12629992
申请日：2009-12-03
申请人： Sanh Tang , Krishna K. Parat , Haitao Liu
发明人： Sanh Tang , Krishna K. Parat , Haitao Liu
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L27/11548 , H01L27/11521 , H01L27/11526 , H01L27/11543 , H01L29/40114 , H01L29/42324 , H01L29/66825
摘要： The floating gate of a flash memory may be formed with a flat lower surface facing a substrate and a curved upper surface facing the control gate. In some embodiments, such a device has improved capacitive coupling to the control gate and reduced capacitive coupling to its neighbors.
摘要翻译：闪存的浮动栅可以形成有面向基板的平坦的下表面和面对控制栅的弯曲的上表面。在一些实施例中，这种器件具有改善的与控制栅极的电容耦合并且减小与其邻居的电容耦合。

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